Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
7911d3f7 | 34 | #include <asm/mmu_context.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
e3f3541c | 36 | #include <asm/timer.h> |
d07bdfd3 PZ |
37 | #include <asm/desc.h> |
38 | #include <asm/ldt.h> | |
241771ef | 39 | |
de0428a7 KW |
40 | #include "perf_event.h" |
41 | ||
de0428a7 | 42 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 43 | |
de0428a7 | 44 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
45 | .enabled = 1, |
46 | }; | |
241771ef | 47 | |
a6673429 AL |
48 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
49 | ||
de0428a7 | 50 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 54 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 58 | |
ee06094f | 59 | /* |
cdd6c482 IM |
60 | * Propagate event elapsed time into the generic event. |
61 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
62 | * Returns the delta events processed. |
63 | */ | |
de0428a7 | 64 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 65 | { |
cc2ad4ba | 66 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 67 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 68 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 69 | int idx = hwc->idx; |
ec3232bd | 70 | s64 delta; |
ee06094f | 71 | |
15c7ad51 | 72 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
73 | return 0; |
74 | ||
ee06094f | 75 | /* |
cdd6c482 | 76 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
77 | * |
78 | * Our tactic to handle this is to first atomically read and | |
79 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 80 | * count to the generic event atomically: |
ee06094f IM |
81 | */ |
82 | again: | |
e7850595 | 83 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 84 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 85 | |
e7850595 | 86 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
87 | new_raw_count) != prev_raw_count) |
88 | goto again; | |
89 | ||
90 | /* | |
91 | * Now we have the new raw value and have updated the prev | |
92 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 93 | * (event-)time and add that to the generic event. |
ee06094f IM |
94 | * |
95 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 96 | * of the count. |
ee06094f | 97 | */ |
ec3232bd PZ |
98 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
99 | delta >>= shift; | |
ee06094f | 100 | |
e7850595 PZ |
101 | local64_add(delta, &event->count); |
102 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
103 | |
104 | return new_raw_count; | |
ee06094f IM |
105 | } |
106 | ||
a7e3ed1e AK |
107 | /* |
108 | * Find and validate any extra registers to set up. | |
109 | */ | |
110 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
111 | { | |
efc9f05d | 112 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
113 | struct extra_reg *er; |
114 | ||
efc9f05d | 115 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
116 | |
117 | if (!x86_pmu.extra_regs) | |
118 | return 0; | |
119 | ||
120 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
121 | if (er->event != (config & er->config_mask)) | |
122 | continue; | |
123 | if (event->attr.config1 & ~er->valid_mask) | |
124 | return -EINVAL; | |
338b522c KL |
125 | /* Check if the extra msrs can be safely accessed*/ |
126 | if (!er->extra_msr_access) | |
127 | return -ENXIO; | |
efc9f05d SE |
128 | |
129 | reg->idx = er->idx; | |
130 | reg->config = event->attr.config1; | |
131 | reg->reg = er->msr; | |
a7e3ed1e AK |
132 | break; |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
cdd6c482 | 137 | static atomic_t active_events; |
1b7b938f | 138 | static atomic_t pmc_refcount; |
4e935e47 PZ |
139 | static DEFINE_MUTEX(pmc_reserve_mutex); |
140 | ||
b27ea29c RR |
141 | #ifdef CONFIG_X86_LOCAL_APIC |
142 | ||
4e935e47 PZ |
143 | static bool reserve_pmc_hardware(void) |
144 | { | |
145 | int i; | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
149 | goto perfctr_fail; |
150 | } | |
151 | ||
948b1bb8 | 152 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 153 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
154 | goto eventsel_fail; |
155 | } | |
156 | ||
157 | return true; | |
158 | ||
159 | eventsel_fail: | |
160 | for (i--; i >= 0; i--) | |
41bf4989 | 161 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 162 | |
948b1bb8 | 163 | i = x86_pmu.num_counters; |
4e935e47 PZ |
164 | |
165 | perfctr_fail: | |
166 | for (i--; i >= 0; i--) | |
41bf4989 | 167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 168 | |
4e935e47 PZ |
169 | return false; |
170 | } | |
171 | ||
172 | static void release_pmc_hardware(void) | |
173 | { | |
174 | int i; | |
175 | ||
948b1bb8 | 176 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
177 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
178 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 179 | } |
4e935e47 PZ |
180 | } |
181 | ||
b27ea29c RR |
182 | #else |
183 | ||
184 | static bool reserve_pmc_hardware(void) { return true; } | |
185 | static void release_pmc_hardware(void) {} | |
186 | ||
187 | #endif | |
188 | ||
33c6d6a7 DZ |
189 | static bool check_hw_exists(void) |
190 | { | |
a5ebe0ba GD |
191 | u64 val, val_fail, val_new= ~0; |
192 | int i, reg, reg_fail, ret = 0; | |
193 | int bios_fail = 0; | |
68ab7476 | 194 | int reg_safe = -1; |
33c6d6a7 | 195 | |
4407204c PZ |
196 | /* |
197 | * Check to see if the BIOS enabled any of the counters, if so | |
198 | * complain and bail. | |
199 | */ | |
200 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 201 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
202 | ret = rdmsrl_safe(reg, &val); |
203 | if (ret) | |
204 | goto msr_fail; | |
a5ebe0ba GD |
205 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
206 | bios_fail = 1; | |
207 | val_fail = val; | |
208 | reg_fail = reg; | |
68ab7476 DZ |
209 | } else { |
210 | reg_safe = i; | |
a5ebe0ba | 211 | } |
4407204c PZ |
212 | } |
213 | ||
214 | if (x86_pmu.num_counters_fixed) { | |
215 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
216 | ret = rdmsrl_safe(reg, &val); | |
217 | if (ret) | |
218 | goto msr_fail; | |
219 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
220 | if (val & (0x03 << i*4)) { |
221 | bios_fail = 1; | |
222 | val_fail = val; | |
223 | reg_fail = reg; | |
224 | } | |
4407204c PZ |
225 | } |
226 | } | |
227 | ||
68ab7476 DZ |
228 | /* |
229 | * If all the counters are enabled, the below test will always | |
230 | * fail. The tools will also become useless in this scenario. | |
231 | * Just fail and disable the hardware counters. | |
232 | */ | |
233 | ||
234 | if (reg_safe == -1) { | |
235 | reg = reg_safe; | |
236 | goto msr_fail; | |
237 | } | |
238 | ||
4407204c | 239 | /* |
bffd5fc2 AP |
240 | * Read the current value, change it and read it back to see if it |
241 | * matches, this is needed to detect certain hardware emulators | |
242 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 243 | */ |
68ab7476 | 244 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
245 | if (rdmsrl_safe(reg, &val)) |
246 | goto msr_fail; | |
247 | val ^= 0xffffUL; | |
f285f92f RR |
248 | ret = wrmsrl_safe(reg, val); |
249 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 250 | if (ret || val != val_new) |
4407204c | 251 | goto msr_fail; |
33c6d6a7 | 252 | |
45daae57 IM |
253 | /* |
254 | * We still allow the PMU driver to operate: | |
255 | */ | |
a5ebe0ba GD |
256 | if (bios_fail) { |
257 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
258 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
259 | } | |
45daae57 IM |
260 | |
261 | return true; | |
4407204c PZ |
262 | |
263 | msr_fail: | |
264 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
65d71fe1 PZI |
265 | printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
266 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, | |
267 | reg, val_new); | |
45daae57 | 268 | |
4407204c | 269 | return false; |
33c6d6a7 DZ |
270 | } |
271 | ||
cdd6c482 | 272 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 273 | { |
6b099d9b | 274 | x86_release_hardware(); |
1b7b938f | 275 | atomic_dec(&active_events); |
4e935e47 PZ |
276 | } |
277 | ||
48070342 AS |
278 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
279 | { | |
280 | hw_perf_event_destroy(event); | |
281 | ||
282 | /* undo the lbr/bts event accounting */ | |
283 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
284 | } | |
285 | ||
85cf9dba RR |
286 | static inline int x86_pmu_initialized(void) |
287 | { | |
288 | return x86_pmu.handle_irq != NULL; | |
289 | } | |
290 | ||
8326f44d | 291 | static inline int |
e994d7d2 | 292 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 293 | { |
e994d7d2 | 294 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
295 | unsigned int cache_type, cache_op, cache_result; |
296 | u64 config, val; | |
297 | ||
298 | config = attr->config; | |
299 | ||
300 | cache_type = (config >> 0) & 0xff; | |
301 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
302 | return -EINVAL; | |
303 | ||
304 | cache_op = (config >> 8) & 0xff; | |
305 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
306 | return -EINVAL; | |
307 | ||
308 | cache_result = (config >> 16) & 0xff; | |
309 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
310 | return -EINVAL; | |
311 | ||
312 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
313 | ||
314 | if (val == 0) | |
315 | return -ENOENT; | |
316 | ||
317 | if (val == -1) | |
318 | return -EINVAL; | |
319 | ||
320 | hwc->config |= val; | |
e994d7d2 AK |
321 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
322 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
323 | } |
324 | ||
6b099d9b AS |
325 | int x86_reserve_hardware(void) |
326 | { | |
327 | int err = 0; | |
328 | ||
1b7b938f | 329 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 330 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 331 | if (atomic_read(&pmc_refcount) == 0) { |
6b099d9b AS |
332 | if (!reserve_pmc_hardware()) |
333 | err = -EBUSY; | |
334 | else | |
335 | reserve_ds_buffers(); | |
336 | } | |
337 | if (!err) | |
1b7b938f | 338 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
339 | mutex_unlock(&pmc_reserve_mutex); |
340 | } | |
341 | ||
342 | return err; | |
343 | } | |
344 | ||
345 | void x86_release_hardware(void) | |
346 | { | |
1b7b938f | 347 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
348 | release_pmc_hardware(); |
349 | release_ds_buffers(); | |
350 | mutex_unlock(&pmc_reserve_mutex); | |
351 | } | |
352 | } | |
353 | ||
48070342 AS |
354 | /* |
355 | * Check if we can create event of a certain type (that no conflicting events | |
356 | * are present). | |
357 | */ | |
358 | int x86_add_exclusive(unsigned int what) | |
359 | { | |
93472aff | 360 | int i; |
48070342 | 361 | |
93472aff PZ |
362 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
363 | mutex_lock(&pmc_reserve_mutex); | |
364 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
365 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
366 | goto fail_unlock; | |
367 | } | |
368 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
369 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 370 | } |
48070342 | 371 | |
93472aff PZ |
372 | atomic_inc(&active_events); |
373 | return 0; | |
48070342 | 374 | |
93472aff | 375 | fail_unlock: |
48070342 | 376 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 377 | return -EBUSY; |
48070342 AS |
378 | } |
379 | ||
380 | void x86_del_exclusive(unsigned int what) | |
381 | { | |
382 | atomic_dec(&x86_pmu.lbr_exclusive[what]); | |
1b7b938f | 383 | atomic_dec(&active_events); |
48070342 AS |
384 | } |
385 | ||
de0428a7 | 386 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
387 | { |
388 | struct perf_event_attr *attr = &event->attr; | |
389 | struct hw_perf_event *hwc = &event->hw; | |
390 | u64 config; | |
391 | ||
6c7e550f | 392 | if (!is_sampling_event(event)) { |
c1726f34 RR |
393 | hwc->sample_period = x86_pmu.max_period; |
394 | hwc->last_period = hwc->sample_period; | |
e7850595 | 395 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
396 | } |
397 | ||
398 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 399 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
400 | |
401 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 402 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
403 | |
404 | if (attr->config >= x86_pmu.max_events) | |
405 | return -EINVAL; | |
406 | ||
407 | /* | |
408 | * The generic map: | |
409 | */ | |
410 | config = x86_pmu.event_map(attr->config); | |
411 | ||
412 | if (config == 0) | |
413 | return -ENOENT; | |
414 | ||
415 | if (config == -1LL) | |
416 | return -EINVAL; | |
417 | ||
418 | /* | |
419 | * Branch tracing: | |
420 | */ | |
18a073a3 PZ |
421 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
422 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 423 | /* BTS is not supported by this architecture. */ |
6809b6ea | 424 | if (!x86_pmu.bts_active) |
c1726f34 RR |
425 | return -EOPNOTSUPP; |
426 | ||
427 | /* BTS is currently only allowed for user-mode. */ | |
428 | if (!attr->exclude_kernel) | |
429 | return -EOPNOTSUPP; | |
48070342 AS |
430 | |
431 | /* disallow bts if conflicting events are present */ | |
432 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
433 | return -EBUSY; | |
434 | ||
435 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
436 | } |
437 | ||
438 | hwc->config |= config; | |
439 | ||
440 | return 0; | |
441 | } | |
4261e0e0 | 442 | |
ff3fb511 SE |
443 | /* |
444 | * check that branch_sample_type is compatible with | |
445 | * settings needed for precise_ip > 1 which implies | |
446 | * using the LBR to capture ALL taken branches at the | |
447 | * priv levels of the measurement | |
448 | */ | |
449 | static inline int precise_br_compat(struct perf_event *event) | |
450 | { | |
451 | u64 m = event->attr.branch_sample_type; | |
452 | u64 b = 0; | |
453 | ||
454 | /* must capture all branches */ | |
455 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
456 | return 0; | |
457 | ||
458 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
459 | ||
460 | if (!event->attr.exclude_user) | |
461 | b |= PERF_SAMPLE_BRANCH_USER; | |
462 | ||
463 | if (!event->attr.exclude_kernel) | |
464 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
465 | ||
466 | /* | |
467 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
468 | */ | |
469 | ||
470 | return m == b; | |
471 | } | |
472 | ||
de0428a7 | 473 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 474 | { |
ab608344 PZ |
475 | if (event->attr.precise_ip) { |
476 | int precise = 0; | |
477 | ||
478 | /* Support for constant skid */ | |
c93dc84c | 479 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
480 | precise++; |
481 | ||
5553be26 | 482 | /* Support for IP fixup */ |
03de874a | 483 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 | 484 | precise++; |
72469764 AK |
485 | |
486 | if (x86_pmu.pebs_prec_dist) | |
487 | precise++; | |
5553be26 | 488 | } |
ab608344 PZ |
489 | |
490 | if (event->attr.precise_ip > precise) | |
491 | return -EOPNOTSUPP; | |
4b854900 YZ |
492 | } |
493 | /* | |
494 | * check that PEBS LBR correction does not conflict with | |
495 | * whatever the user is asking with attr->branch_sample_type | |
496 | */ | |
497 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
498 | u64 *br_type = &event->attr.branch_sample_type; | |
499 | ||
500 | if (has_branch_stack(event)) { | |
501 | if (!precise_br_compat(event)) | |
502 | return -EOPNOTSUPP; | |
503 | ||
504 | /* branch_sample_type is compatible */ | |
505 | ||
506 | } else { | |
507 | /* | |
508 | * user did not specify branch_sample_type | |
509 | * | |
510 | * For PEBS fixups, we capture all | |
511 | * the branches at the priv level of the | |
512 | * event. | |
513 | */ | |
514 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
515 | ||
516 | if (!event->attr.exclude_user) | |
517 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
518 | ||
519 | if (!event->attr.exclude_kernel) | |
520 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 521 | } |
ab608344 PZ |
522 | } |
523 | ||
e18bf526 YZ |
524 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
525 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
526 | ||
a072738e CG |
527 | /* |
528 | * Generate PMC IRQs: | |
529 | * (keep 'enabled' bit clear for now) | |
530 | */ | |
b4cdc5c2 | 531 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
532 | |
533 | /* | |
534 | * Count user and OS events unless requested not to | |
535 | */ | |
b4cdc5c2 PZ |
536 | if (!event->attr.exclude_user) |
537 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
538 | if (!event->attr.exclude_kernel) | |
539 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 540 | |
b4cdc5c2 PZ |
541 | if (event->attr.type == PERF_TYPE_RAW) |
542 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 543 | |
294fe0f5 AK |
544 | if (event->attr.sample_period && x86_pmu.limit_period) { |
545 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
546 | event->attr.sample_period) | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
9d0fcba6 | 550 | return x86_setup_perfctr(event); |
a098f448 RR |
551 | } |
552 | ||
241771ef | 553 | /* |
0d48696f | 554 | * Setup the hardware configuration for a given attr_type |
241771ef | 555 | */ |
b0a873eb | 556 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 557 | { |
4e935e47 | 558 | int err; |
241771ef | 559 | |
85cf9dba RR |
560 | if (!x86_pmu_initialized()) |
561 | return -ENODEV; | |
241771ef | 562 | |
6b099d9b | 563 | err = x86_reserve_hardware(); |
4e935e47 PZ |
564 | if (err) |
565 | return err; | |
566 | ||
1b7b938f | 567 | atomic_inc(&active_events); |
cdd6c482 | 568 | event->destroy = hw_perf_event_destroy; |
a1792cda | 569 | |
4261e0e0 RR |
570 | event->hw.idx = -1; |
571 | event->hw.last_cpu = -1; | |
572 | event->hw.last_tag = ~0ULL; | |
b690081d | 573 | |
efc9f05d SE |
574 | /* mark unused */ |
575 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
576 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
577 | ||
9d0fcba6 | 578 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
579 | } |
580 | ||
de0428a7 | 581 | void x86_pmu_disable_all(void) |
f87ad35d | 582 | { |
89cbc767 | 583 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
584 | int idx; |
585 | ||
948b1bb8 | 586 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
587 | u64 val; |
588 | ||
43f6201a | 589 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 590 | continue; |
41bf4989 | 591 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 592 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 593 | continue; |
bb1165d6 | 594 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 595 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 596 | } |
f87ad35d JSR |
597 | } |
598 | ||
a4eaf7f1 | 599 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 600 | { |
89cbc767 | 601 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 602 | |
85cf9dba | 603 | if (!x86_pmu_initialized()) |
9e35ad38 | 604 | return; |
1da53e02 | 605 | |
1a6e21f7 PZ |
606 | if (!cpuc->enabled) |
607 | return; | |
608 | ||
609 | cpuc->n_added = 0; | |
610 | cpuc->enabled = 0; | |
611 | barrier(); | |
1da53e02 SE |
612 | |
613 | x86_pmu.disable_all(); | |
b56a3802 | 614 | } |
241771ef | 615 | |
de0428a7 | 616 | void x86_pmu_enable_all(int added) |
f87ad35d | 617 | { |
89cbc767 | 618 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
619 | int idx; |
620 | ||
948b1bb8 | 621 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 622 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 623 | |
43f6201a | 624 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 625 | continue; |
984b838c | 626 | |
d45dd923 | 627 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
628 | } |
629 | } | |
630 | ||
51b0fe39 | 631 | static struct pmu pmu; |
1da53e02 SE |
632 | |
633 | static inline int is_x86_event(struct perf_event *event) | |
634 | { | |
635 | return event->pmu == &pmu; | |
636 | } | |
637 | ||
1e2ad28f RR |
638 | /* |
639 | * Event scheduler state: | |
640 | * | |
641 | * Assign events iterating over all events and counters, beginning | |
642 | * with events with least weights first. Keep the current iterator | |
643 | * state in struct sched_state. | |
644 | */ | |
645 | struct sched_state { | |
646 | int weight; | |
647 | int event; /* event index */ | |
648 | int counter; /* counter index */ | |
649 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 650 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
651 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
652 | }; | |
653 | ||
bc1738f6 RR |
654 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
655 | #define SCHED_STATES_MAX 2 | |
656 | ||
1e2ad28f RR |
657 | struct perf_sched { |
658 | int max_weight; | |
659 | int max_events; | |
cc1790cf PZ |
660 | int max_gp; |
661 | int saved_states; | |
b371b594 | 662 | struct event_constraint **constraints; |
1e2ad28f | 663 | struct sched_state state; |
bc1738f6 | 664 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
665 | }; |
666 | ||
667 | /* | |
668 | * Initialize interator that runs through all events and counters. | |
669 | */ | |
b371b594 | 670 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 671 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
672 | { |
673 | int idx; | |
674 | ||
675 | memset(sched, 0, sizeof(*sched)); | |
676 | sched->max_events = num; | |
677 | sched->max_weight = wmax; | |
cc1790cf | 678 | sched->max_gp = gpmax; |
b371b594 | 679 | sched->constraints = constraints; |
1e2ad28f RR |
680 | |
681 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 682 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
683 | break; |
684 | } | |
685 | ||
686 | sched->state.event = idx; /* start with min weight */ | |
687 | sched->state.weight = wmin; | |
688 | sched->state.unassigned = num; | |
689 | } | |
690 | ||
bc1738f6 RR |
691 | static void perf_sched_save_state(struct perf_sched *sched) |
692 | { | |
693 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
694 | return; | |
695 | ||
696 | sched->saved[sched->saved_states] = sched->state; | |
697 | sched->saved_states++; | |
698 | } | |
699 | ||
700 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
701 | { | |
702 | if (!sched->saved_states) | |
703 | return false; | |
704 | ||
705 | sched->saved_states--; | |
706 | sched->state = sched->saved[sched->saved_states]; | |
707 | ||
708 | /* continue with next counter: */ | |
709 | clear_bit(sched->state.counter++, sched->state.used); | |
710 | ||
711 | return true; | |
712 | } | |
713 | ||
1e2ad28f RR |
714 | /* |
715 | * Select a counter for the current event to schedule. Return true on | |
716 | * success. | |
717 | */ | |
bc1738f6 | 718 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
719 | { |
720 | struct event_constraint *c; | |
721 | int idx; | |
722 | ||
723 | if (!sched->state.unassigned) | |
724 | return false; | |
725 | ||
726 | if (sched->state.event >= sched->max_events) | |
727 | return false; | |
728 | ||
b371b594 | 729 | c = sched->constraints[sched->state.event]; |
4defea85 | 730 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
731 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
732 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 733 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
734 | if (!__test_and_set_bit(idx, sched->state.used)) |
735 | goto done; | |
736 | } | |
737 | } | |
cc1790cf | 738 | |
1e2ad28f RR |
739 | /* Grab the first unused counter starting with idx */ |
740 | idx = sched->state.counter; | |
15c7ad51 | 741 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
742 | if (!__test_and_set_bit(idx, sched->state.used)) { |
743 | if (sched->state.nr_gp++ >= sched->max_gp) | |
744 | return false; | |
745 | ||
4defea85 | 746 | goto done; |
cc1790cf | 747 | } |
1e2ad28f | 748 | } |
1e2ad28f | 749 | |
4defea85 PZ |
750 | return false; |
751 | ||
752 | done: | |
753 | sched->state.counter = idx; | |
1e2ad28f | 754 | |
bc1738f6 RR |
755 | if (c->overlap) |
756 | perf_sched_save_state(sched); | |
757 | ||
758 | return true; | |
759 | } | |
760 | ||
761 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
762 | { | |
763 | while (!__perf_sched_find_counter(sched)) { | |
764 | if (!perf_sched_restore_state(sched)) | |
765 | return false; | |
766 | } | |
767 | ||
1e2ad28f RR |
768 | return true; |
769 | } | |
770 | ||
771 | /* | |
772 | * Go through all unassigned events and find the next one to schedule. | |
773 | * Take events with the least weight first. Return true on success. | |
774 | */ | |
775 | static bool perf_sched_next_event(struct perf_sched *sched) | |
776 | { | |
777 | struct event_constraint *c; | |
778 | ||
779 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
780 | return false; | |
781 | ||
782 | do { | |
783 | /* next event */ | |
784 | sched->state.event++; | |
785 | if (sched->state.event >= sched->max_events) { | |
786 | /* next weight */ | |
787 | sched->state.event = 0; | |
788 | sched->state.weight++; | |
789 | if (sched->state.weight > sched->max_weight) | |
790 | return false; | |
791 | } | |
b371b594 | 792 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
793 | } while (c->weight != sched->state.weight); |
794 | ||
795 | sched->state.counter = 0; /* start with first counter */ | |
796 | ||
797 | return true; | |
798 | } | |
799 | ||
800 | /* | |
801 | * Assign a counter for each event. | |
802 | */ | |
b371b594 | 803 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 804 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
805 | { |
806 | struct perf_sched sched; | |
807 | ||
cc1790cf | 808 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
809 | |
810 | do { | |
811 | if (!perf_sched_find_counter(&sched)) | |
812 | break; /* failed */ | |
813 | if (assign) | |
814 | assign[sched.state.event] = sched.state.counter; | |
815 | } while (perf_sched_next_event(&sched)); | |
816 | ||
817 | return sched.state.unassigned; | |
818 | } | |
4a3dc121 | 819 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 820 | |
de0428a7 | 821 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 822 | { |
43b45780 | 823 | struct event_constraint *c; |
1da53e02 | 824 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 825 | struct perf_event *e; |
e979121b | 826 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
827 | struct hw_perf_event *hwc; |
828 | ||
829 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
830 | ||
c5362c0c MD |
831 | if (x86_pmu.start_scheduling) |
832 | x86_pmu.start_scheduling(cpuc); | |
833 | ||
1e2ad28f | 834 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 835 | cpuc->event_constraint[i] = NULL; |
79cba822 | 836 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 837 | cpuc->event_constraint[i] = c; |
43b45780 | 838 | |
1e2ad28f RR |
839 | wmin = min(wmin, c->weight); |
840 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
841 | } |
842 | ||
8113070d SE |
843 | /* |
844 | * fastpath, try to reuse previous register | |
845 | */ | |
c933c1a6 | 846 | for (i = 0; i < n; i++) { |
8113070d | 847 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 848 | c = cpuc->event_constraint[i]; |
8113070d SE |
849 | |
850 | /* never assigned */ | |
851 | if (hwc->idx == -1) | |
852 | break; | |
853 | ||
854 | /* constraint still honored */ | |
63b14649 | 855 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
856 | break; |
857 | ||
858 | /* not already used */ | |
859 | if (test_bit(hwc->idx, used_mask)) | |
860 | break; | |
861 | ||
34538ee7 | 862 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
863 | if (assign) |
864 | assign[i] = hwc->idx; | |
865 | } | |
8113070d | 866 | |
1e2ad28f | 867 | /* slow path */ |
b371b594 | 868 | if (i != n) { |
cc1790cf PZ |
869 | int gpmax = x86_pmu.num_counters; |
870 | ||
871 | /* | |
872 | * Do not allow scheduling of more than half the available | |
873 | * generic counters. | |
874 | * | |
875 | * This helps avoid counter starvation of sibling thread by | |
876 | * ensuring at most half the counters cannot be in exclusive | |
877 | * mode. There is no designated counters for the limits. Any | |
878 | * N/2 counters can be used. This helps with events with | |
879 | * specific counter constraints. | |
880 | */ | |
881 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
882 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
883 | gpmax /= 2; | |
884 | ||
b371b594 | 885 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 886 | wmax, gpmax, assign); |
b371b594 | 887 | } |
8113070d | 888 | |
2f7f73a5 | 889 | /* |
e979121b MD |
890 | * In case of success (unsched = 0), mark events as committed, |
891 | * so we do not put_constraint() in case new events are added | |
892 | * and fail to be scheduled | |
893 | * | |
894 | * We invoke the lower level commit callback to lock the resource | |
895 | * | |
896 | * We do not need to do all of this in case we are called to | |
897 | * validate an event group (assign == NULL) | |
2f7f73a5 | 898 | */ |
e979121b | 899 | if (!unsched && assign) { |
2f7f73a5 SE |
900 | for (i = 0; i < n; i++) { |
901 | e = cpuc->event_list[i]; | |
902 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 903 | if (x86_pmu.commit_scheduling) |
b371b594 | 904 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 | 905 | } |
8736e548 | 906 | } else { |
1da53e02 | 907 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
908 | e = cpuc->event_list[i]; |
909 | /* | |
910 | * do not put_constraint() on comitted events, | |
911 | * because they are good to go | |
912 | */ | |
913 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
914 | continue; | |
915 | ||
e979121b MD |
916 | /* |
917 | * release events that failed scheduling | |
918 | */ | |
1da53e02 | 919 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 920 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
921 | } |
922 | } | |
c5362c0c MD |
923 | |
924 | if (x86_pmu.stop_scheduling) | |
925 | x86_pmu.stop_scheduling(cpuc); | |
926 | ||
e979121b | 927 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
928 | } |
929 | ||
930 | /* | |
931 | * dogrp: true if must collect siblings events (group) | |
932 | * returns total number of events and error code | |
933 | */ | |
934 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
935 | { | |
936 | struct perf_event *event; | |
937 | int n, max_count; | |
938 | ||
948b1bb8 | 939 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
940 | |
941 | /* current number of events already accepted */ | |
942 | n = cpuc->n_events; | |
943 | ||
944 | if (is_x86_event(leader)) { | |
945 | if (n >= max_count) | |
aa2bc1ad | 946 | return -EINVAL; |
1da53e02 SE |
947 | cpuc->event_list[n] = leader; |
948 | n++; | |
949 | } | |
950 | if (!dogrp) | |
951 | return n; | |
952 | ||
953 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
954 | if (!is_x86_event(event) || | |
8113070d | 955 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
956 | continue; |
957 | ||
958 | if (n >= max_count) | |
aa2bc1ad | 959 | return -EINVAL; |
1da53e02 SE |
960 | |
961 | cpuc->event_list[n] = event; | |
962 | n++; | |
963 | } | |
964 | return n; | |
965 | } | |
966 | ||
1da53e02 | 967 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 968 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 969 | { |
447a194b SE |
970 | struct hw_perf_event *hwc = &event->hw; |
971 | ||
972 | hwc->idx = cpuc->assign[i]; | |
973 | hwc->last_cpu = smp_processor_id(); | |
974 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 975 | |
15c7ad51 | 976 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
977 | hwc->config_base = 0; |
978 | hwc->event_base = 0; | |
15c7ad51 | 979 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 980 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
981 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
982 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 983 | } else { |
73d6e522 RR |
984 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
985 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 986 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
987 | } |
988 | } | |
989 | ||
447a194b SE |
990 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
991 | struct cpu_hw_events *cpuc, | |
992 | int i) | |
993 | { | |
994 | return hwc->idx == cpuc->assign[i] && | |
995 | hwc->last_cpu == smp_processor_id() && | |
996 | hwc->last_tag == cpuc->tags[i]; | |
997 | } | |
998 | ||
a4eaf7f1 | 999 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1000 | |
a4eaf7f1 | 1001 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1002 | { |
89cbc767 | 1003 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1004 | struct perf_event *event; |
1005 | struct hw_perf_event *hwc; | |
11164cd4 | 1006 | int i, added = cpuc->n_added; |
1da53e02 | 1007 | |
85cf9dba | 1008 | if (!x86_pmu_initialized()) |
2b9ff0db | 1009 | return; |
1a6e21f7 PZ |
1010 | |
1011 | if (cpuc->enabled) | |
1012 | return; | |
1013 | ||
1da53e02 | 1014 | if (cpuc->n_added) { |
19925ce7 | 1015 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1016 | /* |
1017 | * apply assignment obtained either from | |
1018 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1019 | * | |
1020 | * step1: save events moving to new counters | |
1da53e02 | 1021 | */ |
19925ce7 | 1022 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1023 | event = cpuc->event_list[i]; |
1024 | hwc = &event->hw; | |
1025 | ||
447a194b SE |
1026 | /* |
1027 | * we can avoid reprogramming counter if: | |
1028 | * - assigned same counter as last time | |
1029 | * - running on same CPU as last time | |
1030 | * - no other event has used the counter since | |
1031 | */ | |
1032 | if (hwc->idx == -1 || | |
1033 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1034 | continue; |
1035 | ||
a4eaf7f1 PZ |
1036 | /* |
1037 | * Ensure we don't accidentally enable a stopped | |
1038 | * counter simply because we rescheduled. | |
1039 | */ | |
1040 | if (hwc->state & PERF_HES_STOPPED) | |
1041 | hwc->state |= PERF_HES_ARCH; | |
1042 | ||
1043 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1044 | } |
1045 | ||
c347a2f1 PZ |
1046 | /* |
1047 | * step2: reprogram moved events into new counters | |
1048 | */ | |
1da53e02 | 1049 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1050 | event = cpuc->event_list[i]; |
1051 | hwc = &event->hw; | |
1052 | ||
45e16a68 | 1053 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1054 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1055 | else if (i < n_running) |
1056 | continue; | |
1da53e02 | 1057 | |
a4eaf7f1 PZ |
1058 | if (hwc->state & PERF_HES_ARCH) |
1059 | continue; | |
1060 | ||
1061 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1062 | } |
1063 | cpuc->n_added = 0; | |
1064 | perf_events_lapic_init(); | |
1065 | } | |
1a6e21f7 PZ |
1066 | |
1067 | cpuc->enabled = 1; | |
1068 | barrier(); | |
1069 | ||
11164cd4 | 1070 | x86_pmu.enable_all(added); |
ee06094f | 1071 | } |
ee06094f | 1072 | |
245b2e70 | 1073 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1074 | |
ee06094f IM |
1075 | /* |
1076 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1077 | * To be called with the event disabled in hw: |
ee06094f | 1078 | */ |
de0428a7 | 1079 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1080 | { |
07088edb | 1081 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1082 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1083 | s64 period = hwc->sample_period; |
7645a24c | 1084 | int ret = 0, idx = hwc->idx; |
ee06094f | 1085 | |
15c7ad51 | 1086 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1087 | return 0; |
1088 | ||
ee06094f | 1089 | /* |
af901ca1 | 1090 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1091 | */ |
1092 | if (unlikely(left <= -period)) { | |
1093 | left = period; | |
e7850595 | 1094 | local64_set(&hwc->period_left, left); |
9e350de3 | 1095 | hwc->last_period = period; |
e4abb5d4 | 1096 | ret = 1; |
ee06094f IM |
1097 | } |
1098 | ||
1099 | if (unlikely(left <= 0)) { | |
1100 | left += period; | |
e7850595 | 1101 | local64_set(&hwc->period_left, left); |
9e350de3 | 1102 | hwc->last_period = period; |
e4abb5d4 | 1103 | ret = 1; |
ee06094f | 1104 | } |
1c80f4b5 | 1105 | /* |
dfc65094 | 1106 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1107 | */ |
1108 | if (unlikely(left < 2)) | |
1109 | left = 2; | |
241771ef | 1110 | |
e4abb5d4 PZ |
1111 | if (left > x86_pmu.max_period) |
1112 | left = x86_pmu.max_period; | |
1113 | ||
294fe0f5 AK |
1114 | if (x86_pmu.limit_period) |
1115 | left = x86_pmu.limit_period(event, left); | |
1116 | ||
245b2e70 | 1117 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f | 1118 | |
851559e3 YZ |
1119 | if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) || |
1120 | local64_read(&hwc->prev_count) != (u64)-left) { | |
1121 | /* | |
1122 | * The hw event starts counting from this event offset, | |
1123 | * mark it to be able to extra future deltas: | |
1124 | */ | |
1125 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1126 | |
851559e3 YZ |
1127 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
1128 | } | |
68aa00ac CG |
1129 | |
1130 | /* | |
1131 | * Due to erratum on certan cpu we need | |
1132 | * a second write to be sure the register | |
1133 | * is updated properly | |
1134 | */ | |
1135 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1136 | wrmsrl(hwc->event_base, |
948b1bb8 | 1137 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1138 | } |
e4abb5d4 | 1139 | |
cdd6c482 | 1140 | perf_event_update_userpage(event); |
194002b2 | 1141 | |
e4abb5d4 | 1142 | return ret; |
2f18d1e8 IM |
1143 | } |
1144 | ||
de0428a7 | 1145 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1146 | { |
0a3aee0d | 1147 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1148 | __x86_pmu_enable_event(&event->hw, |
1149 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1150 | } |
1151 | ||
b690081d | 1152 | /* |
a4eaf7f1 | 1153 | * Add a single event to the PMU. |
1da53e02 SE |
1154 | * |
1155 | * The event is added to the group of enabled events | |
1156 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1157 | */ |
a4eaf7f1 | 1158 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1159 | { |
89cbc767 | 1160 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1161 | struct hw_perf_event *hwc; |
1162 | int assign[X86_PMC_IDX_MAX]; | |
1163 | int n, n0, ret; | |
fe9081cc | 1164 | |
1da53e02 | 1165 | hwc = &event->hw; |
fe9081cc | 1166 | |
1da53e02 | 1167 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1168 | ret = n = collect_events(cpuc, event, false); |
1169 | if (ret < 0) | |
1170 | goto out; | |
53b441a5 | 1171 | |
a4eaf7f1 PZ |
1172 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1173 | if (!(flags & PERF_EF_START)) | |
1174 | hwc->state |= PERF_HES_ARCH; | |
1175 | ||
4d1c52b0 LM |
1176 | /* |
1177 | * If group events scheduling transaction was started, | |
0d2eb44f | 1178 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1179 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1180 | */ |
8f3e5684 | 1181 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1182 | goto done_collect; |
4d1c52b0 | 1183 | |
a072738e | 1184 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1185 | if (ret) |
24cd7f54 | 1186 | goto out; |
1da53e02 SE |
1187 | /* |
1188 | * copy new assignment, now we know it is possible | |
1189 | * will be used by hw_perf_enable() | |
1190 | */ | |
1191 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1192 | |
24cd7f54 | 1193 | done_collect: |
c347a2f1 PZ |
1194 | /* |
1195 | * Commit the collect_events() state. See x86_pmu_del() and | |
1196 | * x86_pmu_*_txn(). | |
1197 | */ | |
1da53e02 | 1198 | cpuc->n_events = n; |
356e1f2e | 1199 | cpuc->n_added += n - n0; |
90151c35 | 1200 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1201 | |
24cd7f54 PZ |
1202 | ret = 0; |
1203 | out: | |
24cd7f54 | 1204 | return ret; |
241771ef IM |
1205 | } |
1206 | ||
a4eaf7f1 | 1207 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1208 | { |
89cbc767 | 1209 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1210 | int idx = event->hw.idx; |
1211 | ||
a4eaf7f1 PZ |
1212 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1213 | return; | |
1214 | ||
1215 | if (WARN_ON_ONCE(idx == -1)) | |
1216 | return; | |
1217 | ||
1218 | if (flags & PERF_EF_RELOAD) { | |
1219 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1220 | x86_perf_event_set_period(event); | |
1221 | } | |
1222 | ||
1223 | event->hw.state = 0; | |
d76a0812 | 1224 | |
c08053e6 PZ |
1225 | cpuc->events[idx] = event; |
1226 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1227 | __set_bit(idx, cpuc->running); |
aff3d91a | 1228 | x86_pmu.enable(event); |
c08053e6 | 1229 | perf_event_update_userpage(event); |
a78ac325 PZ |
1230 | } |
1231 | ||
cdd6c482 | 1232 | void perf_event_print_debug(void) |
241771ef | 1233 | { |
2f18d1e8 | 1234 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1235 | u64 pebs, debugctl; |
cdd6c482 | 1236 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1237 | unsigned long flags; |
1e125676 IM |
1238 | int cpu, idx; |
1239 | ||
948b1bb8 | 1240 | if (!x86_pmu.num_counters) |
1e125676 | 1241 | return; |
241771ef | 1242 | |
5bb9efe3 | 1243 | local_irq_save(flags); |
241771ef IM |
1244 | |
1245 | cpu = smp_processor_id(); | |
cdd6c482 | 1246 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1247 | |
faa28ae0 | 1248 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1249 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1250 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1251 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1252 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1253 | ||
1254 | pr_info("\n"); | |
1255 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1256 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1257 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1258 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1259 | if (x86_pmu.pebs_constraints) { |
1260 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1261 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1262 | } | |
da3e606d AK |
1263 | if (x86_pmu.lbr_nr) { |
1264 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1265 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1266 | } | |
f87ad35d | 1267 | } |
7645a24c | 1268 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1269 | |
948b1bb8 | 1270 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1271 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1272 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1273 | |
245b2e70 | 1274 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1275 | |
a1ef58f4 | 1276 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1277 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1278 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1279 | cpu, idx, pmc_count); |
a1ef58f4 | 1280 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1281 | cpu, idx, prev_left); |
241771ef | 1282 | } |
948b1bb8 | 1283 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1284 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1285 | ||
a1ef58f4 | 1286 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1287 | cpu, idx, pmc_count); |
1288 | } | |
5bb9efe3 | 1289 | local_irq_restore(flags); |
241771ef IM |
1290 | } |
1291 | ||
de0428a7 | 1292 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1293 | { |
89cbc767 | 1294 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1295 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1296 | |
a4eaf7f1 PZ |
1297 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1298 | x86_pmu.disable(event); | |
1299 | cpuc->events[hwc->idx] = NULL; | |
1300 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1301 | hwc->state |= PERF_HES_STOPPED; | |
1302 | } | |
30dd568c | 1303 | |
a4eaf7f1 PZ |
1304 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1305 | /* | |
1306 | * Drain the remaining delta count out of a event | |
1307 | * that we are disabling: | |
1308 | */ | |
1309 | x86_perf_event_update(event); | |
1310 | hwc->state |= PERF_HES_UPTODATE; | |
1311 | } | |
2e841873 PZ |
1312 | } |
1313 | ||
a4eaf7f1 | 1314 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1315 | { |
89cbc767 | 1316 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1317 | int i; |
1318 | ||
2f7f73a5 SE |
1319 | /* |
1320 | * event is descheduled | |
1321 | */ | |
1322 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1323 | ||
90151c35 SE |
1324 | /* |
1325 | * If we're called during a txn, we don't need to do anything. | |
1326 | * The events never got scheduled and ->cancel_txn will truncate | |
1327 | * the event_list. | |
c347a2f1 PZ |
1328 | * |
1329 | * XXX assumes any ->del() called during a TXN will only be on | |
1330 | * an event added during that same TXN. | |
90151c35 | 1331 | */ |
8f3e5684 | 1332 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
90151c35 SE |
1333 | return; |
1334 | ||
c347a2f1 PZ |
1335 | /* |
1336 | * Not a TXN, therefore cleanup properly. | |
1337 | */ | |
a4eaf7f1 | 1338 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1339 | |
1da53e02 | 1340 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1341 | if (event == cpuc->event_list[i]) |
1342 | break; | |
1343 | } | |
1da53e02 | 1344 | |
c347a2f1 PZ |
1345 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1346 | return; | |
26e61e89 | 1347 | |
c347a2f1 PZ |
1348 | /* If we have a newly added event; make sure to decrease n_added. */ |
1349 | if (i >= cpuc->n_events - cpuc->n_added) | |
1350 | --cpuc->n_added; | |
1da53e02 | 1351 | |
c347a2f1 PZ |
1352 | if (x86_pmu.put_event_constraints) |
1353 | x86_pmu.put_event_constraints(cpuc, event); | |
1354 | ||
1355 | /* Delete the array entry. */ | |
b371b594 | 1356 | while (++i < cpuc->n_events) { |
c347a2f1 | 1357 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1358 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1359 | } | |
c347a2f1 | 1360 | --cpuc->n_events; |
1da53e02 | 1361 | |
cdd6c482 | 1362 | perf_event_update_userpage(event); |
241771ef IM |
1363 | } |
1364 | ||
de0428a7 | 1365 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1366 | { |
df1a132b | 1367 | struct perf_sample_data data; |
cdd6c482 IM |
1368 | struct cpu_hw_events *cpuc; |
1369 | struct perf_event *event; | |
11d1578f | 1370 | int idx, handled = 0; |
9029a5e3 IM |
1371 | u64 val; |
1372 | ||
89cbc767 | 1373 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1374 | |
2bce5dac DZ |
1375 | /* |
1376 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1377 | * inside the nmi handler. As a result, the unmasking was pushed | |
1378 | * into all the nmi handlers. | |
1379 | * | |
1380 | * This generic handler doesn't seem to have any issues where the | |
1381 | * unmasking occurs so it was left at the top. | |
1382 | */ | |
1383 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1384 | ||
948b1bb8 | 1385 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1386 | if (!test_bit(idx, cpuc->active_mask)) { |
1387 | /* | |
1388 | * Though we deactivated the counter some cpus | |
1389 | * might still deliver spurious interrupts still | |
1390 | * in flight. Catch them: | |
1391 | */ | |
1392 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1393 | handled++; | |
a29aa8a7 | 1394 | continue; |
63e6be6d | 1395 | } |
962bf7a6 | 1396 | |
cdd6c482 | 1397 | event = cpuc->events[idx]; |
a4016a79 | 1398 | |
cc2ad4ba | 1399 | val = x86_perf_event_update(event); |
948b1bb8 | 1400 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1401 | continue; |
962bf7a6 | 1402 | |
9e350de3 | 1403 | /* |
cdd6c482 | 1404 | * event overflow |
9e350de3 | 1405 | */ |
4177c42a | 1406 | handled++; |
fd0d000b | 1407 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1408 | |
07088edb | 1409 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1410 | continue; |
1411 | ||
a8b0ca17 | 1412 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1413 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1414 | } |
962bf7a6 | 1415 | |
9e350de3 PZ |
1416 | if (handled) |
1417 | inc_irq_stat(apic_perf_irqs); | |
1418 | ||
a29aa8a7 RR |
1419 | return handled; |
1420 | } | |
39d81eab | 1421 | |
cdd6c482 | 1422 | void perf_events_lapic_init(void) |
241771ef | 1423 | { |
04da8a43 | 1424 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1425 | return; |
85cf9dba | 1426 | |
241771ef | 1427 | /* |
c323d95f | 1428 | * Always use NMI for PMU |
241771ef | 1429 | */ |
c323d95f | 1430 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1431 | } |
1432 | ||
9326638c | 1433 | static int |
9c48f1c6 | 1434 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1435 | { |
14c63f17 DH |
1436 | u64 start_clock; |
1437 | u64 finish_clock; | |
e8a923cc | 1438 | int ret; |
14c63f17 | 1439 | |
1b7b938f AS |
1440 | /* |
1441 | * All PMUs/events that share this PMI handler should make sure to | |
1442 | * increment active_events for their events. | |
1443 | */ | |
cdd6c482 | 1444 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1445 | return NMI_DONE; |
4177c42a | 1446 | |
e8a923cc | 1447 | start_clock = sched_clock(); |
14c63f17 | 1448 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1449 | finish_clock = sched_clock(); |
14c63f17 DH |
1450 | |
1451 | perf_sample_event_took(finish_clock - start_clock); | |
1452 | ||
1453 | return ret; | |
241771ef | 1454 | } |
9326638c | 1455 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1456 | |
de0428a7 KW |
1457 | struct event_constraint emptyconstraint; |
1458 | struct event_constraint unconstrained; | |
f87ad35d | 1459 | |
148f9bb8 | 1460 | static int |
3f6da390 PZ |
1461 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1462 | { | |
1463 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1464 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
90413464 | 1465 | int i, ret = NOTIFY_OK; |
3f6da390 PZ |
1466 | |
1467 | switch (action & ~CPU_TASKS_FROZEN) { | |
1468 | case CPU_UP_PREPARE: | |
90413464 SE |
1469 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1470 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1471 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1472 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1473 | break; |
1474 | ||
1475 | case CPU_STARTING: | |
1476 | if (x86_pmu.cpu_starting) | |
1477 | x86_pmu.cpu_starting(cpu); | |
1478 | break; | |
1479 | ||
7fdba1ca | 1480 | case CPU_ONLINE: |
90413464 SE |
1481 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1482 | kfree(cpuc->kfree_on_online[i]); | |
1483 | cpuc->kfree_on_online[i] = NULL; | |
1484 | } | |
7fdba1ca PZ |
1485 | break; |
1486 | ||
3f6da390 PZ |
1487 | case CPU_DYING: |
1488 | if (x86_pmu.cpu_dying) | |
1489 | x86_pmu.cpu_dying(cpu); | |
1490 | break; | |
1491 | ||
b38b24ea | 1492 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1493 | case CPU_DEAD: |
1494 | if (x86_pmu.cpu_dead) | |
1495 | x86_pmu.cpu_dead(cpu); | |
1496 | break; | |
1497 | ||
1498 | default: | |
1499 | break; | |
1500 | } | |
1501 | ||
b38b24ea | 1502 | return ret; |
3f6da390 PZ |
1503 | } |
1504 | ||
12558038 CG |
1505 | static void __init pmu_check_apic(void) |
1506 | { | |
1507 | if (cpu_has_apic) | |
1508 | return; | |
1509 | ||
1510 | x86_pmu.apic = 0; | |
1511 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1512 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1513 | |
1514 | /* | |
1515 | * If we have a PMU initialized but no APIC | |
1516 | * interrupts, we cannot sample hardware | |
1517 | * events (user-space has to fall back and | |
1518 | * sample via a hrtimer based software event): | |
1519 | */ | |
1520 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1521 | ||
12558038 CG |
1522 | } |
1523 | ||
641cc938 JO |
1524 | static struct attribute_group x86_pmu_format_group = { |
1525 | .name = "format", | |
1526 | .attrs = NULL, | |
1527 | }; | |
1528 | ||
8300daa2 JO |
1529 | /* |
1530 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1531 | * out of events_attr attributes. | |
1532 | */ | |
1533 | static void __init filter_events(struct attribute **attrs) | |
1534 | { | |
3a54aaa0 SE |
1535 | struct device_attribute *d; |
1536 | struct perf_pmu_events_attr *pmu_attr; | |
61b87cae | 1537 | int offset = 0; |
8300daa2 JO |
1538 | int i, j; |
1539 | ||
1540 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1541 | d = (struct device_attribute *)attrs[i]; |
1542 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1543 | /* str trumps id */ | |
1544 | if (pmu_attr->event_str) | |
1545 | continue; | |
61b87cae | 1546 | if (x86_pmu.event_map(i + offset)) |
8300daa2 JO |
1547 | continue; |
1548 | ||
1549 | for (j = i; attrs[j]; j++) | |
1550 | attrs[j] = attrs[j + 1]; | |
1551 | ||
1552 | /* Check the shifted attr. */ | |
1553 | i--; | |
61b87cae SE |
1554 | |
1555 | /* | |
1556 | * event_map() is index based, the attrs array is organized | |
1557 | * by increasing event index. If we shift the events, then | |
1558 | * we need to compensate for the event_map(), otherwise | |
1559 | * we are looking up the wrong event in the map | |
1560 | */ | |
1561 | offset++; | |
8300daa2 JO |
1562 | } |
1563 | } | |
1564 | ||
1a6461b1 | 1565 | /* Merge two pointer arrays */ |
47732d88 | 1566 | __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) |
1a6461b1 AK |
1567 | { |
1568 | struct attribute **new; | |
1569 | int j, i; | |
1570 | ||
1571 | for (j = 0; a[j]; j++) | |
1572 | ; | |
1573 | for (i = 0; b[i]; i++) | |
1574 | j++; | |
1575 | j++; | |
1576 | ||
1577 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1578 | if (!new) | |
1579 | return NULL; | |
1580 | ||
1581 | j = 0; | |
1582 | for (i = 0; a[i]; i++) | |
1583 | new[j++] = a[i]; | |
1584 | for (i = 0; b[i]; i++) | |
1585 | new[j++] = b[i]; | |
1586 | new[j] = NULL; | |
1587 | ||
1588 | return new; | |
1589 | } | |
1590 | ||
f20093ee | 1591 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1592 | char *page) |
1593 | { | |
1594 | struct perf_pmu_events_attr *pmu_attr = \ | |
1595 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1596 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1597 | |
3a54aaa0 SE |
1598 | /* string trumps id */ |
1599 | if (pmu_attr->event_str) | |
1600 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1601 | |
3a54aaa0 SE |
1602 | return x86_pmu.events_sysfs_show(page, config); |
1603 | } | |
a4747393 JO |
1604 | |
1605 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1606 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1607 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1608 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1609 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1610 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1611 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1612 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1613 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1614 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1615 | ||
1616 | static struct attribute *empty_attrs; | |
1617 | ||
95d18aa2 | 1618 | static struct attribute *events_attr[] = { |
a4747393 JO |
1619 | EVENT_PTR(CPU_CYCLES), |
1620 | EVENT_PTR(INSTRUCTIONS), | |
1621 | EVENT_PTR(CACHE_REFERENCES), | |
1622 | EVENT_PTR(CACHE_MISSES), | |
1623 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1624 | EVENT_PTR(BRANCH_MISSES), | |
1625 | EVENT_PTR(BUS_CYCLES), | |
1626 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1627 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1628 | EVENT_PTR(REF_CPU_CYCLES), | |
1629 | NULL, | |
1630 | }; | |
1631 | ||
1632 | static struct attribute_group x86_pmu_events_group = { | |
1633 | .name = "events", | |
1634 | .attrs = events_attr, | |
1635 | }; | |
1636 | ||
0bf79d44 | 1637 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1638 | { |
43c032fe JO |
1639 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1640 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1641 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1642 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1643 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1644 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1645 | ssize_t ret; | |
1646 | ||
1647 | /* | |
1648 | * We have whole page size to spend and just little data | |
1649 | * to write, so we can safely use sprintf. | |
1650 | */ | |
1651 | ret = sprintf(page, "event=0x%02llx", event); | |
1652 | ||
1653 | if (umask) | |
1654 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1655 | ||
1656 | if (edge) | |
1657 | ret += sprintf(page + ret, ",edge"); | |
1658 | ||
1659 | if (pc) | |
1660 | ret += sprintf(page + ret, ",pc"); | |
1661 | ||
1662 | if (any) | |
1663 | ret += sprintf(page + ret, ",any"); | |
1664 | ||
1665 | if (inv) | |
1666 | ret += sprintf(page + ret, ",inv"); | |
1667 | ||
1668 | if (cmask) | |
1669 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1670 | ||
1671 | ret += sprintf(page + ret, "\n"); | |
1672 | ||
1673 | return ret; | |
1674 | } | |
1675 | ||
dda99116 | 1676 | static int __init init_hw_perf_events(void) |
b56a3802 | 1677 | { |
c1d6f42f | 1678 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1679 | int err; |
1680 | ||
cdd6c482 | 1681 | pr_info("Performance Events: "); |
1123e3ad | 1682 | |
b56a3802 JSR |
1683 | switch (boot_cpu_data.x86_vendor) { |
1684 | case X86_VENDOR_INTEL: | |
72eae04d | 1685 | err = intel_pmu_init(); |
b56a3802 | 1686 | break; |
f87ad35d | 1687 | case X86_VENDOR_AMD: |
72eae04d | 1688 | err = amd_pmu_init(); |
f87ad35d | 1689 | break; |
4138960a | 1690 | default: |
8a3da6c7 | 1691 | err = -ENOTSUPP; |
b56a3802 | 1692 | } |
1123e3ad | 1693 | if (err != 0) { |
cdd6c482 | 1694 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1695 | return 0; |
1123e3ad | 1696 | } |
b56a3802 | 1697 | |
12558038 CG |
1698 | pmu_check_apic(); |
1699 | ||
33c6d6a7 | 1700 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1701 | if (!check_hw_exists()) |
004417a6 | 1702 | return 0; |
33c6d6a7 | 1703 | |
1123e3ad | 1704 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1705 | |
e97df763 PZ |
1706 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1707 | ||
c1d6f42f PZ |
1708 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1709 | quirk->func(); | |
3c44780b | 1710 | |
a1eac7ac RR |
1711 | if (!x86_pmu.intel_ctrl) |
1712 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1713 | |
cdd6c482 | 1714 | perf_events_lapic_init(); |
9c48f1c6 | 1715 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1716 | |
63b14649 | 1717 | unconstrained = (struct event_constraint) |
948b1bb8 | 1718 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1719 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1720 | |
641cc938 | 1721 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1722 | |
f20093ee SE |
1723 | if (x86_pmu.event_attrs) |
1724 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1725 | ||
a4747393 JO |
1726 | if (!x86_pmu.events_sysfs_show) |
1727 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1728 | else |
1729 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1730 | |
1a6461b1 AK |
1731 | if (x86_pmu.cpu_events) { |
1732 | struct attribute **tmp; | |
1733 | ||
1734 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1735 | if (!WARN_ON(!tmp)) | |
1736 | x86_pmu_events_group.attrs = tmp; | |
1737 | } | |
1738 | ||
57c0c15b | 1739 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1740 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1741 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1742 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1743 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1744 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1745 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1746 | |
2e80a82a | 1747 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1748 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1749 | |
1750 | return 0; | |
241771ef | 1751 | } |
004417a6 | 1752 | early_initcall(init_hw_perf_events); |
621a01ea | 1753 | |
cdd6c482 | 1754 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1755 | { |
cc2ad4ba | 1756 | x86_perf_event_update(event); |
ee06094f IM |
1757 | } |
1758 | ||
4d1c52b0 LM |
1759 | /* |
1760 | * Start group events scheduling transaction | |
1761 | * Set the flag to make pmu::enable() not perform the | |
1762 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1763 | * |
1764 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1765 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1766 | * transactions. | |
4d1c52b0 | 1767 | */ |
fbbe0701 | 1768 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 1769 | { |
fbbe0701 SB |
1770 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1771 | ||
1772 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
1773 | ||
1774 | cpuc->txn_flags = txn_flags; | |
1775 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1776 | return; | |
1777 | ||
33696fc0 | 1778 | perf_pmu_disable(pmu); |
0a3aee0d | 1779 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
4d1c52b0 LM |
1780 | } |
1781 | ||
1782 | /* | |
1783 | * Stop group events scheduling transaction | |
1784 | * Clear the flag and pmu::enable() will perform the | |
1785 | * schedulability test. | |
1786 | */ | |
51b0fe39 | 1787 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1788 | { |
fbbe0701 SB |
1789 | unsigned int txn_flags; |
1790 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
1791 | ||
1792 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
1793 | ||
1794 | txn_flags = cpuc->txn_flags; | |
1795 | cpuc->txn_flags = 0; | |
1796 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1797 | return; | |
1798 | ||
90151c35 | 1799 | /* |
c347a2f1 PZ |
1800 | * Truncate collected array by the number of events added in this |
1801 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1802 | */ |
0a3aee0d TH |
1803 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1804 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1805 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1806 | } |
1807 | ||
1808 | /* | |
1809 | * Commit group events scheduling transaction | |
1810 | * Perform the group schedulability test as a whole | |
1811 | * Return 0 if success | |
c347a2f1 PZ |
1812 | * |
1813 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1814 | */ |
51b0fe39 | 1815 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1816 | { |
89cbc767 | 1817 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1818 | int assign[X86_PMC_IDX_MAX]; |
1819 | int n, ret; | |
1820 | ||
fbbe0701 SB |
1821 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
1822 | ||
1823 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1824 | cpuc->txn_flags = 0; | |
1825 | return 0; | |
1826 | } | |
1827 | ||
4d1c52b0 LM |
1828 | n = cpuc->n_events; |
1829 | ||
1830 | if (!x86_pmu_initialized()) | |
1831 | return -EAGAIN; | |
1832 | ||
1833 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1834 | if (ret) | |
1835 | return ret; | |
1836 | ||
1837 | /* | |
1838 | * copy new assignment, now we know it is possible | |
1839 | * will be used by hw_perf_enable() | |
1840 | */ | |
1841 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1842 | ||
fbbe0701 | 1843 | cpuc->txn_flags = 0; |
33696fc0 | 1844 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1845 | return 0; |
1846 | } | |
cd8a38d3 SE |
1847 | /* |
1848 | * a fake_cpuc is used to validate event groups. Due to | |
1849 | * the extra reg logic, we need to also allocate a fake | |
1850 | * per_core and per_cpu structure. Otherwise, group events | |
1851 | * using extra reg may conflict without the kernel being | |
1852 | * able to catch this when the last event gets added to | |
1853 | * the group. | |
1854 | */ | |
1855 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1856 | { | |
1857 | kfree(cpuc->shared_regs); | |
1858 | kfree(cpuc); | |
1859 | } | |
1860 | ||
1861 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1862 | { | |
1863 | struct cpu_hw_events *cpuc; | |
1864 | int cpu = raw_smp_processor_id(); | |
1865 | ||
1866 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1867 | if (!cpuc) | |
1868 | return ERR_PTR(-ENOMEM); | |
1869 | ||
1870 | /* only needed, if we have extra_regs */ | |
1871 | if (x86_pmu.extra_regs) { | |
1872 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1873 | if (!cpuc->shared_regs) | |
1874 | goto error; | |
1875 | } | |
b430f7c4 | 1876 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1877 | return cpuc; |
1878 | error: | |
1879 | free_fake_cpuc(cpuc); | |
1880 | return ERR_PTR(-ENOMEM); | |
1881 | } | |
4d1c52b0 | 1882 | |
ca037701 PZ |
1883 | /* |
1884 | * validate that we can schedule this event | |
1885 | */ | |
1886 | static int validate_event(struct perf_event *event) | |
1887 | { | |
1888 | struct cpu_hw_events *fake_cpuc; | |
1889 | struct event_constraint *c; | |
1890 | int ret = 0; | |
1891 | ||
cd8a38d3 SE |
1892 | fake_cpuc = allocate_fake_cpuc(); |
1893 | if (IS_ERR(fake_cpuc)) | |
1894 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1895 | |
79cba822 | 1896 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1897 | |
1898 | if (!c || !c->weight) | |
aa2bc1ad | 1899 | ret = -EINVAL; |
ca037701 PZ |
1900 | |
1901 | if (x86_pmu.put_event_constraints) | |
1902 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1903 | ||
cd8a38d3 | 1904 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1905 | |
1906 | return ret; | |
1907 | } | |
1908 | ||
1da53e02 SE |
1909 | /* |
1910 | * validate a single event group | |
1911 | * | |
1912 | * validation include: | |
184f412c IM |
1913 | * - check events are compatible which each other |
1914 | * - events do not compete for the same counter | |
1915 | * - number of events <= number of counters | |
1da53e02 SE |
1916 | * |
1917 | * validation ensures the group can be loaded onto the | |
1918 | * PMU if it was the only group available. | |
1919 | */ | |
fe9081cc PZ |
1920 | static int validate_group(struct perf_event *event) |
1921 | { | |
1da53e02 | 1922 | struct perf_event *leader = event->group_leader; |
502568d5 | 1923 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1924 | int ret = -EINVAL, n; |
fe9081cc | 1925 | |
cd8a38d3 SE |
1926 | fake_cpuc = allocate_fake_cpuc(); |
1927 | if (IS_ERR(fake_cpuc)) | |
1928 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1929 | /* |
1930 | * the event is not yet connected with its | |
1931 | * siblings therefore we must first collect | |
1932 | * existing siblings, then add the new event | |
1933 | * before we can simulate the scheduling | |
1934 | */ | |
502568d5 | 1935 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1936 | if (n < 0) |
cd8a38d3 | 1937 | goto out; |
fe9081cc | 1938 | |
502568d5 PZ |
1939 | fake_cpuc->n_events = n; |
1940 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1941 | if (n < 0) |
cd8a38d3 | 1942 | goto out; |
fe9081cc | 1943 | |
502568d5 | 1944 | fake_cpuc->n_events = n; |
1da53e02 | 1945 | |
a072738e | 1946 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1947 | |
502568d5 | 1948 | out: |
cd8a38d3 | 1949 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1950 | return ret; |
fe9081cc PZ |
1951 | } |
1952 | ||
dda99116 | 1953 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1954 | { |
51b0fe39 | 1955 | struct pmu *tmp; |
621a01ea IM |
1956 | int err; |
1957 | ||
b0a873eb PZ |
1958 | switch (event->attr.type) { |
1959 | case PERF_TYPE_RAW: | |
1960 | case PERF_TYPE_HARDWARE: | |
1961 | case PERF_TYPE_HW_CACHE: | |
1962 | break; | |
1963 | ||
1964 | default: | |
1965 | return -ENOENT; | |
1966 | } | |
1967 | ||
1968 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1969 | if (!err) { |
8113070d SE |
1970 | /* |
1971 | * we temporarily connect event to its pmu | |
1972 | * such that validate_group() can classify | |
1973 | * it as an x86 event using is_x86_event() | |
1974 | */ | |
1975 | tmp = event->pmu; | |
1976 | event->pmu = &pmu; | |
1977 | ||
fe9081cc PZ |
1978 | if (event->group_leader != event) |
1979 | err = validate_group(event); | |
ca037701 PZ |
1980 | else |
1981 | err = validate_event(event); | |
8113070d SE |
1982 | |
1983 | event->pmu = tmp; | |
fe9081cc | 1984 | } |
a1792cda | 1985 | if (err) { |
cdd6c482 IM |
1986 | if (event->destroy) |
1987 | event->destroy(event); | |
a1792cda | 1988 | } |
621a01ea | 1989 | |
7911d3f7 AL |
1990 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
1991 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
1992 | ||
b0a873eb | 1993 | return err; |
621a01ea | 1994 | } |
d7d59fb3 | 1995 | |
7911d3f7 AL |
1996 | static void refresh_pce(void *ignored) |
1997 | { | |
1998 | if (current->mm) | |
1999 | load_mm_cr4(current->mm); | |
2000 | } | |
2001 | ||
2002 | static void x86_pmu_event_mapped(struct perf_event *event) | |
2003 | { | |
2004 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2005 | return; | |
2006 | ||
2007 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
2008 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2009 | } | |
2010 | ||
2011 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
2012 | { | |
2013 | if (!current->mm) | |
2014 | return; | |
2015 | ||
2016 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2017 | return; | |
2018 | ||
2019 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
2020 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2021 | } | |
2022 | ||
fe4a3308 PZ |
2023 | static int x86_pmu_event_idx(struct perf_event *event) |
2024 | { | |
2025 | int idx = event->hw.idx; | |
2026 | ||
7911d3f7 | 2027 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
2028 | return 0; |
2029 | ||
15c7ad51 RR |
2030 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
2031 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
2032 | idx |= 1 << 30; |
2033 | } | |
2034 | ||
2035 | return idx + 1; | |
2036 | } | |
2037 | ||
0c9d42ed PZ |
2038 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2039 | struct device_attribute *attr, | |
2040 | char *buf) | |
2041 | { | |
2042 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2043 | } | |
2044 | ||
0c9d42ed PZ |
2045 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2046 | struct device_attribute *attr, | |
2047 | const char *buf, size_t count) | |
2048 | { | |
e2b297fc SK |
2049 | unsigned long val; |
2050 | ssize_t ret; | |
2051 | ||
2052 | ret = kstrtoul(buf, 0, &val); | |
2053 | if (ret) | |
2054 | return ret; | |
e97df763 | 2055 | |
a6673429 AL |
2056 | if (val > 2) |
2057 | return -EINVAL; | |
2058 | ||
e97df763 PZ |
2059 | if (x86_pmu.attr_rdpmc_broken) |
2060 | return -ENOTSUPP; | |
0c9d42ed | 2061 | |
a6673429 AL |
2062 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
2063 | /* | |
2064 | * Changing into or out of always available, aka | |
2065 | * perf-event-bypassing mode. This path is extremely slow, | |
2066 | * but only root can trigger it, so it's okay. | |
2067 | */ | |
2068 | if (val == 2) | |
2069 | static_key_slow_inc(&rdpmc_always_available); | |
2070 | else | |
2071 | static_key_slow_dec(&rdpmc_always_available); | |
2072 | on_each_cpu(refresh_pce, NULL, 1); | |
2073 | } | |
2074 | ||
2075 | x86_pmu.attr_rdpmc = val; | |
2076 | ||
0c9d42ed PZ |
2077 | return count; |
2078 | } | |
2079 | ||
2080 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2081 | ||
2082 | static struct attribute *x86_pmu_attrs[] = { | |
2083 | &dev_attr_rdpmc.attr, | |
2084 | NULL, | |
2085 | }; | |
2086 | ||
2087 | static struct attribute_group x86_pmu_attr_group = { | |
2088 | .attrs = x86_pmu_attrs, | |
2089 | }; | |
2090 | ||
2091 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2092 | &x86_pmu_attr_group, | |
641cc938 | 2093 | &x86_pmu_format_group, |
a4747393 | 2094 | &x86_pmu_events_group, |
0c9d42ed PZ |
2095 | NULL, |
2096 | }; | |
2097 | ||
ba532500 | 2098 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2099 | { |
ba532500 YZ |
2100 | if (x86_pmu.sched_task) |
2101 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2102 | } |
2103 | ||
c93dc84c PZ |
2104 | void perf_check_microcode(void) |
2105 | { | |
2106 | if (x86_pmu.check_microcode) | |
2107 | x86_pmu.check_microcode(); | |
2108 | } | |
2109 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2110 | ||
b0a873eb | 2111 | static struct pmu pmu = { |
d010b332 SE |
2112 | .pmu_enable = x86_pmu_enable, |
2113 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2114 | |
c93dc84c | 2115 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2116 | |
c93dc84c | 2117 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2118 | |
7911d3f7 AL |
2119 | .event_mapped = x86_pmu_event_mapped, |
2120 | .event_unmapped = x86_pmu_event_unmapped, | |
2121 | ||
d010b332 SE |
2122 | .add = x86_pmu_add, |
2123 | .del = x86_pmu_del, | |
2124 | .start = x86_pmu_start, | |
2125 | .stop = x86_pmu_stop, | |
2126 | .read = x86_pmu_read, | |
a4eaf7f1 | 2127 | |
c93dc84c PZ |
2128 | .start_txn = x86_pmu_start_txn, |
2129 | .cancel_txn = x86_pmu_cancel_txn, | |
2130 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2131 | |
c93dc84c | 2132 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2133 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2134 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2135 | }; |
2136 | ||
c1317ec2 AL |
2137 | void arch_perf_update_userpage(struct perf_event *event, |
2138 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2139 | { |
20d1c86a PZ |
2140 | struct cyc2ns_data *data; |
2141 | ||
fa731587 PZ |
2142 | userpg->cap_user_time = 0; |
2143 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2144 | userpg->cap_user_rdpmc = |
2145 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2146 | userpg->pmc_width = x86_pmu.cntval_bits; |
2147 | ||
35af99e6 | 2148 | if (!sched_clock_stable()) |
e3f3541c PZ |
2149 | return; |
2150 | ||
20d1c86a PZ |
2151 | data = cyc2ns_read_begin(); |
2152 | ||
34f43927 PZ |
2153 | /* |
2154 | * Internal timekeeping for enabled/running/stopped times | |
2155 | * is always in the local_clock domain. | |
2156 | */ | |
fa731587 | 2157 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2158 | userpg->time_mult = data->cyc2ns_mul; |
2159 | userpg->time_shift = data->cyc2ns_shift; | |
2160 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2161 | |
34f43927 PZ |
2162 | /* |
2163 | * cap_user_time_zero doesn't make sense when we're using a different | |
2164 | * time base for the records. | |
2165 | */ | |
2166 | if (event->clock == &local_clock) { | |
2167 | userpg->cap_user_time_zero = 1; | |
2168 | userpg->time_zero = data->cyc2ns_offset; | |
2169 | } | |
20d1c86a PZ |
2170 | |
2171 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2172 | } |
2173 | ||
d7d59fb3 PZ |
2174 | /* |
2175 | * callchain support | |
2176 | */ | |
2177 | ||
d7d59fb3 PZ |
2178 | static int backtrace_stack(void *data, char *name) |
2179 | { | |
038e836e | 2180 | return 0; |
d7d59fb3 PZ |
2181 | } |
2182 | ||
2183 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
2184 | { | |
2185 | struct perf_callchain_entry *entry = data; | |
2186 | ||
70791ce9 | 2187 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
2188 | } |
2189 | ||
2190 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
2191 | .stack = backtrace_stack, |
2192 | .address = backtrace_address, | |
06d65bda | 2193 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
2194 | }; |
2195 | ||
56962b44 FW |
2196 | void |
2197 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 2198 | { |
927c7a9e FW |
2199 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2200 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2201 | return; |
927c7a9e FW |
2202 | } |
2203 | ||
70791ce9 | 2204 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2205 | |
e8e999cf | 2206 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2207 | } |
2208 | ||
bc6ca7b3 AS |
2209 | static inline int |
2210 | valid_user_frame(const void __user *fp, unsigned long size) | |
2211 | { | |
2212 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2213 | } | |
2214 | ||
d07bdfd3 PZ |
2215 | static unsigned long get_segment_base(unsigned int segment) |
2216 | { | |
2217 | struct desc_struct *desc; | |
2218 | int idx = segment >> 3; | |
2219 | ||
2220 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2221 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2222 | struct ldt_struct *ldt; |
2223 | ||
d07bdfd3 PZ |
2224 | if (idx > LDT_ENTRIES) |
2225 | return 0; | |
2226 | ||
37868fe1 AL |
2227 | /* IRQs are off, so this synchronizes with smp_store_release */ |
2228 | ldt = lockless_dereference(current->active_mm->context.ldt); | |
2229 | if (!ldt || idx > ldt->size) | |
d07bdfd3 PZ |
2230 | return 0; |
2231 | ||
37868fe1 | 2232 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2233 | #else |
2234 | return 0; | |
2235 | #endif | |
d07bdfd3 PZ |
2236 | } else { |
2237 | if (idx > GDT_ENTRIES) | |
2238 | return 0; | |
2239 | ||
37868fe1 | 2240 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2241 | } |
2242 | ||
37868fe1 | 2243 | return get_desc_base(desc); |
d07bdfd3 PZ |
2244 | } |
2245 | ||
10ed3493 | 2246 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 PA |
2247 | |
2248 | #include <asm/compat.h> | |
2249 | ||
257ef9d2 TE |
2250 | static inline int |
2251 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2252 | { |
257ef9d2 | 2253 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2254 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2255 | struct stack_frame_ia32 frame; |
2256 | const void __user *fp; | |
74193ef0 | 2257 | |
257ef9d2 TE |
2258 | if (!test_thread_flag(TIF_IA32)) |
2259 | return 0; | |
2260 | ||
d07bdfd3 PZ |
2261 | cs_base = get_segment_base(regs->cs); |
2262 | ss_base = get_segment_base(regs->ss); | |
2263 | ||
2264 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2265 | pagefault_disable(); |
257ef9d2 TE |
2266 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2267 | unsigned long bytes; | |
2268 | frame.next_frame = 0; | |
2269 | frame.return_address = 0; | |
2270 | ||
75925e1a AK |
2271 | if (!access_ok(VERIFY_READ, fp, 8)) |
2272 | break; | |
2273 | ||
2274 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); | |
2275 | if (bytes != 0) | |
2276 | break; | |
2277 | bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); | |
0a196848 | 2278 | if (bytes != 0) |
257ef9d2 | 2279 | break; |
74193ef0 | 2280 | |
bc6ca7b3 AS |
2281 | if (!valid_user_frame(fp, sizeof(frame))) |
2282 | break; | |
2283 | ||
d07bdfd3 PZ |
2284 | perf_callchain_store(entry, cs_base + frame.return_address); |
2285 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2286 | } |
75925e1a | 2287 | pagefault_enable(); |
257ef9d2 | 2288 | return 1; |
d7d59fb3 | 2289 | } |
257ef9d2 TE |
2290 | #else |
2291 | static inline int | |
2292 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2293 | { | |
2294 | return 0; | |
2295 | } | |
2296 | #endif | |
d7d59fb3 | 2297 | |
56962b44 FW |
2298 | void |
2299 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2300 | { |
2301 | struct stack_frame frame; | |
2302 | const void __user *fp; | |
2303 | ||
927c7a9e FW |
2304 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2305 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2306 | return; |
927c7a9e | 2307 | } |
5a6cec3a | 2308 | |
d07bdfd3 PZ |
2309 | /* |
2310 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2311 | */ | |
2312 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2313 | return; | |
2314 | ||
74193ef0 | 2315 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2316 | |
70791ce9 | 2317 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2318 | |
20afc60f AV |
2319 | if (!current->mm) |
2320 | return; | |
2321 | ||
257ef9d2 TE |
2322 | if (perf_callchain_user32(regs, entry)) |
2323 | return; | |
2324 | ||
75925e1a | 2325 | pagefault_disable(); |
f9188e02 | 2326 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2327 | unsigned long bytes; |
038e836e | 2328 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2329 | frame.return_address = 0; |
2330 | ||
75925e1a AK |
2331 | if (!access_ok(VERIFY_READ, fp, 16)) |
2332 | break; | |
2333 | ||
2334 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8); | |
2335 | if (bytes != 0) | |
2336 | break; | |
2337 | bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8); | |
0a196848 | 2338 | if (bytes != 0) |
d7d59fb3 PZ |
2339 | break; |
2340 | ||
bc6ca7b3 AS |
2341 | if (!valid_user_frame(fp, sizeof(frame))) |
2342 | break; | |
2343 | ||
70791ce9 | 2344 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2345 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2346 | } |
75925e1a | 2347 | pagefault_enable(); |
d7d59fb3 PZ |
2348 | } |
2349 | ||
d07bdfd3 PZ |
2350 | /* |
2351 | * Deal with code segment offsets for the various execution modes: | |
2352 | * | |
2353 | * VM86 - the good olde 16 bit days, where the linear address is | |
2354 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2355 | * | |
2356 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2357 | * to figure out what the 32bit base address is. | |
2358 | * | |
2359 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2360 | * | |
2361 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2362 | */ | |
2363 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2364 | { |
383f3af3 AL |
2365 | /* |
2366 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2367 | * effective IP to a linear address. | |
2368 | */ | |
2369 | ||
2370 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2371 | /* |
2372 | * If we are in VM86 mode, add the segment offset to convert to a | |
2373 | * linear address. | |
2374 | */ | |
2375 | if (regs->flags & X86_VM_MASK) | |
2376 | return 0x10 * regs->cs; | |
2377 | ||
55474c48 | 2378 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2379 | return get_segment_base(regs->cs); |
2380 | #else | |
c56716af AL |
2381 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2382 | regs->cs != __USER32_CS) | |
2383 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2384 | #endif |
2385 | return 0; | |
2386 | } | |
dcf46b94 | 2387 | |
d07bdfd3 PZ |
2388 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2389 | { | |
39447b38 | 2390 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2391 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2392 | |
d07bdfd3 | 2393 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2394 | } |
2395 | ||
2396 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2397 | { | |
2398 | int misc = 0; | |
dcf46b94 | 2399 | |
39447b38 | 2400 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2401 | if (perf_guest_cbs->is_user_mode()) |
2402 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2403 | else | |
2404 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2405 | } else { | |
d07bdfd3 | 2406 | if (user_mode(regs)) |
dcf46b94 ZY |
2407 | misc |= PERF_RECORD_MISC_USER; |
2408 | else | |
2409 | misc |= PERF_RECORD_MISC_KERNEL; | |
2410 | } | |
2411 | ||
39447b38 | 2412 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2413 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2414 | |
2415 | return misc; | |
2416 | } | |
b3d9468a GN |
2417 | |
2418 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2419 | { | |
2420 | cap->version = x86_pmu.version; | |
2421 | cap->num_counters_gp = x86_pmu.num_counters; | |
2422 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2423 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2424 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2425 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2426 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2427 | } | |
2428 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |