Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
257ef9d2 | 31 | #include <asm/compat.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
241771ef | 34 | |
de0428a7 KW |
35 | #include "perf_event.h" |
36 | ||
7645a24c PZ |
37 | #if 0 |
38 | #undef wrmsrl | |
39 | #define wrmsrl(msr, val) \ | |
40 | do { \ | |
41 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
42 | (unsigned long)(val)); \ | |
43 | native_write_msr((msr), (u32)((u64)(val)), \ | |
44 | (u32)((u64)(val) >> 32)); \ | |
45 | } while (0) | |
46 | #endif | |
47 | ||
de0428a7 | 48 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 49 | |
de0428a7 | 50 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
51 | .enabled = 1, |
52 | }; | |
241771ef | 53 | |
de0428a7 | 54 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 58 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
59 | [PERF_COUNT_HW_CACHE_MAX] |
60 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
61 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 62 | |
ee06094f | 63 | /* |
cdd6c482 IM |
64 | * Propagate event elapsed time into the generic event. |
65 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
66 | * Returns the delta events processed. |
67 | */ | |
de0428a7 | 68 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 69 | { |
cc2ad4ba | 70 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 71 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 72 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 73 | int idx = hwc->idx; |
ec3232bd | 74 | s64 delta; |
ee06094f | 75 | |
30dd568c MM |
76 | if (idx == X86_PMC_IDX_FIXED_BTS) |
77 | return 0; | |
78 | ||
ee06094f | 79 | /* |
cdd6c482 | 80 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
81 | * |
82 | * Our tactic to handle this is to first atomically read and | |
83 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 84 | * count to the generic event atomically: |
ee06094f IM |
85 | */ |
86 | again: | |
e7850595 | 87 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 88 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 89 | |
e7850595 | 90 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
91 | new_raw_count) != prev_raw_count) |
92 | goto again; | |
93 | ||
94 | /* | |
95 | * Now we have the new raw value and have updated the prev | |
96 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 97 | * (event-)time and add that to the generic event. |
ee06094f IM |
98 | * |
99 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 100 | * of the count. |
ee06094f | 101 | */ |
ec3232bd PZ |
102 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
103 | delta >>= shift; | |
ee06094f | 104 | |
e7850595 PZ |
105 | local64_add(delta, &event->count); |
106 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
107 | |
108 | return new_raw_count; | |
ee06094f IM |
109 | } |
110 | ||
a7e3ed1e AK |
111 | /* |
112 | * Find and validate any extra registers to set up. | |
113 | */ | |
114 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
115 | { | |
efc9f05d | 116 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
117 | struct extra_reg *er; |
118 | ||
efc9f05d | 119 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
120 | |
121 | if (!x86_pmu.extra_regs) | |
122 | return 0; | |
123 | ||
124 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
125 | if (er->event != (config & er->config_mask)) | |
126 | continue; | |
127 | if (event->attr.config1 & ~er->valid_mask) | |
128 | return -EINVAL; | |
efc9f05d SE |
129 | |
130 | reg->idx = er->idx; | |
131 | reg->config = event->attr.config1; | |
132 | reg->reg = er->msr; | |
a7e3ed1e AK |
133 | break; |
134 | } | |
135 | return 0; | |
136 | } | |
137 | ||
cdd6c482 | 138 | static atomic_t active_events; |
4e935e47 PZ |
139 | static DEFINE_MUTEX(pmc_reserve_mutex); |
140 | ||
b27ea29c RR |
141 | #ifdef CONFIG_X86_LOCAL_APIC |
142 | ||
4e935e47 PZ |
143 | static bool reserve_pmc_hardware(void) |
144 | { | |
145 | int i; | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
149 | goto perfctr_fail; |
150 | } | |
151 | ||
948b1bb8 | 152 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 153 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
154 | goto eventsel_fail; |
155 | } | |
156 | ||
157 | return true; | |
158 | ||
159 | eventsel_fail: | |
160 | for (i--; i >= 0; i--) | |
41bf4989 | 161 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 162 | |
948b1bb8 | 163 | i = x86_pmu.num_counters; |
4e935e47 PZ |
164 | |
165 | perfctr_fail: | |
166 | for (i--; i >= 0; i--) | |
41bf4989 | 167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 168 | |
4e935e47 PZ |
169 | return false; |
170 | } | |
171 | ||
172 | static void release_pmc_hardware(void) | |
173 | { | |
174 | int i; | |
175 | ||
948b1bb8 | 176 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
177 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
178 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 179 | } |
4e935e47 PZ |
180 | } |
181 | ||
b27ea29c RR |
182 | #else |
183 | ||
184 | static bool reserve_pmc_hardware(void) { return true; } | |
185 | static void release_pmc_hardware(void) {} | |
186 | ||
187 | #endif | |
188 | ||
33c6d6a7 DZ |
189 | static bool check_hw_exists(void) |
190 | { | |
191 | u64 val, val_new = 0; | |
4407204c | 192 | int i, reg, ret = 0; |
33c6d6a7 | 193 | |
4407204c PZ |
194 | /* |
195 | * Check to see if the BIOS enabled any of the counters, if so | |
196 | * complain and bail. | |
197 | */ | |
198 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 199 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
200 | ret = rdmsrl_safe(reg, &val); |
201 | if (ret) | |
202 | goto msr_fail; | |
203 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
204 | goto bios_fail; | |
205 | } | |
206 | ||
207 | if (x86_pmu.num_counters_fixed) { | |
208 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
209 | ret = rdmsrl_safe(reg, &val); | |
210 | if (ret) | |
211 | goto msr_fail; | |
212 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
213 | if (val & (0x03 << i*4)) | |
214 | goto bios_fail; | |
215 | } | |
216 | } | |
217 | ||
218 | /* | |
219 | * Now write a value and read it back to see if it matches, | |
220 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
221 | * that don't trap on the MSR access and always return 0s. | |
222 | */ | |
33c6d6a7 | 223 | val = 0xabcdUL; |
41bf4989 RR |
224 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
225 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 226 | if (ret || val != val_new) |
4407204c | 227 | goto msr_fail; |
33c6d6a7 DZ |
228 | |
229 | return true; | |
4407204c PZ |
230 | |
231 | bios_fail: | |
45daae57 IM |
232 | /* |
233 | * We still allow the PMU driver to operate: | |
234 | */ | |
235 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 236 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
237 | |
238 | return true; | |
4407204c PZ |
239 | |
240 | msr_fail: | |
241 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 242 | |
4407204c | 243 | return false; |
33c6d6a7 DZ |
244 | } |
245 | ||
cdd6c482 | 246 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 247 | { |
cdd6c482 | 248 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 249 | release_pmc_hardware(); |
ca037701 | 250 | release_ds_buffers(); |
4e935e47 PZ |
251 | mutex_unlock(&pmc_reserve_mutex); |
252 | } | |
253 | } | |
254 | ||
85cf9dba RR |
255 | static inline int x86_pmu_initialized(void) |
256 | { | |
257 | return x86_pmu.handle_irq != NULL; | |
258 | } | |
259 | ||
8326f44d | 260 | static inline int |
e994d7d2 | 261 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 262 | { |
e994d7d2 | 263 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
264 | unsigned int cache_type, cache_op, cache_result; |
265 | u64 config, val; | |
266 | ||
267 | config = attr->config; | |
268 | ||
269 | cache_type = (config >> 0) & 0xff; | |
270 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
271 | return -EINVAL; | |
272 | ||
273 | cache_op = (config >> 8) & 0xff; | |
274 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
275 | return -EINVAL; | |
276 | ||
277 | cache_result = (config >> 16) & 0xff; | |
278 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
279 | return -EINVAL; | |
280 | ||
281 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
282 | ||
283 | if (val == 0) | |
284 | return -ENOENT; | |
285 | ||
286 | if (val == -1) | |
287 | return -EINVAL; | |
288 | ||
289 | hwc->config |= val; | |
e994d7d2 AK |
290 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
291 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
292 | } |
293 | ||
de0428a7 | 294 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
295 | { |
296 | struct perf_event_attr *attr = &event->attr; | |
297 | struct hw_perf_event *hwc = &event->hw; | |
298 | u64 config; | |
299 | ||
6c7e550f | 300 | if (!is_sampling_event(event)) { |
c1726f34 RR |
301 | hwc->sample_period = x86_pmu.max_period; |
302 | hwc->last_period = hwc->sample_period; | |
e7850595 | 303 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
304 | } else { |
305 | /* | |
306 | * If we have a PMU initialized but no APIC | |
307 | * interrupts, we cannot sample hardware | |
308 | * events (user-space has to fall back and | |
309 | * sample via a hrtimer based software event): | |
310 | */ | |
311 | if (!x86_pmu.apic) | |
312 | return -EOPNOTSUPP; | |
313 | } | |
314 | ||
b52c55c6 IM |
315 | /* |
316 | * Do not allow config1 (extended registers) to propagate, | |
317 | * there's no sane user-space generalization yet: | |
318 | */ | |
c1726f34 | 319 | if (attr->type == PERF_TYPE_RAW) |
b52c55c6 | 320 | return 0; |
c1726f34 RR |
321 | |
322 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 323 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
324 | |
325 | if (attr->config >= x86_pmu.max_events) | |
326 | return -EINVAL; | |
327 | ||
328 | /* | |
329 | * The generic map: | |
330 | */ | |
331 | config = x86_pmu.event_map(attr->config); | |
332 | ||
333 | if (config == 0) | |
334 | return -ENOENT; | |
335 | ||
336 | if (config == -1LL) | |
337 | return -EINVAL; | |
338 | ||
339 | /* | |
340 | * Branch tracing: | |
341 | */ | |
18a073a3 PZ |
342 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
343 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 344 | /* BTS is not supported by this architecture. */ |
6809b6ea | 345 | if (!x86_pmu.bts_active) |
c1726f34 RR |
346 | return -EOPNOTSUPP; |
347 | ||
348 | /* BTS is currently only allowed for user-mode. */ | |
349 | if (!attr->exclude_kernel) | |
350 | return -EOPNOTSUPP; | |
351 | } | |
352 | ||
353 | hwc->config |= config; | |
354 | ||
355 | return 0; | |
356 | } | |
4261e0e0 | 357 | |
de0428a7 | 358 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 359 | { |
ab608344 PZ |
360 | if (event->attr.precise_ip) { |
361 | int precise = 0; | |
362 | ||
363 | /* Support for constant skid */ | |
6809b6ea | 364 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
365 | precise++; |
366 | ||
5553be26 PZ |
367 | /* Support for IP fixup */ |
368 | if (x86_pmu.lbr_nr) | |
369 | precise++; | |
370 | } | |
ab608344 PZ |
371 | |
372 | if (event->attr.precise_ip > precise) | |
373 | return -EOPNOTSUPP; | |
374 | } | |
375 | ||
a072738e CG |
376 | /* |
377 | * Generate PMC IRQs: | |
378 | * (keep 'enabled' bit clear for now) | |
379 | */ | |
b4cdc5c2 | 380 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
381 | |
382 | /* | |
383 | * Count user and OS events unless requested not to | |
384 | */ | |
b4cdc5c2 PZ |
385 | if (!event->attr.exclude_user) |
386 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
387 | if (!event->attr.exclude_kernel) | |
388 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 389 | |
b4cdc5c2 PZ |
390 | if (event->attr.type == PERF_TYPE_RAW) |
391 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 392 | |
9d0fcba6 | 393 | return x86_setup_perfctr(event); |
a098f448 RR |
394 | } |
395 | ||
241771ef | 396 | /* |
0d48696f | 397 | * Setup the hardware configuration for a given attr_type |
241771ef | 398 | */ |
b0a873eb | 399 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 400 | { |
4e935e47 | 401 | int err; |
241771ef | 402 | |
85cf9dba RR |
403 | if (!x86_pmu_initialized()) |
404 | return -ENODEV; | |
241771ef | 405 | |
4e935e47 | 406 | err = 0; |
cdd6c482 | 407 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 408 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 409 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
410 | if (!reserve_pmc_hardware()) |
411 | err = -EBUSY; | |
f80c9e30 PZ |
412 | else |
413 | reserve_ds_buffers(); | |
30dd568c MM |
414 | } |
415 | if (!err) | |
cdd6c482 | 416 | atomic_inc(&active_events); |
4e935e47 PZ |
417 | mutex_unlock(&pmc_reserve_mutex); |
418 | } | |
419 | if (err) | |
420 | return err; | |
421 | ||
cdd6c482 | 422 | event->destroy = hw_perf_event_destroy; |
a1792cda | 423 | |
4261e0e0 RR |
424 | event->hw.idx = -1; |
425 | event->hw.last_cpu = -1; | |
426 | event->hw.last_tag = ~0ULL; | |
b690081d | 427 | |
efc9f05d SE |
428 | /* mark unused */ |
429 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
430 | ||
9d0fcba6 | 431 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
432 | } |
433 | ||
de0428a7 | 434 | void x86_pmu_disable_all(void) |
f87ad35d | 435 | { |
cdd6c482 | 436 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
437 | int idx; |
438 | ||
948b1bb8 | 439 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
440 | u64 val; |
441 | ||
43f6201a | 442 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 443 | continue; |
41bf4989 | 444 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 445 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 446 | continue; |
bb1165d6 | 447 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 448 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 449 | } |
f87ad35d JSR |
450 | } |
451 | ||
a4eaf7f1 | 452 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 453 | { |
1da53e02 SE |
454 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
455 | ||
85cf9dba | 456 | if (!x86_pmu_initialized()) |
9e35ad38 | 457 | return; |
1da53e02 | 458 | |
1a6e21f7 PZ |
459 | if (!cpuc->enabled) |
460 | return; | |
461 | ||
462 | cpuc->n_added = 0; | |
463 | cpuc->enabled = 0; | |
464 | barrier(); | |
1da53e02 SE |
465 | |
466 | x86_pmu.disable_all(); | |
b56a3802 | 467 | } |
241771ef | 468 | |
de0428a7 | 469 | void x86_pmu_enable_all(int added) |
f87ad35d | 470 | { |
cdd6c482 | 471 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
472 | int idx; |
473 | ||
948b1bb8 | 474 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 475 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 476 | |
43f6201a | 477 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 478 | continue; |
984b838c | 479 | |
d45dd923 | 480 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
481 | } |
482 | } | |
483 | ||
51b0fe39 | 484 | static struct pmu pmu; |
1da53e02 SE |
485 | |
486 | static inline int is_x86_event(struct perf_event *event) | |
487 | { | |
488 | return event->pmu == &pmu; | |
489 | } | |
490 | ||
de0428a7 | 491 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 492 | { |
63b14649 | 493 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 494 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 495 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
496 | struct hw_perf_event *hwc; |
497 | ||
498 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
499 | ||
500 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
501 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
502 | constraints[i] = c; | |
1da53e02 SE |
503 | } |
504 | ||
8113070d SE |
505 | /* |
506 | * fastpath, try to reuse previous register | |
507 | */ | |
c933c1a6 | 508 | for (i = 0; i < n; i++) { |
8113070d | 509 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 510 | c = constraints[i]; |
8113070d SE |
511 | |
512 | /* never assigned */ | |
513 | if (hwc->idx == -1) | |
514 | break; | |
515 | ||
516 | /* constraint still honored */ | |
63b14649 | 517 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
518 | break; |
519 | ||
520 | /* not already used */ | |
521 | if (test_bit(hwc->idx, used_mask)) | |
522 | break; | |
523 | ||
34538ee7 | 524 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
525 | if (assign) |
526 | assign[i] = hwc->idx; | |
527 | } | |
c933c1a6 | 528 | if (i == n) |
8113070d SE |
529 | goto done; |
530 | ||
531 | /* | |
532 | * begin slow path | |
533 | */ | |
534 | ||
535 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
536 | ||
1da53e02 SE |
537 | /* |
538 | * weight = number of possible counters | |
539 | * | |
540 | * 1 = most constrained, only works on one counter | |
541 | * wmax = least constrained, works on any counter | |
542 | * | |
543 | * assign events to counters starting with most | |
544 | * constrained events. | |
545 | */ | |
948b1bb8 | 546 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
547 | |
548 | /* | |
549 | * when fixed event counters are present, | |
550 | * wmax is incremented by 1 to account | |
551 | * for one more choice | |
552 | */ | |
948b1bb8 | 553 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
554 | wmax++; |
555 | ||
8113070d | 556 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 557 | /* for each event */ |
8113070d | 558 | for (i = 0; num && i < n; i++) { |
81269a08 | 559 | c = constraints[i]; |
1da53e02 SE |
560 | hwc = &cpuc->event_list[i]->hw; |
561 | ||
272d30be | 562 | if (c->weight != w) |
1da53e02 SE |
563 | continue; |
564 | ||
984b3f57 | 565 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
566 | if (!test_bit(j, used_mask)) |
567 | break; | |
568 | } | |
569 | ||
570 | if (j == X86_PMC_IDX_MAX) | |
571 | break; | |
1da53e02 | 572 | |
34538ee7 | 573 | __set_bit(j, used_mask); |
8113070d | 574 | |
1da53e02 SE |
575 | if (assign) |
576 | assign[i] = j; | |
577 | num--; | |
578 | } | |
579 | } | |
8113070d | 580 | done: |
1da53e02 SE |
581 | /* |
582 | * scheduling failed or is just a simulation, | |
583 | * free resources if necessary | |
584 | */ | |
585 | if (!assign || num) { | |
586 | for (i = 0; i < n; i++) { | |
587 | if (x86_pmu.put_event_constraints) | |
588 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
589 | } | |
590 | } | |
591 | return num ? -ENOSPC : 0; | |
592 | } | |
593 | ||
594 | /* | |
595 | * dogrp: true if must collect siblings events (group) | |
596 | * returns total number of events and error code | |
597 | */ | |
598 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
599 | { | |
600 | struct perf_event *event; | |
601 | int n, max_count; | |
602 | ||
948b1bb8 | 603 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
604 | |
605 | /* current number of events already accepted */ | |
606 | n = cpuc->n_events; | |
607 | ||
608 | if (is_x86_event(leader)) { | |
609 | if (n >= max_count) | |
610 | return -ENOSPC; | |
611 | cpuc->event_list[n] = leader; | |
612 | n++; | |
613 | } | |
614 | if (!dogrp) | |
615 | return n; | |
616 | ||
617 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
618 | if (!is_x86_event(event) || | |
8113070d | 619 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
620 | continue; |
621 | ||
622 | if (n >= max_count) | |
623 | return -ENOSPC; | |
624 | ||
625 | cpuc->event_list[n] = event; | |
626 | n++; | |
627 | } | |
628 | return n; | |
629 | } | |
630 | ||
1da53e02 | 631 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 632 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 633 | { |
447a194b SE |
634 | struct hw_perf_event *hwc = &event->hw; |
635 | ||
636 | hwc->idx = cpuc->assign[i]; | |
637 | hwc->last_cpu = smp_processor_id(); | |
638 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
639 | |
640 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
641 | hwc->config_base = 0; | |
642 | hwc->event_base = 0; | |
643 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
644 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 645 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 646 | } else { |
73d6e522 RR |
647 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
648 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
649 | } |
650 | } | |
651 | ||
447a194b SE |
652 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
653 | struct cpu_hw_events *cpuc, | |
654 | int i) | |
655 | { | |
656 | return hwc->idx == cpuc->assign[i] && | |
657 | hwc->last_cpu == smp_processor_id() && | |
658 | hwc->last_tag == cpuc->tags[i]; | |
659 | } | |
660 | ||
a4eaf7f1 | 661 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 662 | |
a4eaf7f1 | 663 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 664 | { |
1da53e02 SE |
665 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
666 | struct perf_event *event; | |
667 | struct hw_perf_event *hwc; | |
11164cd4 | 668 | int i, added = cpuc->n_added; |
1da53e02 | 669 | |
85cf9dba | 670 | if (!x86_pmu_initialized()) |
2b9ff0db | 671 | return; |
1a6e21f7 PZ |
672 | |
673 | if (cpuc->enabled) | |
674 | return; | |
675 | ||
1da53e02 | 676 | if (cpuc->n_added) { |
19925ce7 | 677 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
678 | /* |
679 | * apply assignment obtained either from | |
680 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
681 | * | |
682 | * step1: save events moving to new counters | |
683 | * step2: reprogram moved events into new counters | |
684 | */ | |
19925ce7 | 685 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
686 | event = cpuc->event_list[i]; |
687 | hwc = &event->hw; | |
688 | ||
447a194b SE |
689 | /* |
690 | * we can avoid reprogramming counter if: | |
691 | * - assigned same counter as last time | |
692 | * - running on same CPU as last time | |
693 | * - no other event has used the counter since | |
694 | */ | |
695 | if (hwc->idx == -1 || | |
696 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
697 | continue; |
698 | ||
a4eaf7f1 PZ |
699 | /* |
700 | * Ensure we don't accidentally enable a stopped | |
701 | * counter simply because we rescheduled. | |
702 | */ | |
703 | if (hwc->state & PERF_HES_STOPPED) | |
704 | hwc->state |= PERF_HES_ARCH; | |
705 | ||
706 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
707 | } |
708 | ||
709 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
710 | event = cpuc->event_list[i]; |
711 | hwc = &event->hw; | |
712 | ||
45e16a68 | 713 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 714 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
715 | else if (i < n_running) |
716 | continue; | |
1da53e02 | 717 | |
a4eaf7f1 PZ |
718 | if (hwc->state & PERF_HES_ARCH) |
719 | continue; | |
720 | ||
721 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
722 | } |
723 | cpuc->n_added = 0; | |
724 | perf_events_lapic_init(); | |
725 | } | |
1a6e21f7 PZ |
726 | |
727 | cpuc->enabled = 1; | |
728 | barrier(); | |
729 | ||
11164cd4 | 730 | x86_pmu.enable_all(added); |
ee06094f | 731 | } |
ee06094f | 732 | |
245b2e70 | 733 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 734 | |
ee06094f IM |
735 | /* |
736 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 737 | * To be called with the event disabled in hw: |
ee06094f | 738 | */ |
de0428a7 | 739 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 740 | { |
07088edb | 741 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 742 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 743 | s64 period = hwc->sample_period; |
7645a24c | 744 | int ret = 0, idx = hwc->idx; |
ee06094f | 745 | |
30dd568c MM |
746 | if (idx == X86_PMC_IDX_FIXED_BTS) |
747 | return 0; | |
748 | ||
ee06094f | 749 | /* |
af901ca1 | 750 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
751 | */ |
752 | if (unlikely(left <= -period)) { | |
753 | left = period; | |
e7850595 | 754 | local64_set(&hwc->period_left, left); |
9e350de3 | 755 | hwc->last_period = period; |
e4abb5d4 | 756 | ret = 1; |
ee06094f IM |
757 | } |
758 | ||
759 | if (unlikely(left <= 0)) { | |
760 | left += period; | |
e7850595 | 761 | local64_set(&hwc->period_left, left); |
9e350de3 | 762 | hwc->last_period = period; |
e4abb5d4 | 763 | ret = 1; |
ee06094f | 764 | } |
1c80f4b5 | 765 | /* |
dfc65094 | 766 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
767 | */ |
768 | if (unlikely(left < 2)) | |
769 | left = 2; | |
241771ef | 770 | |
e4abb5d4 PZ |
771 | if (left > x86_pmu.max_period) |
772 | left = x86_pmu.max_period; | |
773 | ||
245b2e70 | 774 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
775 | |
776 | /* | |
cdd6c482 | 777 | * The hw event starts counting from this event offset, |
ee06094f IM |
778 | * mark it to be able to extra future deltas: |
779 | */ | |
e7850595 | 780 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 781 | |
73d6e522 | 782 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
783 | |
784 | /* | |
785 | * Due to erratum on certan cpu we need | |
786 | * a second write to be sure the register | |
787 | * is updated properly | |
788 | */ | |
789 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 790 | wrmsrl(hwc->event_base, |
948b1bb8 | 791 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 792 | } |
e4abb5d4 | 793 | |
cdd6c482 | 794 | perf_event_update_userpage(event); |
194002b2 | 795 | |
e4abb5d4 | 796 | return ret; |
2f18d1e8 IM |
797 | } |
798 | ||
de0428a7 | 799 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 800 | { |
0a3aee0d | 801 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
802 | __x86_pmu_enable_event(&event->hw, |
803 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
804 | } |
805 | ||
b690081d | 806 | /* |
a4eaf7f1 | 807 | * Add a single event to the PMU. |
1da53e02 SE |
808 | * |
809 | * The event is added to the group of enabled events | |
810 | * but only if it can be scehduled with existing events. | |
fe9081cc | 811 | */ |
a4eaf7f1 | 812 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
813 | { |
814 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
815 | struct hw_perf_event *hwc; |
816 | int assign[X86_PMC_IDX_MAX]; | |
817 | int n, n0, ret; | |
fe9081cc | 818 | |
1da53e02 | 819 | hwc = &event->hw; |
fe9081cc | 820 | |
33696fc0 | 821 | perf_pmu_disable(event->pmu); |
1da53e02 | 822 | n0 = cpuc->n_events; |
24cd7f54 PZ |
823 | ret = n = collect_events(cpuc, event, false); |
824 | if (ret < 0) | |
825 | goto out; | |
53b441a5 | 826 | |
a4eaf7f1 PZ |
827 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
828 | if (!(flags & PERF_EF_START)) | |
829 | hwc->state |= PERF_HES_ARCH; | |
830 | ||
4d1c52b0 LM |
831 | /* |
832 | * If group events scheduling transaction was started, | |
0d2eb44f | 833 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 834 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 835 | */ |
8d2cacbb | 836 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 837 | goto done_collect; |
4d1c52b0 | 838 | |
a072738e | 839 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 840 | if (ret) |
24cd7f54 | 841 | goto out; |
1da53e02 SE |
842 | /* |
843 | * copy new assignment, now we know it is possible | |
844 | * will be used by hw_perf_enable() | |
845 | */ | |
846 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 847 | |
24cd7f54 | 848 | done_collect: |
1da53e02 | 849 | cpuc->n_events = n; |
356e1f2e | 850 | cpuc->n_added += n - n0; |
90151c35 | 851 | cpuc->n_txn += n - n0; |
95cdd2e7 | 852 | |
24cd7f54 PZ |
853 | ret = 0; |
854 | out: | |
33696fc0 | 855 | perf_pmu_enable(event->pmu); |
24cd7f54 | 856 | return ret; |
241771ef IM |
857 | } |
858 | ||
a4eaf7f1 | 859 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 860 | { |
c08053e6 PZ |
861 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
862 | int idx = event->hw.idx; | |
863 | ||
a4eaf7f1 PZ |
864 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
865 | return; | |
866 | ||
867 | if (WARN_ON_ONCE(idx == -1)) | |
868 | return; | |
869 | ||
870 | if (flags & PERF_EF_RELOAD) { | |
871 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
872 | x86_perf_event_set_period(event); | |
873 | } | |
874 | ||
875 | event->hw.state = 0; | |
d76a0812 | 876 | |
c08053e6 PZ |
877 | cpuc->events[idx] = event; |
878 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 879 | __set_bit(idx, cpuc->running); |
aff3d91a | 880 | x86_pmu.enable(event); |
c08053e6 | 881 | perf_event_update_userpage(event); |
a78ac325 PZ |
882 | } |
883 | ||
cdd6c482 | 884 | void perf_event_print_debug(void) |
241771ef | 885 | { |
2f18d1e8 | 886 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 887 | u64 pebs; |
cdd6c482 | 888 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 889 | unsigned long flags; |
1e125676 IM |
890 | int cpu, idx; |
891 | ||
948b1bb8 | 892 | if (!x86_pmu.num_counters) |
1e125676 | 893 | return; |
241771ef | 894 | |
5bb9efe3 | 895 | local_irq_save(flags); |
241771ef IM |
896 | |
897 | cpu = smp_processor_id(); | |
cdd6c482 | 898 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 899 | |
faa28ae0 | 900 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
901 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
902 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
903 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
904 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 905 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
906 | |
907 | pr_info("\n"); | |
908 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
909 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
910 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
911 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 912 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 913 | } |
7645a24c | 914 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 915 | |
948b1bb8 | 916 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
917 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
918 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 919 | |
245b2e70 | 920 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 921 | |
a1ef58f4 | 922 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 923 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 924 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 925 | cpu, idx, pmc_count); |
a1ef58f4 | 926 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 927 | cpu, idx, prev_left); |
241771ef | 928 | } |
948b1bb8 | 929 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
930 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
931 | ||
a1ef58f4 | 932 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
933 | cpu, idx, pmc_count); |
934 | } | |
5bb9efe3 | 935 | local_irq_restore(flags); |
241771ef IM |
936 | } |
937 | ||
de0428a7 | 938 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 939 | { |
d76a0812 | 940 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 941 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 942 | |
a4eaf7f1 PZ |
943 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
944 | x86_pmu.disable(event); | |
945 | cpuc->events[hwc->idx] = NULL; | |
946 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
947 | hwc->state |= PERF_HES_STOPPED; | |
948 | } | |
30dd568c | 949 | |
a4eaf7f1 PZ |
950 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
951 | /* | |
952 | * Drain the remaining delta count out of a event | |
953 | * that we are disabling: | |
954 | */ | |
955 | x86_perf_event_update(event); | |
956 | hwc->state |= PERF_HES_UPTODATE; | |
957 | } | |
2e841873 PZ |
958 | } |
959 | ||
a4eaf7f1 | 960 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
961 | { |
962 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
963 | int i; | |
964 | ||
90151c35 SE |
965 | /* |
966 | * If we're called during a txn, we don't need to do anything. | |
967 | * The events never got scheduled and ->cancel_txn will truncate | |
968 | * the event_list. | |
969 | */ | |
8d2cacbb | 970 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
971 | return; |
972 | ||
a4eaf7f1 | 973 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 974 | |
1da53e02 SE |
975 | for (i = 0; i < cpuc->n_events; i++) { |
976 | if (event == cpuc->event_list[i]) { | |
977 | ||
978 | if (x86_pmu.put_event_constraints) | |
979 | x86_pmu.put_event_constraints(cpuc, event); | |
980 | ||
981 | while (++i < cpuc->n_events) | |
982 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
983 | ||
984 | --cpuc->n_events; | |
6c9687ab | 985 | break; |
1da53e02 SE |
986 | } |
987 | } | |
cdd6c482 | 988 | perf_event_update_userpage(event); |
241771ef IM |
989 | } |
990 | ||
de0428a7 | 991 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 992 | { |
df1a132b | 993 | struct perf_sample_data data; |
cdd6c482 IM |
994 | struct cpu_hw_events *cpuc; |
995 | struct perf_event *event; | |
11d1578f | 996 | int idx, handled = 0; |
9029a5e3 IM |
997 | u64 val; |
998 | ||
dc1d628a | 999 | perf_sample_data_init(&data, 0); |
df1a132b | 1000 | |
cdd6c482 | 1001 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1002 | |
2bce5dac DZ |
1003 | /* |
1004 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1005 | * inside the nmi handler. As a result, the unmasking was pushed | |
1006 | * into all the nmi handlers. | |
1007 | * | |
1008 | * This generic handler doesn't seem to have any issues where the | |
1009 | * unmasking occurs so it was left at the top. | |
1010 | */ | |
1011 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1012 | ||
948b1bb8 | 1013 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1014 | if (!test_bit(idx, cpuc->active_mask)) { |
1015 | /* | |
1016 | * Though we deactivated the counter some cpus | |
1017 | * might still deliver spurious interrupts still | |
1018 | * in flight. Catch them: | |
1019 | */ | |
1020 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1021 | handled++; | |
a29aa8a7 | 1022 | continue; |
63e6be6d | 1023 | } |
962bf7a6 | 1024 | |
cdd6c482 | 1025 | event = cpuc->events[idx]; |
a4016a79 | 1026 | |
cc2ad4ba | 1027 | val = x86_perf_event_update(event); |
948b1bb8 | 1028 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1029 | continue; |
962bf7a6 | 1030 | |
9e350de3 | 1031 | /* |
cdd6c482 | 1032 | * event overflow |
9e350de3 | 1033 | */ |
4177c42a | 1034 | handled++; |
cdd6c482 | 1035 | data.period = event->hw.last_period; |
9e350de3 | 1036 | |
07088edb | 1037 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1038 | continue; |
1039 | ||
a8b0ca17 | 1040 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1041 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1042 | } |
962bf7a6 | 1043 | |
9e350de3 PZ |
1044 | if (handled) |
1045 | inc_irq_stat(apic_perf_irqs); | |
1046 | ||
a29aa8a7 RR |
1047 | return handled; |
1048 | } | |
39d81eab | 1049 | |
cdd6c482 | 1050 | void perf_events_lapic_init(void) |
241771ef | 1051 | { |
04da8a43 | 1052 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1053 | return; |
85cf9dba | 1054 | |
241771ef | 1055 | /* |
c323d95f | 1056 | * Always use NMI for PMU |
241771ef | 1057 | */ |
c323d95f | 1058 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1059 | } |
1060 | ||
1061 | static int __kprobes | |
9c48f1c6 | 1062 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1063 | { |
cdd6c482 | 1064 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1065 | return NMI_DONE; |
4177c42a | 1066 | |
9c48f1c6 | 1067 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1068 | } |
1069 | ||
de0428a7 KW |
1070 | struct event_constraint emptyconstraint; |
1071 | struct event_constraint unconstrained; | |
f87ad35d | 1072 | |
3f6da390 PZ |
1073 | static int __cpuinit |
1074 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1075 | { | |
1076 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1077 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1078 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1079 | |
1080 | switch (action & ~CPU_TASKS_FROZEN) { | |
1081 | case CPU_UP_PREPARE: | |
7fdba1ca | 1082 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1083 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1084 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1085 | break; |
1086 | ||
1087 | case CPU_STARTING: | |
1088 | if (x86_pmu.cpu_starting) | |
1089 | x86_pmu.cpu_starting(cpu); | |
1090 | break; | |
1091 | ||
7fdba1ca PZ |
1092 | case CPU_ONLINE: |
1093 | kfree(cpuc->kfree_on_online); | |
1094 | break; | |
1095 | ||
3f6da390 PZ |
1096 | case CPU_DYING: |
1097 | if (x86_pmu.cpu_dying) | |
1098 | x86_pmu.cpu_dying(cpu); | |
1099 | break; | |
1100 | ||
b38b24ea | 1101 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1102 | case CPU_DEAD: |
1103 | if (x86_pmu.cpu_dead) | |
1104 | x86_pmu.cpu_dead(cpu); | |
1105 | break; | |
1106 | ||
1107 | default: | |
1108 | break; | |
1109 | } | |
1110 | ||
b38b24ea | 1111 | return ret; |
3f6da390 PZ |
1112 | } |
1113 | ||
12558038 CG |
1114 | static void __init pmu_check_apic(void) |
1115 | { | |
1116 | if (cpu_has_apic) | |
1117 | return; | |
1118 | ||
1119 | x86_pmu.apic = 0; | |
1120 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1121 | pr_info("no hardware sampling interrupt available.\n"); | |
1122 | } | |
1123 | ||
dda99116 | 1124 | static int __init init_hw_perf_events(void) |
b56a3802 | 1125 | { |
b622d644 | 1126 | struct event_constraint *c; |
72eae04d RR |
1127 | int err; |
1128 | ||
cdd6c482 | 1129 | pr_info("Performance Events: "); |
1123e3ad | 1130 | |
b56a3802 JSR |
1131 | switch (boot_cpu_data.x86_vendor) { |
1132 | case X86_VENDOR_INTEL: | |
72eae04d | 1133 | err = intel_pmu_init(); |
b56a3802 | 1134 | break; |
f87ad35d | 1135 | case X86_VENDOR_AMD: |
72eae04d | 1136 | err = amd_pmu_init(); |
f87ad35d | 1137 | break; |
4138960a | 1138 | default: |
004417a6 | 1139 | return 0; |
b56a3802 | 1140 | } |
1123e3ad | 1141 | if (err != 0) { |
cdd6c482 | 1142 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1143 | return 0; |
1123e3ad | 1144 | } |
b56a3802 | 1145 | |
12558038 CG |
1146 | pmu_check_apic(); |
1147 | ||
33c6d6a7 | 1148 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1149 | if (!check_hw_exists()) |
004417a6 | 1150 | return 0; |
33c6d6a7 | 1151 | |
1123e3ad | 1152 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1153 | |
3c44780b PZ |
1154 | if (x86_pmu.quirks) |
1155 | x86_pmu.quirks(); | |
1156 | ||
948b1bb8 | 1157 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1158 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1159 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1160 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1161 | } |
948b1bb8 | 1162 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1163 | |
948b1bb8 | 1164 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1165 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1166 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1167 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1168 | } |
862a1a5f | 1169 | |
d6dc0b4e | 1170 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1171 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1172 | |
cdd6c482 | 1173 | perf_events_lapic_init(); |
9c48f1c6 | 1174 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1175 | |
63b14649 | 1176 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1177 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1178 | 0, x86_pmu.num_counters); | |
63b14649 | 1179 | |
b622d644 PZ |
1180 | if (x86_pmu.event_constraints) { |
1181 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1182 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1183 | continue; |
1184 | ||
948b1bb8 RR |
1185 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1186 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1187 | } |
1188 | } | |
1189 | ||
57c0c15b | 1190 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1191 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1192 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1193 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1194 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1195 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1196 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1197 | |
2e80a82a | 1198 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1199 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1200 | |
1201 | return 0; | |
241771ef | 1202 | } |
004417a6 | 1203 | early_initcall(init_hw_perf_events); |
621a01ea | 1204 | |
cdd6c482 | 1205 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1206 | { |
cc2ad4ba | 1207 | x86_perf_event_update(event); |
ee06094f IM |
1208 | } |
1209 | ||
4d1c52b0 LM |
1210 | /* |
1211 | * Start group events scheduling transaction | |
1212 | * Set the flag to make pmu::enable() not perform the | |
1213 | * schedulability test, it will be performed at commit time | |
1214 | */ | |
51b0fe39 | 1215 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1216 | { |
33696fc0 | 1217 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1218 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1219 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1220 | } |
1221 | ||
1222 | /* | |
1223 | * Stop group events scheduling transaction | |
1224 | * Clear the flag and pmu::enable() will perform the | |
1225 | * schedulability test. | |
1226 | */ | |
51b0fe39 | 1227 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1228 | { |
0a3aee0d | 1229 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1230 | /* |
1231 | * Truncate the collected events. | |
1232 | */ | |
0a3aee0d TH |
1233 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1234 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1235 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1236 | } |
1237 | ||
1238 | /* | |
1239 | * Commit group events scheduling transaction | |
1240 | * Perform the group schedulability test as a whole | |
1241 | * Return 0 if success | |
1242 | */ | |
51b0fe39 | 1243 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1244 | { |
1245 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1246 | int assign[X86_PMC_IDX_MAX]; | |
1247 | int n, ret; | |
1248 | ||
1249 | n = cpuc->n_events; | |
1250 | ||
1251 | if (!x86_pmu_initialized()) | |
1252 | return -EAGAIN; | |
1253 | ||
1254 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1255 | if (ret) | |
1256 | return ret; | |
1257 | ||
1258 | /* | |
1259 | * copy new assignment, now we know it is possible | |
1260 | * will be used by hw_perf_enable() | |
1261 | */ | |
1262 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1263 | ||
8d2cacbb | 1264 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1265 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1266 | return 0; |
1267 | } | |
cd8a38d3 SE |
1268 | /* |
1269 | * a fake_cpuc is used to validate event groups. Due to | |
1270 | * the extra reg logic, we need to also allocate a fake | |
1271 | * per_core and per_cpu structure. Otherwise, group events | |
1272 | * using extra reg may conflict without the kernel being | |
1273 | * able to catch this when the last event gets added to | |
1274 | * the group. | |
1275 | */ | |
1276 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1277 | { | |
1278 | kfree(cpuc->shared_regs); | |
1279 | kfree(cpuc); | |
1280 | } | |
1281 | ||
1282 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1283 | { | |
1284 | struct cpu_hw_events *cpuc; | |
1285 | int cpu = raw_smp_processor_id(); | |
1286 | ||
1287 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1288 | if (!cpuc) | |
1289 | return ERR_PTR(-ENOMEM); | |
1290 | ||
1291 | /* only needed, if we have extra_regs */ | |
1292 | if (x86_pmu.extra_regs) { | |
1293 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1294 | if (!cpuc->shared_regs) | |
1295 | goto error; | |
1296 | } | |
1297 | return cpuc; | |
1298 | error: | |
1299 | free_fake_cpuc(cpuc); | |
1300 | return ERR_PTR(-ENOMEM); | |
1301 | } | |
4d1c52b0 | 1302 | |
ca037701 PZ |
1303 | /* |
1304 | * validate that we can schedule this event | |
1305 | */ | |
1306 | static int validate_event(struct perf_event *event) | |
1307 | { | |
1308 | struct cpu_hw_events *fake_cpuc; | |
1309 | struct event_constraint *c; | |
1310 | int ret = 0; | |
1311 | ||
cd8a38d3 SE |
1312 | fake_cpuc = allocate_fake_cpuc(); |
1313 | if (IS_ERR(fake_cpuc)) | |
1314 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1315 | |
1316 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1317 | ||
1318 | if (!c || !c->weight) | |
1319 | ret = -ENOSPC; | |
1320 | ||
1321 | if (x86_pmu.put_event_constraints) | |
1322 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1323 | ||
cd8a38d3 | 1324 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1325 | |
1326 | return ret; | |
1327 | } | |
1328 | ||
1da53e02 SE |
1329 | /* |
1330 | * validate a single event group | |
1331 | * | |
1332 | * validation include: | |
184f412c IM |
1333 | * - check events are compatible which each other |
1334 | * - events do not compete for the same counter | |
1335 | * - number of events <= number of counters | |
1da53e02 SE |
1336 | * |
1337 | * validation ensures the group can be loaded onto the | |
1338 | * PMU if it was the only group available. | |
1339 | */ | |
fe9081cc PZ |
1340 | static int validate_group(struct perf_event *event) |
1341 | { | |
1da53e02 | 1342 | struct perf_event *leader = event->group_leader; |
502568d5 | 1343 | struct cpu_hw_events *fake_cpuc; |
cd8a38d3 | 1344 | int ret = -ENOSPC, n; |
fe9081cc | 1345 | |
cd8a38d3 SE |
1346 | fake_cpuc = allocate_fake_cpuc(); |
1347 | if (IS_ERR(fake_cpuc)) | |
1348 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1349 | /* |
1350 | * the event is not yet connected with its | |
1351 | * siblings therefore we must first collect | |
1352 | * existing siblings, then add the new event | |
1353 | * before we can simulate the scheduling | |
1354 | */ | |
502568d5 | 1355 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1356 | if (n < 0) |
cd8a38d3 | 1357 | goto out; |
fe9081cc | 1358 | |
502568d5 PZ |
1359 | fake_cpuc->n_events = n; |
1360 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1361 | if (n < 0) |
cd8a38d3 | 1362 | goto out; |
fe9081cc | 1363 | |
502568d5 | 1364 | fake_cpuc->n_events = n; |
1da53e02 | 1365 | |
a072738e | 1366 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1367 | |
502568d5 | 1368 | out: |
cd8a38d3 | 1369 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1370 | return ret; |
fe9081cc PZ |
1371 | } |
1372 | ||
dda99116 | 1373 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1374 | { |
51b0fe39 | 1375 | struct pmu *tmp; |
621a01ea IM |
1376 | int err; |
1377 | ||
b0a873eb PZ |
1378 | switch (event->attr.type) { |
1379 | case PERF_TYPE_RAW: | |
1380 | case PERF_TYPE_HARDWARE: | |
1381 | case PERF_TYPE_HW_CACHE: | |
1382 | break; | |
1383 | ||
1384 | default: | |
1385 | return -ENOENT; | |
1386 | } | |
1387 | ||
1388 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1389 | if (!err) { |
8113070d SE |
1390 | /* |
1391 | * we temporarily connect event to its pmu | |
1392 | * such that validate_group() can classify | |
1393 | * it as an x86 event using is_x86_event() | |
1394 | */ | |
1395 | tmp = event->pmu; | |
1396 | event->pmu = &pmu; | |
1397 | ||
fe9081cc PZ |
1398 | if (event->group_leader != event) |
1399 | err = validate_group(event); | |
ca037701 PZ |
1400 | else |
1401 | err = validate_event(event); | |
8113070d SE |
1402 | |
1403 | event->pmu = tmp; | |
fe9081cc | 1404 | } |
a1792cda | 1405 | if (err) { |
cdd6c482 IM |
1406 | if (event->destroy) |
1407 | event->destroy(event); | |
a1792cda | 1408 | } |
621a01ea | 1409 | |
b0a873eb | 1410 | return err; |
621a01ea | 1411 | } |
d7d59fb3 | 1412 | |
b0a873eb | 1413 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1414 | .pmu_enable = x86_pmu_enable, |
1415 | .pmu_disable = x86_pmu_disable, | |
1416 | ||
b0a873eb | 1417 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1418 | |
1419 | .add = x86_pmu_add, | |
1420 | .del = x86_pmu_del, | |
b0a873eb PZ |
1421 | .start = x86_pmu_start, |
1422 | .stop = x86_pmu_stop, | |
1423 | .read = x86_pmu_read, | |
a4eaf7f1 | 1424 | |
b0a873eb PZ |
1425 | .start_txn = x86_pmu_start_txn, |
1426 | .cancel_txn = x86_pmu_cancel_txn, | |
1427 | .commit_txn = x86_pmu_commit_txn, | |
1428 | }; | |
1429 | ||
d7d59fb3 PZ |
1430 | /* |
1431 | * callchain support | |
1432 | */ | |
1433 | ||
d7d59fb3 PZ |
1434 | static int backtrace_stack(void *data, char *name) |
1435 | { | |
038e836e | 1436 | return 0; |
d7d59fb3 PZ |
1437 | } |
1438 | ||
1439 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1440 | { | |
1441 | struct perf_callchain_entry *entry = data; | |
1442 | ||
70791ce9 | 1443 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1444 | } |
1445 | ||
1446 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1447 | .stack = backtrace_stack, |
1448 | .address = backtrace_address, | |
06d65bda | 1449 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1450 | }; |
1451 | ||
56962b44 FW |
1452 | void |
1453 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1454 | { |
927c7a9e FW |
1455 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1456 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1457 | return; |
927c7a9e FW |
1458 | } |
1459 | ||
70791ce9 | 1460 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1461 | |
e8e999cf | 1462 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1463 | } |
1464 | ||
257ef9d2 TE |
1465 | #ifdef CONFIG_COMPAT |
1466 | static inline int | |
1467 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1468 | { |
257ef9d2 TE |
1469 | /* 32-bit process in 64-bit kernel. */ |
1470 | struct stack_frame_ia32 frame; | |
1471 | const void __user *fp; | |
74193ef0 | 1472 | |
257ef9d2 TE |
1473 | if (!test_thread_flag(TIF_IA32)) |
1474 | return 0; | |
1475 | ||
1476 | fp = compat_ptr(regs->bp); | |
1477 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1478 | unsigned long bytes; | |
1479 | frame.next_frame = 0; | |
1480 | frame.return_address = 0; | |
1481 | ||
1482 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1483 | if (bytes != sizeof(frame)) | |
1484 | break; | |
74193ef0 | 1485 | |
257ef9d2 TE |
1486 | if (fp < compat_ptr(regs->sp)) |
1487 | break; | |
74193ef0 | 1488 | |
70791ce9 | 1489 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1490 | fp = compat_ptr(frame.next_frame); |
1491 | } | |
1492 | return 1; | |
d7d59fb3 | 1493 | } |
257ef9d2 TE |
1494 | #else |
1495 | static inline int | |
1496 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1497 | { | |
1498 | return 0; | |
1499 | } | |
1500 | #endif | |
d7d59fb3 | 1501 | |
56962b44 FW |
1502 | void |
1503 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1504 | { |
1505 | struct stack_frame frame; | |
1506 | const void __user *fp; | |
1507 | ||
927c7a9e FW |
1508 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1509 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1510 | return; |
927c7a9e | 1511 | } |
5a6cec3a | 1512 | |
74193ef0 | 1513 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1514 | |
70791ce9 | 1515 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1516 | |
20afc60f AV |
1517 | if (!current->mm) |
1518 | return; | |
1519 | ||
257ef9d2 TE |
1520 | if (perf_callchain_user32(regs, entry)) |
1521 | return; | |
1522 | ||
f9188e02 | 1523 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1524 | unsigned long bytes; |
038e836e | 1525 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1526 | frame.return_address = 0; |
1527 | ||
257ef9d2 TE |
1528 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1529 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1530 | break; |
1531 | ||
5a6cec3a | 1532 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1533 | break; |
1534 | ||
70791ce9 | 1535 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1536 | fp = frame.next_frame; |
d7d59fb3 PZ |
1537 | } |
1538 | } | |
1539 | ||
39447b38 ZY |
1540 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1541 | { | |
1542 | unsigned long ip; | |
dcf46b94 | 1543 | |
39447b38 ZY |
1544 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1545 | ip = perf_guest_cbs->get_guest_ip(); | |
1546 | else | |
1547 | ip = instruction_pointer(regs); | |
dcf46b94 | 1548 | |
39447b38 ZY |
1549 | return ip; |
1550 | } | |
1551 | ||
1552 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1553 | { | |
1554 | int misc = 0; | |
dcf46b94 | 1555 | |
39447b38 | 1556 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1557 | if (perf_guest_cbs->is_user_mode()) |
1558 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1559 | else | |
1560 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1561 | } else { | |
1562 | if (user_mode(regs)) | |
1563 | misc |= PERF_RECORD_MISC_USER; | |
1564 | else | |
1565 | misc |= PERF_RECORD_MISC_KERNEL; | |
1566 | } | |
1567 | ||
39447b38 | 1568 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1569 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1570 | |
1571 | return misc; | |
1572 | } |