Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
d07bdfd3 PZ |
35 | #include <asm/desc.h> |
36 | #include <asm/ldt.h> | |
241771ef | 37 | |
de0428a7 KW |
38 | #include "perf_event.h" |
39 | ||
de0428a7 | 40 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 41 | |
de0428a7 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
43 | .enabled = 1, |
44 | }; | |
241771ef | 45 | |
de0428a7 | 46 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
47 | [PERF_COUNT_HW_CACHE_MAX] |
48 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
49 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 50 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 54 | |
ee06094f | 55 | /* |
cdd6c482 IM |
56 | * Propagate event elapsed time into the generic event. |
57 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
58 | * Returns the delta events processed. |
59 | */ | |
de0428a7 | 60 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 61 | { |
cc2ad4ba | 62 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 63 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 64 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 65 | int idx = hwc->idx; |
ec3232bd | 66 | s64 delta; |
ee06094f | 67 | |
15c7ad51 | 68 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
69 | return 0; |
70 | ||
ee06094f | 71 | /* |
cdd6c482 | 72 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
73 | * |
74 | * Our tactic to handle this is to first atomically read and | |
75 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 76 | * count to the generic event atomically: |
ee06094f IM |
77 | */ |
78 | again: | |
e7850595 | 79 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 80 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 81 | |
e7850595 | 82 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
83 | new_raw_count) != prev_raw_count) |
84 | goto again; | |
85 | ||
86 | /* | |
87 | * Now we have the new raw value and have updated the prev | |
88 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 89 | * (event-)time and add that to the generic event. |
ee06094f IM |
90 | * |
91 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 92 | * of the count. |
ee06094f | 93 | */ |
ec3232bd PZ |
94 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
95 | delta >>= shift; | |
ee06094f | 96 | |
e7850595 PZ |
97 | local64_add(delta, &event->count); |
98 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
99 | |
100 | return new_raw_count; | |
ee06094f IM |
101 | } |
102 | ||
a7e3ed1e AK |
103 | /* |
104 | * Find and validate any extra registers to set up. | |
105 | */ | |
106 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
107 | { | |
efc9f05d | 108 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
109 | struct extra_reg *er; |
110 | ||
efc9f05d | 111 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
112 | |
113 | if (!x86_pmu.extra_regs) | |
114 | return 0; | |
115 | ||
116 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
117 | if (er->event != (config & er->config_mask)) | |
118 | continue; | |
119 | if (event->attr.config1 & ~er->valid_mask) | |
120 | return -EINVAL; | |
efc9f05d SE |
121 | |
122 | reg->idx = er->idx; | |
123 | reg->config = event->attr.config1; | |
124 | reg->reg = er->msr; | |
a7e3ed1e AK |
125 | break; |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
cdd6c482 | 130 | static atomic_t active_events; |
4e935e47 PZ |
131 | static DEFINE_MUTEX(pmc_reserve_mutex); |
132 | ||
b27ea29c RR |
133 | #ifdef CONFIG_X86_LOCAL_APIC |
134 | ||
4e935e47 PZ |
135 | static bool reserve_pmc_hardware(void) |
136 | { | |
137 | int i; | |
138 | ||
948b1bb8 | 139 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 140 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
141 | goto perfctr_fail; |
142 | } | |
143 | ||
948b1bb8 | 144 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 145 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
146 | goto eventsel_fail; |
147 | } | |
148 | ||
149 | return true; | |
150 | ||
151 | eventsel_fail: | |
152 | for (i--; i >= 0; i--) | |
41bf4989 | 153 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 154 | |
948b1bb8 | 155 | i = x86_pmu.num_counters; |
4e935e47 PZ |
156 | |
157 | perfctr_fail: | |
158 | for (i--; i >= 0; i--) | |
41bf4989 | 159 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 160 | |
4e935e47 PZ |
161 | return false; |
162 | } | |
163 | ||
164 | static void release_pmc_hardware(void) | |
165 | { | |
166 | int i; | |
167 | ||
948b1bb8 | 168 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
169 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
170 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 171 | } |
4e935e47 PZ |
172 | } |
173 | ||
b27ea29c RR |
174 | #else |
175 | ||
176 | static bool reserve_pmc_hardware(void) { return true; } | |
177 | static void release_pmc_hardware(void) {} | |
178 | ||
179 | #endif | |
180 | ||
33c6d6a7 DZ |
181 | static bool check_hw_exists(void) |
182 | { | |
a5ebe0ba GD |
183 | u64 val, val_fail, val_new= ~0; |
184 | int i, reg, reg_fail, ret = 0; | |
185 | int bios_fail = 0; | |
33c6d6a7 | 186 | |
4407204c PZ |
187 | /* |
188 | * Check to see if the BIOS enabled any of the counters, if so | |
189 | * complain and bail. | |
190 | */ | |
191 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 192 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
193 | ret = rdmsrl_safe(reg, &val); |
194 | if (ret) | |
195 | goto msr_fail; | |
a5ebe0ba GD |
196 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
197 | bios_fail = 1; | |
198 | val_fail = val; | |
199 | reg_fail = reg; | |
200 | } | |
4407204c PZ |
201 | } |
202 | ||
203 | if (x86_pmu.num_counters_fixed) { | |
204 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
205 | ret = rdmsrl_safe(reg, &val); | |
206 | if (ret) | |
207 | goto msr_fail; | |
208 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
209 | if (val & (0x03 << i*4)) { |
210 | bios_fail = 1; | |
211 | val_fail = val; | |
212 | reg_fail = reg; | |
213 | } | |
4407204c PZ |
214 | } |
215 | } | |
216 | ||
217 | /* | |
bffd5fc2 AP |
218 | * Read the current value, change it and read it back to see if it |
219 | * matches, this is needed to detect certain hardware emulators | |
220 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 221 | */ |
f285f92f | 222 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
223 | if (rdmsrl_safe(reg, &val)) |
224 | goto msr_fail; | |
225 | val ^= 0xffffUL; | |
f285f92f RR |
226 | ret = wrmsrl_safe(reg, val); |
227 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 228 | if (ret || val != val_new) |
4407204c | 229 | goto msr_fail; |
33c6d6a7 | 230 | |
45daae57 IM |
231 | /* |
232 | * We still allow the PMU driver to operate: | |
233 | */ | |
a5ebe0ba GD |
234 | if (bios_fail) { |
235 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
236 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
237 | } | |
45daae57 IM |
238 | |
239 | return true; | |
4407204c PZ |
240 | |
241 | msr_fail: | |
242 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
f285f92f | 243 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); |
45daae57 | 244 | |
4407204c | 245 | return false; |
33c6d6a7 DZ |
246 | } |
247 | ||
cdd6c482 | 248 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 249 | { |
cdd6c482 | 250 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 251 | release_pmc_hardware(); |
ca037701 | 252 | release_ds_buffers(); |
4e935e47 PZ |
253 | mutex_unlock(&pmc_reserve_mutex); |
254 | } | |
255 | } | |
256 | ||
85cf9dba RR |
257 | static inline int x86_pmu_initialized(void) |
258 | { | |
259 | return x86_pmu.handle_irq != NULL; | |
260 | } | |
261 | ||
8326f44d | 262 | static inline int |
e994d7d2 | 263 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 264 | { |
e994d7d2 | 265 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
266 | unsigned int cache_type, cache_op, cache_result; |
267 | u64 config, val; | |
268 | ||
269 | config = attr->config; | |
270 | ||
271 | cache_type = (config >> 0) & 0xff; | |
272 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
273 | return -EINVAL; | |
274 | ||
275 | cache_op = (config >> 8) & 0xff; | |
276 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
277 | return -EINVAL; | |
278 | ||
279 | cache_result = (config >> 16) & 0xff; | |
280 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
281 | return -EINVAL; | |
282 | ||
283 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
284 | ||
285 | if (val == 0) | |
286 | return -ENOENT; | |
287 | ||
288 | if (val == -1) | |
289 | return -EINVAL; | |
290 | ||
291 | hwc->config |= val; | |
e994d7d2 AK |
292 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
293 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
294 | } |
295 | ||
de0428a7 | 296 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
297 | { |
298 | struct perf_event_attr *attr = &event->attr; | |
299 | struct hw_perf_event *hwc = &event->hw; | |
300 | u64 config; | |
301 | ||
6c7e550f | 302 | if (!is_sampling_event(event)) { |
c1726f34 RR |
303 | hwc->sample_period = x86_pmu.max_period; |
304 | hwc->last_period = hwc->sample_period; | |
e7850595 | 305 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
306 | } else { |
307 | /* | |
308 | * If we have a PMU initialized but no APIC | |
309 | * interrupts, we cannot sample hardware | |
310 | * events (user-space has to fall back and | |
311 | * sample via a hrtimer based software event): | |
312 | */ | |
313 | if (!x86_pmu.apic) | |
314 | return -EOPNOTSUPP; | |
315 | } | |
316 | ||
317 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 318 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
319 | |
320 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 321 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
322 | |
323 | if (attr->config >= x86_pmu.max_events) | |
324 | return -EINVAL; | |
325 | ||
326 | /* | |
327 | * The generic map: | |
328 | */ | |
329 | config = x86_pmu.event_map(attr->config); | |
330 | ||
331 | if (config == 0) | |
332 | return -ENOENT; | |
333 | ||
334 | if (config == -1LL) | |
335 | return -EINVAL; | |
336 | ||
337 | /* | |
338 | * Branch tracing: | |
339 | */ | |
18a073a3 PZ |
340 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
341 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 342 | /* BTS is not supported by this architecture. */ |
6809b6ea | 343 | if (!x86_pmu.bts_active) |
c1726f34 RR |
344 | return -EOPNOTSUPP; |
345 | ||
346 | /* BTS is currently only allowed for user-mode. */ | |
347 | if (!attr->exclude_kernel) | |
348 | return -EOPNOTSUPP; | |
349 | } | |
350 | ||
351 | hwc->config |= config; | |
352 | ||
353 | return 0; | |
354 | } | |
4261e0e0 | 355 | |
ff3fb511 SE |
356 | /* |
357 | * check that branch_sample_type is compatible with | |
358 | * settings needed for precise_ip > 1 which implies | |
359 | * using the LBR to capture ALL taken branches at the | |
360 | * priv levels of the measurement | |
361 | */ | |
362 | static inline int precise_br_compat(struct perf_event *event) | |
363 | { | |
364 | u64 m = event->attr.branch_sample_type; | |
365 | u64 b = 0; | |
366 | ||
367 | /* must capture all branches */ | |
368 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
369 | return 0; | |
370 | ||
371 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
372 | ||
373 | if (!event->attr.exclude_user) | |
374 | b |= PERF_SAMPLE_BRANCH_USER; | |
375 | ||
376 | if (!event->attr.exclude_kernel) | |
377 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
378 | ||
379 | /* | |
380 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
381 | */ | |
382 | ||
383 | return m == b; | |
384 | } | |
385 | ||
de0428a7 | 386 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 387 | { |
ab608344 PZ |
388 | if (event->attr.precise_ip) { |
389 | int precise = 0; | |
390 | ||
391 | /* Support for constant skid */ | |
c93dc84c | 392 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
393 | precise++; |
394 | ||
5553be26 PZ |
395 | /* Support for IP fixup */ |
396 | if (x86_pmu.lbr_nr) | |
397 | precise++; | |
398 | } | |
ab608344 PZ |
399 | |
400 | if (event->attr.precise_ip > precise) | |
401 | return -EOPNOTSUPP; | |
ff3fb511 SE |
402 | /* |
403 | * check that PEBS LBR correction does not conflict with | |
404 | * whatever the user is asking with attr->branch_sample_type | |
405 | */ | |
130768b8 AK |
406 | if (event->attr.precise_ip > 1 && |
407 | x86_pmu.intel_cap.pebs_format < 2) { | |
ff3fb511 SE |
408 | u64 *br_type = &event->attr.branch_sample_type; |
409 | ||
410 | if (has_branch_stack(event)) { | |
411 | if (!precise_br_compat(event)) | |
412 | return -EOPNOTSUPP; | |
413 | ||
414 | /* branch_sample_type is compatible */ | |
415 | ||
416 | } else { | |
417 | /* | |
418 | * user did not specify branch_sample_type | |
419 | * | |
420 | * For PEBS fixups, we capture all | |
421 | * the branches at the priv level of the | |
422 | * event. | |
423 | */ | |
424 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
425 | ||
426 | if (!event->attr.exclude_user) | |
427 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
428 | ||
429 | if (!event->attr.exclude_kernel) | |
430 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
431 | } | |
432 | } | |
ab608344 PZ |
433 | } |
434 | ||
a072738e CG |
435 | /* |
436 | * Generate PMC IRQs: | |
437 | * (keep 'enabled' bit clear for now) | |
438 | */ | |
b4cdc5c2 | 439 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
440 | |
441 | /* | |
442 | * Count user and OS events unless requested not to | |
443 | */ | |
b4cdc5c2 PZ |
444 | if (!event->attr.exclude_user) |
445 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
446 | if (!event->attr.exclude_kernel) | |
447 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 448 | |
b4cdc5c2 PZ |
449 | if (event->attr.type == PERF_TYPE_RAW) |
450 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 451 | |
9d0fcba6 | 452 | return x86_setup_perfctr(event); |
a098f448 RR |
453 | } |
454 | ||
241771ef | 455 | /* |
0d48696f | 456 | * Setup the hardware configuration for a given attr_type |
241771ef | 457 | */ |
b0a873eb | 458 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 459 | { |
4e935e47 | 460 | int err; |
241771ef | 461 | |
85cf9dba RR |
462 | if (!x86_pmu_initialized()) |
463 | return -ENODEV; | |
241771ef | 464 | |
4e935e47 | 465 | err = 0; |
cdd6c482 | 466 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 467 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 468 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
469 | if (!reserve_pmc_hardware()) |
470 | err = -EBUSY; | |
f80c9e30 PZ |
471 | else |
472 | reserve_ds_buffers(); | |
30dd568c MM |
473 | } |
474 | if (!err) | |
cdd6c482 | 475 | atomic_inc(&active_events); |
4e935e47 PZ |
476 | mutex_unlock(&pmc_reserve_mutex); |
477 | } | |
478 | if (err) | |
479 | return err; | |
480 | ||
cdd6c482 | 481 | event->destroy = hw_perf_event_destroy; |
a1792cda | 482 | |
4261e0e0 RR |
483 | event->hw.idx = -1; |
484 | event->hw.last_cpu = -1; | |
485 | event->hw.last_tag = ~0ULL; | |
b690081d | 486 | |
efc9f05d SE |
487 | /* mark unused */ |
488 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
489 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
490 | ||
9d0fcba6 | 491 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
492 | } |
493 | ||
de0428a7 | 494 | void x86_pmu_disable_all(void) |
f87ad35d | 495 | { |
cdd6c482 | 496 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
497 | int idx; |
498 | ||
948b1bb8 | 499 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
500 | u64 val; |
501 | ||
43f6201a | 502 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 503 | continue; |
41bf4989 | 504 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 505 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 506 | continue; |
bb1165d6 | 507 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 508 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 509 | } |
f87ad35d JSR |
510 | } |
511 | ||
a4eaf7f1 | 512 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 513 | { |
1da53e02 SE |
514 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
515 | ||
85cf9dba | 516 | if (!x86_pmu_initialized()) |
9e35ad38 | 517 | return; |
1da53e02 | 518 | |
1a6e21f7 PZ |
519 | if (!cpuc->enabled) |
520 | return; | |
521 | ||
522 | cpuc->n_added = 0; | |
523 | cpuc->enabled = 0; | |
524 | barrier(); | |
1da53e02 SE |
525 | |
526 | x86_pmu.disable_all(); | |
b56a3802 | 527 | } |
241771ef | 528 | |
de0428a7 | 529 | void x86_pmu_enable_all(int added) |
f87ad35d | 530 | { |
cdd6c482 | 531 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
532 | int idx; |
533 | ||
948b1bb8 | 534 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 535 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 536 | |
43f6201a | 537 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 538 | continue; |
984b838c | 539 | |
d45dd923 | 540 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
541 | } |
542 | } | |
543 | ||
51b0fe39 | 544 | static struct pmu pmu; |
1da53e02 SE |
545 | |
546 | static inline int is_x86_event(struct perf_event *event) | |
547 | { | |
548 | return event->pmu == &pmu; | |
549 | } | |
550 | ||
1e2ad28f RR |
551 | /* |
552 | * Event scheduler state: | |
553 | * | |
554 | * Assign events iterating over all events and counters, beginning | |
555 | * with events with least weights first. Keep the current iterator | |
556 | * state in struct sched_state. | |
557 | */ | |
558 | struct sched_state { | |
559 | int weight; | |
560 | int event; /* event index */ | |
561 | int counter; /* counter index */ | |
562 | int unassigned; /* number of events to be assigned left */ | |
563 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
564 | }; | |
565 | ||
bc1738f6 RR |
566 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
567 | #define SCHED_STATES_MAX 2 | |
568 | ||
1e2ad28f RR |
569 | struct perf_sched { |
570 | int max_weight; | |
571 | int max_events; | |
43b45780 | 572 | struct perf_event **events; |
1e2ad28f | 573 | struct sched_state state; |
bc1738f6 RR |
574 | int saved_states; |
575 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
576 | }; |
577 | ||
578 | /* | |
579 | * Initialize interator that runs through all events and counters. | |
580 | */ | |
43b45780 | 581 | static void perf_sched_init(struct perf_sched *sched, struct perf_event **events, |
1e2ad28f RR |
582 | int num, int wmin, int wmax) |
583 | { | |
584 | int idx; | |
585 | ||
586 | memset(sched, 0, sizeof(*sched)); | |
587 | sched->max_events = num; | |
588 | sched->max_weight = wmax; | |
43b45780 | 589 | sched->events = events; |
1e2ad28f RR |
590 | |
591 | for (idx = 0; idx < num; idx++) { | |
43b45780 | 592 | if (events[idx]->hw.constraint->weight == wmin) |
1e2ad28f RR |
593 | break; |
594 | } | |
595 | ||
596 | sched->state.event = idx; /* start with min weight */ | |
597 | sched->state.weight = wmin; | |
598 | sched->state.unassigned = num; | |
599 | } | |
600 | ||
bc1738f6 RR |
601 | static void perf_sched_save_state(struct perf_sched *sched) |
602 | { | |
603 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
604 | return; | |
605 | ||
606 | sched->saved[sched->saved_states] = sched->state; | |
607 | sched->saved_states++; | |
608 | } | |
609 | ||
610 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
611 | { | |
612 | if (!sched->saved_states) | |
613 | return false; | |
614 | ||
615 | sched->saved_states--; | |
616 | sched->state = sched->saved[sched->saved_states]; | |
617 | ||
618 | /* continue with next counter: */ | |
619 | clear_bit(sched->state.counter++, sched->state.used); | |
620 | ||
621 | return true; | |
622 | } | |
623 | ||
1e2ad28f RR |
624 | /* |
625 | * Select a counter for the current event to schedule. Return true on | |
626 | * success. | |
627 | */ | |
bc1738f6 | 628 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
629 | { |
630 | struct event_constraint *c; | |
631 | int idx; | |
632 | ||
633 | if (!sched->state.unassigned) | |
634 | return false; | |
635 | ||
636 | if (sched->state.event >= sched->max_events) | |
637 | return false; | |
638 | ||
43b45780 | 639 | c = sched->events[sched->state.event]->hw.constraint; |
4defea85 | 640 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
641 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
642 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 643 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
644 | if (!__test_and_set_bit(idx, sched->state.used)) |
645 | goto done; | |
646 | } | |
647 | } | |
1e2ad28f RR |
648 | /* Grab the first unused counter starting with idx */ |
649 | idx = sched->state.counter; | |
15c7ad51 | 650 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 651 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 652 | goto done; |
1e2ad28f | 653 | } |
1e2ad28f | 654 | |
4defea85 PZ |
655 | return false; |
656 | ||
657 | done: | |
658 | sched->state.counter = idx; | |
1e2ad28f | 659 | |
bc1738f6 RR |
660 | if (c->overlap) |
661 | perf_sched_save_state(sched); | |
662 | ||
663 | return true; | |
664 | } | |
665 | ||
666 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
667 | { | |
668 | while (!__perf_sched_find_counter(sched)) { | |
669 | if (!perf_sched_restore_state(sched)) | |
670 | return false; | |
671 | } | |
672 | ||
1e2ad28f RR |
673 | return true; |
674 | } | |
675 | ||
676 | /* | |
677 | * Go through all unassigned events and find the next one to schedule. | |
678 | * Take events with the least weight first. Return true on success. | |
679 | */ | |
680 | static bool perf_sched_next_event(struct perf_sched *sched) | |
681 | { | |
682 | struct event_constraint *c; | |
683 | ||
684 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
685 | return false; | |
686 | ||
687 | do { | |
688 | /* next event */ | |
689 | sched->state.event++; | |
690 | if (sched->state.event >= sched->max_events) { | |
691 | /* next weight */ | |
692 | sched->state.event = 0; | |
693 | sched->state.weight++; | |
694 | if (sched->state.weight > sched->max_weight) | |
695 | return false; | |
696 | } | |
43b45780 | 697 | c = sched->events[sched->state.event]->hw.constraint; |
1e2ad28f RR |
698 | } while (c->weight != sched->state.weight); |
699 | ||
700 | sched->state.counter = 0; /* start with first counter */ | |
701 | ||
702 | return true; | |
703 | } | |
704 | ||
705 | /* | |
706 | * Assign a counter for each event. | |
707 | */ | |
43b45780 | 708 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 709 | int wmin, int wmax, int *assign) |
1e2ad28f RR |
710 | { |
711 | struct perf_sched sched; | |
712 | ||
43b45780 | 713 | perf_sched_init(&sched, events, n, wmin, wmax); |
1e2ad28f RR |
714 | |
715 | do { | |
716 | if (!perf_sched_find_counter(&sched)) | |
717 | break; /* failed */ | |
718 | if (assign) | |
719 | assign[sched.state.event] = sched.state.counter; | |
720 | } while (perf_sched_next_event(&sched)); | |
721 | ||
722 | return sched.state.unassigned; | |
723 | } | |
724 | ||
de0428a7 | 725 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 726 | { |
43b45780 | 727 | struct event_constraint *c; |
1da53e02 | 728 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 729 | struct perf_event *e; |
1e2ad28f | 730 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
731 | struct hw_perf_event *hwc; |
732 | ||
733 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
734 | ||
1e2ad28f | 735 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
43b45780 | 736 | hwc = &cpuc->event_list[i]->hw; |
b622d644 | 737 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
43b45780 AH |
738 | hwc->constraint = c; |
739 | ||
1e2ad28f RR |
740 | wmin = min(wmin, c->weight); |
741 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
742 | } |
743 | ||
8113070d SE |
744 | /* |
745 | * fastpath, try to reuse previous register | |
746 | */ | |
c933c1a6 | 747 | for (i = 0; i < n; i++) { |
8113070d | 748 | hwc = &cpuc->event_list[i]->hw; |
43b45780 | 749 | c = hwc->constraint; |
8113070d SE |
750 | |
751 | /* never assigned */ | |
752 | if (hwc->idx == -1) | |
753 | break; | |
754 | ||
755 | /* constraint still honored */ | |
63b14649 | 756 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
757 | break; |
758 | ||
759 | /* not already used */ | |
760 | if (test_bit(hwc->idx, used_mask)) | |
761 | break; | |
762 | ||
34538ee7 | 763 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
764 | if (assign) |
765 | assign[i] = hwc->idx; | |
766 | } | |
8113070d | 767 | |
1e2ad28f RR |
768 | /* slow path */ |
769 | if (i != n) | |
43b45780 AH |
770 | num = perf_assign_events(cpuc->event_list, n, wmin, |
771 | wmax, assign); | |
8113070d | 772 | |
2f7f73a5 SE |
773 | /* |
774 | * Mark the event as committed, so we do not put_constraint() | |
775 | * in case new events are added and fail scheduling. | |
776 | */ | |
777 | if (!num && assign) { | |
778 | for (i = 0; i < n; i++) { | |
779 | e = cpuc->event_list[i]; | |
780 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
781 | } | |
782 | } | |
1da53e02 SE |
783 | /* |
784 | * scheduling failed or is just a simulation, | |
785 | * free resources if necessary | |
786 | */ | |
787 | if (!assign || num) { | |
788 | for (i = 0; i < n; i++) { | |
2f7f73a5 SE |
789 | e = cpuc->event_list[i]; |
790 | /* | |
791 | * do not put_constraint() on comitted events, | |
792 | * because they are good to go | |
793 | */ | |
794 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
795 | continue; | |
796 | ||
1da53e02 | 797 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 798 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
799 | } |
800 | } | |
aa2bc1ad | 801 | return num ? -EINVAL : 0; |
1da53e02 SE |
802 | } |
803 | ||
804 | /* | |
805 | * dogrp: true if must collect siblings events (group) | |
806 | * returns total number of events and error code | |
807 | */ | |
808 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
809 | { | |
810 | struct perf_event *event; | |
811 | int n, max_count; | |
812 | ||
948b1bb8 | 813 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
814 | |
815 | /* current number of events already accepted */ | |
816 | n = cpuc->n_events; | |
817 | ||
818 | if (is_x86_event(leader)) { | |
819 | if (n >= max_count) | |
aa2bc1ad | 820 | return -EINVAL; |
1da53e02 SE |
821 | cpuc->event_list[n] = leader; |
822 | n++; | |
823 | } | |
824 | if (!dogrp) | |
825 | return n; | |
826 | ||
827 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
828 | if (!is_x86_event(event) || | |
8113070d | 829 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
830 | continue; |
831 | ||
832 | if (n >= max_count) | |
aa2bc1ad | 833 | return -EINVAL; |
1da53e02 SE |
834 | |
835 | cpuc->event_list[n] = event; | |
836 | n++; | |
837 | } | |
838 | return n; | |
839 | } | |
840 | ||
1da53e02 | 841 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 842 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 843 | { |
447a194b SE |
844 | struct hw_perf_event *hwc = &event->hw; |
845 | ||
846 | hwc->idx = cpuc->assign[i]; | |
847 | hwc->last_cpu = smp_processor_id(); | |
848 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 849 | |
15c7ad51 | 850 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
851 | hwc->config_base = 0; |
852 | hwc->event_base = 0; | |
15c7ad51 | 853 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 854 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
855 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
856 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 857 | } else { |
73d6e522 RR |
858 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
859 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 860 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
861 | } |
862 | } | |
863 | ||
447a194b SE |
864 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
865 | struct cpu_hw_events *cpuc, | |
866 | int i) | |
867 | { | |
868 | return hwc->idx == cpuc->assign[i] && | |
869 | hwc->last_cpu == smp_processor_id() && | |
870 | hwc->last_tag == cpuc->tags[i]; | |
871 | } | |
872 | ||
a4eaf7f1 | 873 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 874 | |
a4eaf7f1 | 875 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 876 | { |
1da53e02 SE |
877 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
878 | struct perf_event *event; | |
879 | struct hw_perf_event *hwc; | |
11164cd4 | 880 | int i, added = cpuc->n_added; |
1da53e02 | 881 | |
85cf9dba | 882 | if (!x86_pmu_initialized()) |
2b9ff0db | 883 | return; |
1a6e21f7 PZ |
884 | |
885 | if (cpuc->enabled) | |
886 | return; | |
887 | ||
1da53e02 | 888 | if (cpuc->n_added) { |
19925ce7 | 889 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
890 | /* |
891 | * apply assignment obtained either from | |
892 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
893 | * | |
894 | * step1: save events moving to new counters | |
895 | * step2: reprogram moved events into new counters | |
896 | */ | |
19925ce7 | 897 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
898 | event = cpuc->event_list[i]; |
899 | hwc = &event->hw; | |
900 | ||
447a194b SE |
901 | /* |
902 | * we can avoid reprogramming counter if: | |
903 | * - assigned same counter as last time | |
904 | * - running on same CPU as last time | |
905 | * - no other event has used the counter since | |
906 | */ | |
907 | if (hwc->idx == -1 || | |
908 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
909 | continue; |
910 | ||
a4eaf7f1 PZ |
911 | /* |
912 | * Ensure we don't accidentally enable a stopped | |
913 | * counter simply because we rescheduled. | |
914 | */ | |
915 | if (hwc->state & PERF_HES_STOPPED) | |
916 | hwc->state |= PERF_HES_ARCH; | |
917 | ||
918 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
919 | } |
920 | ||
921 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
922 | event = cpuc->event_list[i]; |
923 | hwc = &event->hw; | |
924 | ||
45e16a68 | 925 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 926 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
927 | else if (i < n_running) |
928 | continue; | |
1da53e02 | 929 | |
a4eaf7f1 PZ |
930 | if (hwc->state & PERF_HES_ARCH) |
931 | continue; | |
932 | ||
933 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
934 | } |
935 | cpuc->n_added = 0; | |
936 | perf_events_lapic_init(); | |
937 | } | |
1a6e21f7 PZ |
938 | |
939 | cpuc->enabled = 1; | |
940 | barrier(); | |
941 | ||
11164cd4 | 942 | x86_pmu.enable_all(added); |
ee06094f | 943 | } |
ee06094f | 944 | |
245b2e70 | 945 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 946 | |
ee06094f IM |
947 | /* |
948 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 949 | * To be called with the event disabled in hw: |
ee06094f | 950 | */ |
de0428a7 | 951 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 952 | { |
07088edb | 953 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 954 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 955 | s64 period = hwc->sample_period; |
7645a24c | 956 | int ret = 0, idx = hwc->idx; |
ee06094f | 957 | |
15c7ad51 | 958 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
959 | return 0; |
960 | ||
ee06094f | 961 | /* |
af901ca1 | 962 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
963 | */ |
964 | if (unlikely(left <= -period)) { | |
965 | left = period; | |
e7850595 | 966 | local64_set(&hwc->period_left, left); |
9e350de3 | 967 | hwc->last_period = period; |
e4abb5d4 | 968 | ret = 1; |
ee06094f IM |
969 | } |
970 | ||
971 | if (unlikely(left <= 0)) { | |
972 | left += period; | |
e7850595 | 973 | local64_set(&hwc->period_left, left); |
9e350de3 | 974 | hwc->last_period = period; |
e4abb5d4 | 975 | ret = 1; |
ee06094f | 976 | } |
1c80f4b5 | 977 | /* |
dfc65094 | 978 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
979 | */ |
980 | if (unlikely(left < 2)) | |
981 | left = 2; | |
241771ef | 982 | |
e4abb5d4 PZ |
983 | if (left > x86_pmu.max_period) |
984 | left = x86_pmu.max_period; | |
985 | ||
245b2e70 | 986 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
987 | |
988 | /* | |
cdd6c482 | 989 | * The hw event starts counting from this event offset, |
ee06094f IM |
990 | * mark it to be able to extra future deltas: |
991 | */ | |
e7850595 | 992 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 993 | |
73d6e522 | 994 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
995 | |
996 | /* | |
997 | * Due to erratum on certan cpu we need | |
998 | * a second write to be sure the register | |
999 | * is updated properly | |
1000 | */ | |
1001 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1002 | wrmsrl(hwc->event_base, |
948b1bb8 | 1003 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1004 | } |
e4abb5d4 | 1005 | |
cdd6c482 | 1006 | perf_event_update_userpage(event); |
194002b2 | 1007 | |
e4abb5d4 | 1008 | return ret; |
2f18d1e8 IM |
1009 | } |
1010 | ||
de0428a7 | 1011 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1012 | { |
0a3aee0d | 1013 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1014 | __x86_pmu_enable_event(&event->hw, |
1015 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1016 | } |
1017 | ||
b690081d | 1018 | /* |
a4eaf7f1 | 1019 | * Add a single event to the PMU. |
1da53e02 SE |
1020 | * |
1021 | * The event is added to the group of enabled events | |
1022 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1023 | */ |
a4eaf7f1 | 1024 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1025 | { |
1026 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1027 | struct hw_perf_event *hwc; |
1028 | int assign[X86_PMC_IDX_MAX]; | |
1029 | int n, n0, ret; | |
fe9081cc | 1030 | |
1da53e02 | 1031 | hwc = &event->hw; |
fe9081cc | 1032 | |
33696fc0 | 1033 | perf_pmu_disable(event->pmu); |
1da53e02 | 1034 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1035 | ret = n = collect_events(cpuc, event, false); |
1036 | if (ret < 0) | |
1037 | goto out; | |
53b441a5 | 1038 | |
a4eaf7f1 PZ |
1039 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1040 | if (!(flags & PERF_EF_START)) | |
1041 | hwc->state |= PERF_HES_ARCH; | |
1042 | ||
4d1c52b0 LM |
1043 | /* |
1044 | * If group events scheduling transaction was started, | |
0d2eb44f | 1045 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1046 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1047 | */ |
8d2cacbb | 1048 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1049 | goto done_collect; |
4d1c52b0 | 1050 | |
a072738e | 1051 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1052 | if (ret) |
24cd7f54 | 1053 | goto out; |
1da53e02 SE |
1054 | /* |
1055 | * copy new assignment, now we know it is possible | |
1056 | * will be used by hw_perf_enable() | |
1057 | */ | |
1058 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1059 | |
24cd7f54 | 1060 | done_collect: |
1da53e02 | 1061 | cpuc->n_events = n; |
356e1f2e | 1062 | cpuc->n_added += n - n0; |
90151c35 | 1063 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1064 | |
24cd7f54 PZ |
1065 | ret = 0; |
1066 | out: | |
33696fc0 | 1067 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1068 | return ret; |
241771ef IM |
1069 | } |
1070 | ||
a4eaf7f1 | 1071 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1072 | { |
c08053e6 PZ |
1073 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1074 | int idx = event->hw.idx; | |
1075 | ||
a4eaf7f1 PZ |
1076 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1077 | return; | |
1078 | ||
1079 | if (WARN_ON_ONCE(idx == -1)) | |
1080 | return; | |
1081 | ||
1082 | if (flags & PERF_EF_RELOAD) { | |
1083 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1084 | x86_perf_event_set_period(event); | |
1085 | } | |
1086 | ||
1087 | event->hw.state = 0; | |
d76a0812 | 1088 | |
c08053e6 PZ |
1089 | cpuc->events[idx] = event; |
1090 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1091 | __set_bit(idx, cpuc->running); |
aff3d91a | 1092 | x86_pmu.enable(event); |
c08053e6 | 1093 | perf_event_update_userpage(event); |
a78ac325 PZ |
1094 | } |
1095 | ||
cdd6c482 | 1096 | void perf_event_print_debug(void) |
241771ef | 1097 | { |
2f18d1e8 | 1098 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1099 | u64 pebs; |
cdd6c482 | 1100 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1101 | unsigned long flags; |
1e125676 IM |
1102 | int cpu, idx; |
1103 | ||
948b1bb8 | 1104 | if (!x86_pmu.num_counters) |
1e125676 | 1105 | return; |
241771ef | 1106 | |
5bb9efe3 | 1107 | local_irq_save(flags); |
241771ef IM |
1108 | |
1109 | cpu = smp_processor_id(); | |
cdd6c482 | 1110 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1111 | |
faa28ae0 | 1112 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1113 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1114 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1115 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1116 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1117 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1118 | |
1119 | pr_info("\n"); | |
1120 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1121 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1122 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1123 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1124 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1125 | } |
7645a24c | 1126 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1127 | |
948b1bb8 | 1128 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1129 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1130 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1131 | |
245b2e70 | 1132 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1133 | |
a1ef58f4 | 1134 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1135 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1136 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1137 | cpu, idx, pmc_count); |
a1ef58f4 | 1138 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1139 | cpu, idx, prev_left); |
241771ef | 1140 | } |
948b1bb8 | 1141 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1142 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1143 | ||
a1ef58f4 | 1144 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1145 | cpu, idx, pmc_count); |
1146 | } | |
5bb9efe3 | 1147 | local_irq_restore(flags); |
241771ef IM |
1148 | } |
1149 | ||
de0428a7 | 1150 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1151 | { |
d76a0812 | 1152 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1153 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1154 | |
a4eaf7f1 PZ |
1155 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1156 | x86_pmu.disable(event); | |
1157 | cpuc->events[hwc->idx] = NULL; | |
1158 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1159 | hwc->state |= PERF_HES_STOPPED; | |
1160 | } | |
30dd568c | 1161 | |
a4eaf7f1 PZ |
1162 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1163 | /* | |
1164 | * Drain the remaining delta count out of a event | |
1165 | * that we are disabling: | |
1166 | */ | |
1167 | x86_perf_event_update(event); | |
1168 | hwc->state |= PERF_HES_UPTODATE; | |
1169 | } | |
2e841873 PZ |
1170 | } |
1171 | ||
a4eaf7f1 | 1172 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1173 | { |
1174 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1175 | int i; | |
1176 | ||
2f7f73a5 SE |
1177 | /* |
1178 | * event is descheduled | |
1179 | */ | |
1180 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1181 | ||
90151c35 SE |
1182 | /* |
1183 | * If we're called during a txn, we don't need to do anything. | |
1184 | * The events never got scheduled and ->cancel_txn will truncate | |
1185 | * the event_list. | |
1186 | */ | |
8d2cacbb | 1187 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1188 | return; |
1189 | ||
a4eaf7f1 | 1190 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1191 | |
1da53e02 SE |
1192 | for (i = 0; i < cpuc->n_events; i++) { |
1193 | if (event == cpuc->event_list[i]) { | |
1194 | ||
1195 | if (x86_pmu.put_event_constraints) | |
1196 | x86_pmu.put_event_constraints(cpuc, event); | |
1197 | ||
1198 | while (++i < cpuc->n_events) | |
1199 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1200 | ||
1201 | --cpuc->n_events; | |
6c9687ab | 1202 | break; |
1da53e02 SE |
1203 | } |
1204 | } | |
cdd6c482 | 1205 | perf_event_update_userpage(event); |
241771ef IM |
1206 | } |
1207 | ||
de0428a7 | 1208 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1209 | { |
df1a132b | 1210 | struct perf_sample_data data; |
cdd6c482 IM |
1211 | struct cpu_hw_events *cpuc; |
1212 | struct perf_event *event; | |
11d1578f | 1213 | int idx, handled = 0; |
9029a5e3 IM |
1214 | u64 val; |
1215 | ||
cdd6c482 | 1216 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1217 | |
2bce5dac DZ |
1218 | /* |
1219 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1220 | * inside the nmi handler. As a result, the unmasking was pushed | |
1221 | * into all the nmi handlers. | |
1222 | * | |
1223 | * This generic handler doesn't seem to have any issues where the | |
1224 | * unmasking occurs so it was left at the top. | |
1225 | */ | |
1226 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1227 | ||
948b1bb8 | 1228 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1229 | if (!test_bit(idx, cpuc->active_mask)) { |
1230 | /* | |
1231 | * Though we deactivated the counter some cpus | |
1232 | * might still deliver spurious interrupts still | |
1233 | * in flight. Catch them: | |
1234 | */ | |
1235 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1236 | handled++; | |
a29aa8a7 | 1237 | continue; |
63e6be6d | 1238 | } |
962bf7a6 | 1239 | |
cdd6c482 | 1240 | event = cpuc->events[idx]; |
a4016a79 | 1241 | |
cc2ad4ba | 1242 | val = x86_perf_event_update(event); |
948b1bb8 | 1243 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1244 | continue; |
962bf7a6 | 1245 | |
9e350de3 | 1246 | /* |
cdd6c482 | 1247 | * event overflow |
9e350de3 | 1248 | */ |
4177c42a | 1249 | handled++; |
fd0d000b | 1250 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1251 | |
07088edb | 1252 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1253 | continue; |
1254 | ||
a8b0ca17 | 1255 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1256 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1257 | } |
962bf7a6 | 1258 | |
9e350de3 PZ |
1259 | if (handled) |
1260 | inc_irq_stat(apic_perf_irqs); | |
1261 | ||
a29aa8a7 RR |
1262 | return handled; |
1263 | } | |
39d81eab | 1264 | |
cdd6c482 | 1265 | void perf_events_lapic_init(void) |
241771ef | 1266 | { |
04da8a43 | 1267 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1268 | return; |
85cf9dba | 1269 | |
241771ef | 1270 | /* |
c323d95f | 1271 | * Always use NMI for PMU |
241771ef | 1272 | */ |
c323d95f | 1273 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1274 | } |
1275 | ||
1276 | static int __kprobes | |
9c48f1c6 | 1277 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1278 | { |
14c63f17 DH |
1279 | u64 start_clock; |
1280 | u64 finish_clock; | |
e8a923cc | 1281 | int ret; |
14c63f17 | 1282 | |
cdd6c482 | 1283 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1284 | return NMI_DONE; |
4177c42a | 1285 | |
e8a923cc | 1286 | start_clock = sched_clock(); |
14c63f17 | 1287 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1288 | finish_clock = sched_clock(); |
14c63f17 DH |
1289 | |
1290 | perf_sample_event_took(finish_clock - start_clock); | |
1291 | ||
1292 | return ret; | |
241771ef IM |
1293 | } |
1294 | ||
de0428a7 KW |
1295 | struct event_constraint emptyconstraint; |
1296 | struct event_constraint unconstrained; | |
f87ad35d | 1297 | |
148f9bb8 | 1298 | static int |
3f6da390 PZ |
1299 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1300 | { | |
1301 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1302 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1303 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1304 | |
1305 | switch (action & ~CPU_TASKS_FROZEN) { | |
1306 | case CPU_UP_PREPARE: | |
7fdba1ca | 1307 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1308 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1309 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1310 | break; |
1311 | ||
1312 | case CPU_STARTING: | |
0c9d42ed PZ |
1313 | if (x86_pmu.attr_rdpmc) |
1314 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1315 | if (x86_pmu.cpu_starting) |
1316 | x86_pmu.cpu_starting(cpu); | |
1317 | break; | |
1318 | ||
7fdba1ca PZ |
1319 | case CPU_ONLINE: |
1320 | kfree(cpuc->kfree_on_online); | |
1321 | break; | |
1322 | ||
3f6da390 PZ |
1323 | case CPU_DYING: |
1324 | if (x86_pmu.cpu_dying) | |
1325 | x86_pmu.cpu_dying(cpu); | |
1326 | break; | |
1327 | ||
b38b24ea | 1328 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1329 | case CPU_DEAD: |
1330 | if (x86_pmu.cpu_dead) | |
1331 | x86_pmu.cpu_dead(cpu); | |
1332 | break; | |
1333 | ||
1334 | default: | |
1335 | break; | |
1336 | } | |
1337 | ||
b38b24ea | 1338 | return ret; |
3f6da390 PZ |
1339 | } |
1340 | ||
12558038 CG |
1341 | static void __init pmu_check_apic(void) |
1342 | { | |
1343 | if (cpu_has_apic) | |
1344 | return; | |
1345 | ||
1346 | x86_pmu.apic = 0; | |
1347 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1348 | pr_info("no hardware sampling interrupt available.\n"); | |
1349 | } | |
1350 | ||
641cc938 JO |
1351 | static struct attribute_group x86_pmu_format_group = { |
1352 | .name = "format", | |
1353 | .attrs = NULL, | |
1354 | }; | |
1355 | ||
8300daa2 JO |
1356 | /* |
1357 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1358 | * out of events_attr attributes. | |
1359 | */ | |
1360 | static void __init filter_events(struct attribute **attrs) | |
1361 | { | |
3a54aaa0 SE |
1362 | struct device_attribute *d; |
1363 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1364 | int i, j; |
1365 | ||
1366 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1367 | d = (struct device_attribute *)attrs[i]; |
1368 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1369 | /* str trumps id */ | |
1370 | if (pmu_attr->event_str) | |
1371 | continue; | |
8300daa2 JO |
1372 | if (x86_pmu.event_map(i)) |
1373 | continue; | |
1374 | ||
1375 | for (j = i; attrs[j]; j++) | |
1376 | attrs[j] = attrs[j + 1]; | |
1377 | ||
1378 | /* Check the shifted attr. */ | |
1379 | i--; | |
1380 | } | |
1381 | } | |
1382 | ||
1a6461b1 AK |
1383 | /* Merge two pointer arrays */ |
1384 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1385 | { | |
1386 | struct attribute **new; | |
1387 | int j, i; | |
1388 | ||
1389 | for (j = 0; a[j]; j++) | |
1390 | ; | |
1391 | for (i = 0; b[i]; i++) | |
1392 | j++; | |
1393 | j++; | |
1394 | ||
1395 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1396 | if (!new) | |
1397 | return NULL; | |
1398 | ||
1399 | j = 0; | |
1400 | for (i = 0; a[i]; i++) | |
1401 | new[j++] = a[i]; | |
1402 | for (i = 0; b[i]; i++) | |
1403 | new[j++] = b[i]; | |
1404 | new[j] = NULL; | |
1405 | ||
1406 | return new; | |
1407 | } | |
1408 | ||
f20093ee | 1409 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1410 | char *page) |
1411 | { | |
1412 | struct perf_pmu_events_attr *pmu_attr = \ | |
1413 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1414 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1415 | |
3a54aaa0 SE |
1416 | /* string trumps id */ |
1417 | if (pmu_attr->event_str) | |
1418 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1419 | |
3a54aaa0 SE |
1420 | return x86_pmu.events_sysfs_show(page, config); |
1421 | } | |
a4747393 JO |
1422 | |
1423 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1424 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1425 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1426 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1427 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1428 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1429 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1430 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1431 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1432 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1433 | ||
1434 | static struct attribute *empty_attrs; | |
1435 | ||
95d18aa2 | 1436 | static struct attribute *events_attr[] = { |
a4747393 JO |
1437 | EVENT_PTR(CPU_CYCLES), |
1438 | EVENT_PTR(INSTRUCTIONS), | |
1439 | EVENT_PTR(CACHE_REFERENCES), | |
1440 | EVENT_PTR(CACHE_MISSES), | |
1441 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1442 | EVENT_PTR(BRANCH_MISSES), | |
1443 | EVENT_PTR(BUS_CYCLES), | |
1444 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1445 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1446 | EVENT_PTR(REF_CPU_CYCLES), | |
1447 | NULL, | |
1448 | }; | |
1449 | ||
1450 | static struct attribute_group x86_pmu_events_group = { | |
1451 | .name = "events", | |
1452 | .attrs = events_attr, | |
1453 | }; | |
1454 | ||
0bf79d44 | 1455 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1456 | { |
43c032fe JO |
1457 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1458 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1459 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1460 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1461 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1462 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1463 | ssize_t ret; | |
1464 | ||
1465 | /* | |
1466 | * We have whole page size to spend and just little data | |
1467 | * to write, so we can safely use sprintf. | |
1468 | */ | |
1469 | ret = sprintf(page, "event=0x%02llx", event); | |
1470 | ||
1471 | if (umask) | |
1472 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1473 | ||
1474 | if (edge) | |
1475 | ret += sprintf(page + ret, ",edge"); | |
1476 | ||
1477 | if (pc) | |
1478 | ret += sprintf(page + ret, ",pc"); | |
1479 | ||
1480 | if (any) | |
1481 | ret += sprintf(page + ret, ",any"); | |
1482 | ||
1483 | if (inv) | |
1484 | ret += sprintf(page + ret, ",inv"); | |
1485 | ||
1486 | if (cmask) | |
1487 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1488 | ||
1489 | ret += sprintf(page + ret, "\n"); | |
1490 | ||
1491 | return ret; | |
1492 | } | |
1493 | ||
dda99116 | 1494 | static int __init init_hw_perf_events(void) |
b56a3802 | 1495 | { |
c1d6f42f | 1496 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1497 | int err; |
1498 | ||
cdd6c482 | 1499 | pr_info("Performance Events: "); |
1123e3ad | 1500 | |
b56a3802 JSR |
1501 | switch (boot_cpu_data.x86_vendor) { |
1502 | case X86_VENDOR_INTEL: | |
72eae04d | 1503 | err = intel_pmu_init(); |
b56a3802 | 1504 | break; |
f87ad35d | 1505 | case X86_VENDOR_AMD: |
72eae04d | 1506 | err = amd_pmu_init(); |
f87ad35d | 1507 | break; |
4138960a | 1508 | default: |
8a3da6c7 | 1509 | err = -ENOTSUPP; |
b56a3802 | 1510 | } |
1123e3ad | 1511 | if (err != 0) { |
cdd6c482 | 1512 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1513 | return 0; |
1123e3ad | 1514 | } |
b56a3802 | 1515 | |
12558038 CG |
1516 | pmu_check_apic(); |
1517 | ||
33c6d6a7 | 1518 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1519 | if (!check_hw_exists()) |
004417a6 | 1520 | return 0; |
33c6d6a7 | 1521 | |
1123e3ad | 1522 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1523 | |
c1d6f42f PZ |
1524 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1525 | quirk->func(); | |
3c44780b | 1526 | |
a1eac7ac RR |
1527 | if (!x86_pmu.intel_ctrl) |
1528 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1529 | |
cdd6c482 | 1530 | perf_events_lapic_init(); |
9c48f1c6 | 1531 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1532 | |
63b14649 | 1533 | unconstrained = (struct event_constraint) |
948b1bb8 | 1534 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1535 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1536 | |
0c9d42ed | 1537 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
641cc938 | 1538 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1539 | |
f20093ee SE |
1540 | if (x86_pmu.event_attrs) |
1541 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1542 | ||
a4747393 JO |
1543 | if (!x86_pmu.events_sysfs_show) |
1544 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1545 | else |
1546 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1547 | |
1a6461b1 AK |
1548 | if (x86_pmu.cpu_events) { |
1549 | struct attribute **tmp; | |
1550 | ||
1551 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1552 | if (!WARN_ON(!tmp)) | |
1553 | x86_pmu_events_group.attrs = tmp; | |
1554 | } | |
1555 | ||
57c0c15b | 1556 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1557 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1558 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1559 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1560 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1561 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1562 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1563 | |
2e80a82a | 1564 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1565 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1566 | |
1567 | return 0; | |
241771ef | 1568 | } |
004417a6 | 1569 | early_initcall(init_hw_perf_events); |
621a01ea | 1570 | |
cdd6c482 | 1571 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1572 | { |
cc2ad4ba | 1573 | x86_perf_event_update(event); |
ee06094f IM |
1574 | } |
1575 | ||
4d1c52b0 LM |
1576 | /* |
1577 | * Start group events scheduling transaction | |
1578 | * Set the flag to make pmu::enable() not perform the | |
1579 | * schedulability test, it will be performed at commit time | |
1580 | */ | |
51b0fe39 | 1581 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1582 | { |
33696fc0 | 1583 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1584 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1585 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1586 | } |
1587 | ||
1588 | /* | |
1589 | * Stop group events scheduling transaction | |
1590 | * Clear the flag and pmu::enable() will perform the | |
1591 | * schedulability test. | |
1592 | */ | |
51b0fe39 | 1593 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1594 | { |
0a3aee0d | 1595 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1596 | /* |
1597 | * Truncate the collected events. | |
1598 | */ | |
0a3aee0d TH |
1599 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1600 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1601 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1602 | } |
1603 | ||
1604 | /* | |
1605 | * Commit group events scheduling transaction | |
1606 | * Perform the group schedulability test as a whole | |
1607 | * Return 0 if success | |
1608 | */ | |
51b0fe39 | 1609 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1610 | { |
1611 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1612 | int assign[X86_PMC_IDX_MAX]; | |
1613 | int n, ret; | |
1614 | ||
1615 | n = cpuc->n_events; | |
1616 | ||
1617 | if (!x86_pmu_initialized()) | |
1618 | return -EAGAIN; | |
1619 | ||
1620 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1621 | if (ret) | |
1622 | return ret; | |
1623 | ||
1624 | /* | |
1625 | * copy new assignment, now we know it is possible | |
1626 | * will be used by hw_perf_enable() | |
1627 | */ | |
1628 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1629 | ||
8d2cacbb | 1630 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1631 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1632 | return 0; |
1633 | } | |
cd8a38d3 SE |
1634 | /* |
1635 | * a fake_cpuc is used to validate event groups. Due to | |
1636 | * the extra reg logic, we need to also allocate a fake | |
1637 | * per_core and per_cpu structure. Otherwise, group events | |
1638 | * using extra reg may conflict without the kernel being | |
1639 | * able to catch this when the last event gets added to | |
1640 | * the group. | |
1641 | */ | |
1642 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1643 | { | |
1644 | kfree(cpuc->shared_regs); | |
1645 | kfree(cpuc); | |
1646 | } | |
1647 | ||
1648 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1649 | { | |
1650 | struct cpu_hw_events *cpuc; | |
1651 | int cpu = raw_smp_processor_id(); | |
1652 | ||
1653 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1654 | if (!cpuc) | |
1655 | return ERR_PTR(-ENOMEM); | |
1656 | ||
1657 | /* only needed, if we have extra_regs */ | |
1658 | if (x86_pmu.extra_regs) { | |
1659 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1660 | if (!cpuc->shared_regs) | |
1661 | goto error; | |
1662 | } | |
b430f7c4 | 1663 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1664 | return cpuc; |
1665 | error: | |
1666 | free_fake_cpuc(cpuc); | |
1667 | return ERR_PTR(-ENOMEM); | |
1668 | } | |
4d1c52b0 | 1669 | |
ca037701 PZ |
1670 | /* |
1671 | * validate that we can schedule this event | |
1672 | */ | |
1673 | static int validate_event(struct perf_event *event) | |
1674 | { | |
1675 | struct cpu_hw_events *fake_cpuc; | |
1676 | struct event_constraint *c; | |
1677 | int ret = 0; | |
1678 | ||
cd8a38d3 SE |
1679 | fake_cpuc = allocate_fake_cpuc(); |
1680 | if (IS_ERR(fake_cpuc)) | |
1681 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1682 | |
1683 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1684 | ||
1685 | if (!c || !c->weight) | |
aa2bc1ad | 1686 | ret = -EINVAL; |
ca037701 PZ |
1687 | |
1688 | if (x86_pmu.put_event_constraints) | |
1689 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1690 | ||
cd8a38d3 | 1691 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1692 | |
1693 | return ret; | |
1694 | } | |
1695 | ||
1da53e02 SE |
1696 | /* |
1697 | * validate a single event group | |
1698 | * | |
1699 | * validation include: | |
184f412c IM |
1700 | * - check events are compatible which each other |
1701 | * - events do not compete for the same counter | |
1702 | * - number of events <= number of counters | |
1da53e02 SE |
1703 | * |
1704 | * validation ensures the group can be loaded onto the | |
1705 | * PMU if it was the only group available. | |
1706 | */ | |
fe9081cc PZ |
1707 | static int validate_group(struct perf_event *event) |
1708 | { | |
1da53e02 | 1709 | struct perf_event *leader = event->group_leader; |
502568d5 | 1710 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1711 | int ret = -EINVAL, n; |
fe9081cc | 1712 | |
cd8a38d3 SE |
1713 | fake_cpuc = allocate_fake_cpuc(); |
1714 | if (IS_ERR(fake_cpuc)) | |
1715 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1716 | /* |
1717 | * the event is not yet connected with its | |
1718 | * siblings therefore we must first collect | |
1719 | * existing siblings, then add the new event | |
1720 | * before we can simulate the scheduling | |
1721 | */ | |
502568d5 | 1722 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1723 | if (n < 0) |
cd8a38d3 | 1724 | goto out; |
fe9081cc | 1725 | |
502568d5 PZ |
1726 | fake_cpuc->n_events = n; |
1727 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1728 | if (n < 0) |
cd8a38d3 | 1729 | goto out; |
fe9081cc | 1730 | |
502568d5 | 1731 | fake_cpuc->n_events = n; |
1da53e02 | 1732 | |
a072738e | 1733 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1734 | |
502568d5 | 1735 | out: |
cd8a38d3 | 1736 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1737 | return ret; |
fe9081cc PZ |
1738 | } |
1739 | ||
dda99116 | 1740 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1741 | { |
51b0fe39 | 1742 | struct pmu *tmp; |
621a01ea IM |
1743 | int err; |
1744 | ||
b0a873eb PZ |
1745 | switch (event->attr.type) { |
1746 | case PERF_TYPE_RAW: | |
1747 | case PERF_TYPE_HARDWARE: | |
1748 | case PERF_TYPE_HW_CACHE: | |
1749 | break; | |
1750 | ||
1751 | default: | |
1752 | return -ENOENT; | |
1753 | } | |
1754 | ||
1755 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1756 | if (!err) { |
8113070d SE |
1757 | /* |
1758 | * we temporarily connect event to its pmu | |
1759 | * such that validate_group() can classify | |
1760 | * it as an x86 event using is_x86_event() | |
1761 | */ | |
1762 | tmp = event->pmu; | |
1763 | event->pmu = &pmu; | |
1764 | ||
fe9081cc PZ |
1765 | if (event->group_leader != event) |
1766 | err = validate_group(event); | |
ca037701 PZ |
1767 | else |
1768 | err = validate_event(event); | |
8113070d SE |
1769 | |
1770 | event->pmu = tmp; | |
fe9081cc | 1771 | } |
a1792cda | 1772 | if (err) { |
cdd6c482 IM |
1773 | if (event->destroy) |
1774 | event->destroy(event); | |
a1792cda | 1775 | } |
621a01ea | 1776 | |
b0a873eb | 1777 | return err; |
621a01ea | 1778 | } |
d7d59fb3 | 1779 | |
fe4a3308 PZ |
1780 | static int x86_pmu_event_idx(struct perf_event *event) |
1781 | { | |
1782 | int idx = event->hw.idx; | |
1783 | ||
c7206205 PZ |
1784 | if (!x86_pmu.attr_rdpmc) |
1785 | return 0; | |
1786 | ||
15c7ad51 RR |
1787 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1788 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1789 | idx |= 1 << 30; |
1790 | } | |
1791 | ||
1792 | return idx + 1; | |
1793 | } | |
1794 | ||
0c9d42ed PZ |
1795 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1796 | struct device_attribute *attr, | |
1797 | char *buf) | |
1798 | { | |
1799 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1800 | } | |
1801 | ||
1802 | static void change_rdpmc(void *info) | |
1803 | { | |
1804 | bool enable = !!(unsigned long)info; | |
1805 | ||
1806 | if (enable) | |
1807 | set_in_cr4(X86_CR4_PCE); | |
1808 | else | |
1809 | clear_in_cr4(X86_CR4_PCE); | |
1810 | } | |
1811 | ||
1812 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1813 | struct device_attribute *attr, | |
1814 | const char *buf, size_t count) | |
1815 | { | |
e2b297fc SK |
1816 | unsigned long val; |
1817 | ssize_t ret; | |
1818 | ||
1819 | ret = kstrtoul(buf, 0, &val); | |
1820 | if (ret) | |
1821 | return ret; | |
0c9d42ed PZ |
1822 | |
1823 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1824 | x86_pmu.attr_rdpmc = !!val; | |
1825 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1826 | } | |
1827 | ||
1828 | return count; | |
1829 | } | |
1830 | ||
1831 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1832 | ||
1833 | static struct attribute *x86_pmu_attrs[] = { | |
1834 | &dev_attr_rdpmc.attr, | |
1835 | NULL, | |
1836 | }; | |
1837 | ||
1838 | static struct attribute_group x86_pmu_attr_group = { | |
1839 | .attrs = x86_pmu_attrs, | |
1840 | }; | |
1841 | ||
1842 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1843 | &x86_pmu_attr_group, | |
641cc938 | 1844 | &x86_pmu_format_group, |
a4747393 | 1845 | &x86_pmu_events_group, |
0c9d42ed PZ |
1846 | NULL, |
1847 | }; | |
1848 | ||
d010b332 SE |
1849 | static void x86_pmu_flush_branch_stack(void) |
1850 | { | |
1851 | if (x86_pmu.flush_branch_stack) | |
1852 | x86_pmu.flush_branch_stack(); | |
1853 | } | |
1854 | ||
c93dc84c PZ |
1855 | void perf_check_microcode(void) |
1856 | { | |
1857 | if (x86_pmu.check_microcode) | |
1858 | x86_pmu.check_microcode(); | |
1859 | } | |
1860 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1861 | ||
b0a873eb | 1862 | static struct pmu pmu = { |
d010b332 SE |
1863 | .pmu_enable = x86_pmu_enable, |
1864 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1865 | |
c93dc84c | 1866 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1867 | |
c93dc84c | 1868 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1869 | |
d010b332 SE |
1870 | .add = x86_pmu_add, |
1871 | .del = x86_pmu_del, | |
1872 | .start = x86_pmu_start, | |
1873 | .stop = x86_pmu_stop, | |
1874 | .read = x86_pmu_read, | |
a4eaf7f1 | 1875 | |
c93dc84c PZ |
1876 | .start_txn = x86_pmu_start_txn, |
1877 | .cancel_txn = x86_pmu_cancel_txn, | |
1878 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1879 | |
c93dc84c | 1880 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1881 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1882 | }; |
1883 | ||
c7206205 | 1884 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1885 | { |
fa731587 PZ |
1886 | userpg->cap_user_time = 0; |
1887 | userpg->cap_user_time_zero = 0; | |
1888 | userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc; | |
c7206205 PZ |
1889 | userpg->pmc_width = x86_pmu.cntval_bits; |
1890 | ||
d8b11a0c | 1891 | if (!sched_clock_stable) |
e3f3541c PZ |
1892 | return; |
1893 | ||
fa731587 | 1894 | userpg->cap_user_time = 1; |
e3f3541c PZ |
1895 | userpg->time_mult = this_cpu_read(cyc2ns); |
1896 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1897 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
c73deb6a | 1898 | |
d8b11a0c PZ |
1899 | userpg->cap_user_time_zero = 1; |
1900 | userpg->time_zero = this_cpu_read(cyc2ns_offset); | |
e3f3541c PZ |
1901 | } |
1902 | ||
d7d59fb3 PZ |
1903 | /* |
1904 | * callchain support | |
1905 | */ | |
1906 | ||
d7d59fb3 PZ |
1907 | static int backtrace_stack(void *data, char *name) |
1908 | { | |
038e836e | 1909 | return 0; |
d7d59fb3 PZ |
1910 | } |
1911 | ||
1912 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1913 | { | |
1914 | struct perf_callchain_entry *entry = data; | |
1915 | ||
70791ce9 | 1916 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1917 | } |
1918 | ||
1919 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1920 | .stack = backtrace_stack, |
1921 | .address = backtrace_address, | |
06d65bda | 1922 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1923 | }; |
1924 | ||
56962b44 FW |
1925 | void |
1926 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1927 | { |
927c7a9e FW |
1928 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1929 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1930 | return; |
927c7a9e FW |
1931 | } |
1932 | ||
70791ce9 | 1933 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1934 | |
e8e999cf | 1935 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1936 | } |
1937 | ||
bc6ca7b3 AS |
1938 | static inline int |
1939 | valid_user_frame(const void __user *fp, unsigned long size) | |
1940 | { | |
1941 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1942 | } | |
1943 | ||
d07bdfd3 PZ |
1944 | static unsigned long get_segment_base(unsigned int segment) |
1945 | { | |
1946 | struct desc_struct *desc; | |
1947 | int idx = segment >> 3; | |
1948 | ||
1949 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
1950 | if (idx > LDT_ENTRIES) | |
1951 | return 0; | |
1952 | ||
1953 | if (idx > current->active_mm->context.size) | |
1954 | return 0; | |
1955 | ||
1956 | desc = current->active_mm->context.ldt; | |
1957 | } else { | |
1958 | if (idx > GDT_ENTRIES) | |
1959 | return 0; | |
1960 | ||
1961 | desc = __this_cpu_ptr(&gdt_page.gdt[0]); | |
1962 | } | |
1963 | ||
1964 | return get_desc_base(desc + idx); | |
1965 | } | |
1966 | ||
257ef9d2 | 1967 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
1968 | |
1969 | #include <asm/compat.h> | |
1970 | ||
257ef9d2 TE |
1971 | static inline int |
1972 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1973 | { |
257ef9d2 | 1974 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 1975 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
1976 | struct stack_frame_ia32 frame; |
1977 | const void __user *fp; | |
74193ef0 | 1978 | |
257ef9d2 TE |
1979 | if (!test_thread_flag(TIF_IA32)) |
1980 | return 0; | |
1981 | ||
d07bdfd3 PZ |
1982 | cs_base = get_segment_base(regs->cs); |
1983 | ss_base = get_segment_base(regs->ss); | |
1984 | ||
1985 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
1986 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
1987 | unsigned long bytes; | |
1988 | frame.next_frame = 0; | |
1989 | frame.return_address = 0; | |
1990 | ||
1991 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1992 | if (bytes != sizeof(frame)) | |
1993 | break; | |
74193ef0 | 1994 | |
bc6ca7b3 AS |
1995 | if (!valid_user_frame(fp, sizeof(frame))) |
1996 | break; | |
1997 | ||
d07bdfd3 PZ |
1998 | perf_callchain_store(entry, cs_base + frame.return_address); |
1999 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2000 | } |
2001 | return 1; | |
d7d59fb3 | 2002 | } |
257ef9d2 TE |
2003 | #else |
2004 | static inline int | |
2005 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2006 | { | |
2007 | return 0; | |
2008 | } | |
2009 | #endif | |
d7d59fb3 | 2010 | |
56962b44 FW |
2011 | void |
2012 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2013 | { |
2014 | struct stack_frame frame; | |
2015 | const void __user *fp; | |
2016 | ||
927c7a9e FW |
2017 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2018 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2019 | return; |
927c7a9e | 2020 | } |
5a6cec3a | 2021 | |
d07bdfd3 PZ |
2022 | /* |
2023 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2024 | */ | |
2025 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2026 | return; | |
2027 | ||
74193ef0 | 2028 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2029 | |
70791ce9 | 2030 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2031 | |
20afc60f AV |
2032 | if (!current->mm) |
2033 | return; | |
2034 | ||
257ef9d2 TE |
2035 | if (perf_callchain_user32(regs, entry)) |
2036 | return; | |
2037 | ||
f9188e02 | 2038 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2039 | unsigned long bytes; |
038e836e | 2040 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2041 | frame.return_address = 0; |
2042 | ||
257ef9d2 TE |
2043 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
2044 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
2045 | break; |
2046 | ||
bc6ca7b3 AS |
2047 | if (!valid_user_frame(fp, sizeof(frame))) |
2048 | break; | |
2049 | ||
70791ce9 | 2050 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2051 | fp = frame.next_frame; |
d7d59fb3 PZ |
2052 | } |
2053 | } | |
2054 | ||
d07bdfd3 PZ |
2055 | /* |
2056 | * Deal with code segment offsets for the various execution modes: | |
2057 | * | |
2058 | * VM86 - the good olde 16 bit days, where the linear address is | |
2059 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2060 | * | |
2061 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2062 | * to figure out what the 32bit base address is. | |
2063 | * | |
2064 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2065 | * | |
2066 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2067 | */ | |
2068 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2069 | { |
d07bdfd3 PZ |
2070 | /* |
2071 | * If we are in VM86 mode, add the segment offset to convert to a | |
2072 | * linear address. | |
2073 | */ | |
2074 | if (regs->flags & X86_VM_MASK) | |
2075 | return 0x10 * regs->cs; | |
2076 | ||
2077 | /* | |
2078 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2079 | * effective IP to a linear address. | |
2080 | */ | |
2081 | #ifdef CONFIG_X86_32 | |
2082 | if (user_mode(regs) && regs->cs != __USER_CS) | |
2083 | return get_segment_base(regs->cs); | |
2084 | #else | |
2085 | if (test_thread_flag(TIF_IA32)) { | |
2086 | if (user_mode(regs) && regs->cs != __USER32_CS) | |
2087 | return get_segment_base(regs->cs); | |
2088 | } | |
2089 | #endif | |
2090 | return 0; | |
2091 | } | |
dcf46b94 | 2092 | |
d07bdfd3 PZ |
2093 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2094 | { | |
39447b38 | 2095 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2096 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2097 | |
d07bdfd3 | 2098 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2099 | } |
2100 | ||
2101 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2102 | { | |
2103 | int misc = 0; | |
dcf46b94 | 2104 | |
39447b38 | 2105 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2106 | if (perf_guest_cbs->is_user_mode()) |
2107 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2108 | else | |
2109 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2110 | } else { | |
d07bdfd3 | 2111 | if (user_mode(regs)) |
dcf46b94 ZY |
2112 | misc |= PERF_RECORD_MISC_USER; |
2113 | else | |
2114 | misc |= PERF_RECORD_MISC_KERNEL; | |
2115 | } | |
2116 | ||
39447b38 | 2117 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2118 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2119 | |
2120 | return misc; | |
2121 | } | |
b3d9468a GN |
2122 | |
2123 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2124 | { | |
2125 | cap->version = x86_pmu.version; | |
2126 | cap->num_counters_gp = x86_pmu.num_counters; | |
2127 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2128 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2129 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2130 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2131 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2132 | } | |
2133 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |