Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
241771ef | 35 | |
de0428a7 KW |
36 | #include "perf_event.h" |
37 | ||
de0428a7 | 38 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 39 | |
de0428a7 | 40 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
41 | .enabled = 1, |
42 | }; | |
241771ef | 43 | |
de0428a7 | 44 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
45 | [PERF_COUNT_HW_CACHE_MAX] |
46 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
47 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 48 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
49 | [PERF_COUNT_HW_CACHE_MAX] |
50 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
51 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 52 | |
ee06094f | 53 | /* |
cdd6c482 IM |
54 | * Propagate event elapsed time into the generic event. |
55 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
56 | * Returns the delta events processed. |
57 | */ | |
de0428a7 | 58 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 59 | { |
cc2ad4ba | 60 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 61 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 62 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 63 | int idx = hwc->idx; |
ec3232bd | 64 | s64 delta; |
ee06094f | 65 | |
15c7ad51 | 66 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
67 | return 0; |
68 | ||
ee06094f | 69 | /* |
cdd6c482 | 70 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
71 | * |
72 | * Our tactic to handle this is to first atomically read and | |
73 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 74 | * count to the generic event atomically: |
ee06094f IM |
75 | */ |
76 | again: | |
e7850595 | 77 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 78 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 79 | |
e7850595 | 80 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
81 | new_raw_count) != prev_raw_count) |
82 | goto again; | |
83 | ||
84 | /* | |
85 | * Now we have the new raw value and have updated the prev | |
86 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 87 | * (event-)time and add that to the generic event. |
ee06094f IM |
88 | * |
89 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 90 | * of the count. |
ee06094f | 91 | */ |
ec3232bd PZ |
92 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
93 | delta >>= shift; | |
ee06094f | 94 | |
e7850595 PZ |
95 | local64_add(delta, &event->count); |
96 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
97 | |
98 | return new_raw_count; | |
ee06094f IM |
99 | } |
100 | ||
a7e3ed1e AK |
101 | /* |
102 | * Find and validate any extra registers to set up. | |
103 | */ | |
104 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
105 | { | |
efc9f05d | 106 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
107 | struct extra_reg *er; |
108 | ||
efc9f05d | 109 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
110 | |
111 | if (!x86_pmu.extra_regs) | |
112 | return 0; | |
113 | ||
114 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
115 | if (er->event != (config & er->config_mask)) | |
116 | continue; | |
117 | if (event->attr.config1 & ~er->valid_mask) | |
118 | return -EINVAL; | |
efc9f05d SE |
119 | |
120 | reg->idx = er->idx; | |
121 | reg->config = event->attr.config1; | |
122 | reg->reg = er->msr; | |
a7e3ed1e AK |
123 | break; |
124 | } | |
125 | return 0; | |
126 | } | |
127 | ||
cdd6c482 | 128 | static atomic_t active_events; |
4e935e47 PZ |
129 | static DEFINE_MUTEX(pmc_reserve_mutex); |
130 | ||
b27ea29c RR |
131 | #ifdef CONFIG_X86_LOCAL_APIC |
132 | ||
4e935e47 PZ |
133 | static bool reserve_pmc_hardware(void) |
134 | { | |
135 | int i; | |
136 | ||
948b1bb8 | 137 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 138 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
139 | goto perfctr_fail; |
140 | } | |
141 | ||
948b1bb8 | 142 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 143 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
144 | goto eventsel_fail; |
145 | } | |
146 | ||
147 | return true; | |
148 | ||
149 | eventsel_fail: | |
150 | for (i--; i >= 0; i--) | |
41bf4989 | 151 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 152 | |
948b1bb8 | 153 | i = x86_pmu.num_counters; |
4e935e47 PZ |
154 | |
155 | perfctr_fail: | |
156 | for (i--; i >= 0; i--) | |
41bf4989 | 157 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 158 | |
4e935e47 PZ |
159 | return false; |
160 | } | |
161 | ||
162 | static void release_pmc_hardware(void) | |
163 | { | |
164 | int i; | |
165 | ||
948b1bb8 | 166 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
168 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 169 | } |
4e935e47 PZ |
170 | } |
171 | ||
b27ea29c RR |
172 | #else |
173 | ||
174 | static bool reserve_pmc_hardware(void) { return true; } | |
175 | static void release_pmc_hardware(void) {} | |
176 | ||
177 | #endif | |
178 | ||
33c6d6a7 DZ |
179 | static bool check_hw_exists(void) |
180 | { | |
181 | u64 val, val_new = 0; | |
4407204c | 182 | int i, reg, ret = 0; |
33c6d6a7 | 183 | |
4407204c PZ |
184 | /* |
185 | * Check to see if the BIOS enabled any of the counters, if so | |
186 | * complain and bail. | |
187 | */ | |
188 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 189 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
190 | ret = rdmsrl_safe(reg, &val); |
191 | if (ret) | |
192 | goto msr_fail; | |
193 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
194 | goto bios_fail; | |
195 | } | |
196 | ||
197 | if (x86_pmu.num_counters_fixed) { | |
198 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
199 | ret = rdmsrl_safe(reg, &val); | |
200 | if (ret) | |
201 | goto msr_fail; | |
202 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
203 | if (val & (0x03 << i*4)) | |
204 | goto bios_fail; | |
205 | } | |
206 | } | |
207 | ||
208 | /* | |
209 | * Now write a value and read it back to see if it matches, | |
210 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
211 | * that don't trap on the MSR access and always return 0s. | |
212 | */ | |
33c6d6a7 | 213 | val = 0xabcdUL; |
715c85b1 | 214 | ret = wrmsrl_safe(x86_pmu_event_addr(0), val); |
41bf4989 | 215 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); |
33c6d6a7 | 216 | if (ret || val != val_new) |
4407204c | 217 | goto msr_fail; |
33c6d6a7 DZ |
218 | |
219 | return true; | |
4407204c PZ |
220 | |
221 | bios_fail: | |
45daae57 IM |
222 | /* |
223 | * We still allow the PMU driver to operate: | |
224 | */ | |
225 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 226 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
227 | |
228 | return true; | |
4407204c PZ |
229 | |
230 | msr_fail: | |
231 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 232 | |
4407204c | 233 | return false; |
33c6d6a7 DZ |
234 | } |
235 | ||
cdd6c482 | 236 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 237 | { |
cdd6c482 | 238 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 239 | release_pmc_hardware(); |
ca037701 | 240 | release_ds_buffers(); |
4e935e47 PZ |
241 | mutex_unlock(&pmc_reserve_mutex); |
242 | } | |
243 | } | |
244 | ||
85cf9dba RR |
245 | static inline int x86_pmu_initialized(void) |
246 | { | |
247 | return x86_pmu.handle_irq != NULL; | |
248 | } | |
249 | ||
8326f44d | 250 | static inline int |
e994d7d2 | 251 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 252 | { |
e994d7d2 | 253 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
254 | unsigned int cache_type, cache_op, cache_result; |
255 | u64 config, val; | |
256 | ||
257 | config = attr->config; | |
258 | ||
259 | cache_type = (config >> 0) & 0xff; | |
260 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
261 | return -EINVAL; | |
262 | ||
263 | cache_op = (config >> 8) & 0xff; | |
264 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
265 | return -EINVAL; | |
266 | ||
267 | cache_result = (config >> 16) & 0xff; | |
268 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
269 | return -EINVAL; | |
270 | ||
271 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
272 | ||
273 | if (val == 0) | |
274 | return -ENOENT; | |
275 | ||
276 | if (val == -1) | |
277 | return -EINVAL; | |
278 | ||
279 | hwc->config |= val; | |
e994d7d2 AK |
280 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
281 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
282 | } |
283 | ||
de0428a7 | 284 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
285 | { |
286 | struct perf_event_attr *attr = &event->attr; | |
287 | struct hw_perf_event *hwc = &event->hw; | |
288 | u64 config; | |
289 | ||
6c7e550f | 290 | if (!is_sampling_event(event)) { |
c1726f34 RR |
291 | hwc->sample_period = x86_pmu.max_period; |
292 | hwc->last_period = hwc->sample_period; | |
e7850595 | 293 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
294 | } else { |
295 | /* | |
296 | * If we have a PMU initialized but no APIC | |
297 | * interrupts, we cannot sample hardware | |
298 | * events (user-space has to fall back and | |
299 | * sample via a hrtimer based software event): | |
300 | */ | |
301 | if (!x86_pmu.apic) | |
302 | return -EOPNOTSUPP; | |
303 | } | |
304 | ||
305 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 306 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
307 | |
308 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 309 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
310 | |
311 | if (attr->config >= x86_pmu.max_events) | |
312 | return -EINVAL; | |
313 | ||
314 | /* | |
315 | * The generic map: | |
316 | */ | |
317 | config = x86_pmu.event_map(attr->config); | |
318 | ||
319 | if (config == 0) | |
320 | return -ENOENT; | |
321 | ||
322 | if (config == -1LL) | |
323 | return -EINVAL; | |
324 | ||
325 | /* | |
326 | * Branch tracing: | |
327 | */ | |
18a073a3 PZ |
328 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
329 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 330 | /* BTS is not supported by this architecture. */ |
6809b6ea | 331 | if (!x86_pmu.bts_active) |
c1726f34 RR |
332 | return -EOPNOTSUPP; |
333 | ||
334 | /* BTS is currently only allowed for user-mode. */ | |
335 | if (!attr->exclude_kernel) | |
336 | return -EOPNOTSUPP; | |
337 | } | |
338 | ||
339 | hwc->config |= config; | |
340 | ||
341 | return 0; | |
342 | } | |
4261e0e0 | 343 | |
ff3fb511 SE |
344 | /* |
345 | * check that branch_sample_type is compatible with | |
346 | * settings needed for precise_ip > 1 which implies | |
347 | * using the LBR to capture ALL taken branches at the | |
348 | * priv levels of the measurement | |
349 | */ | |
350 | static inline int precise_br_compat(struct perf_event *event) | |
351 | { | |
352 | u64 m = event->attr.branch_sample_type; | |
353 | u64 b = 0; | |
354 | ||
355 | /* must capture all branches */ | |
356 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
357 | return 0; | |
358 | ||
359 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
360 | ||
361 | if (!event->attr.exclude_user) | |
362 | b |= PERF_SAMPLE_BRANCH_USER; | |
363 | ||
364 | if (!event->attr.exclude_kernel) | |
365 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
366 | ||
367 | /* | |
368 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
369 | */ | |
370 | ||
371 | return m == b; | |
372 | } | |
373 | ||
de0428a7 | 374 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 375 | { |
ab608344 PZ |
376 | if (event->attr.precise_ip) { |
377 | int precise = 0; | |
378 | ||
379 | /* Support for constant skid */ | |
6809b6ea | 380 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
381 | precise++; |
382 | ||
5553be26 PZ |
383 | /* Support for IP fixup */ |
384 | if (x86_pmu.lbr_nr) | |
385 | precise++; | |
386 | } | |
ab608344 PZ |
387 | |
388 | if (event->attr.precise_ip > precise) | |
389 | return -EOPNOTSUPP; | |
ff3fb511 SE |
390 | /* |
391 | * check that PEBS LBR correction does not conflict with | |
392 | * whatever the user is asking with attr->branch_sample_type | |
393 | */ | |
394 | if (event->attr.precise_ip > 1) { | |
395 | u64 *br_type = &event->attr.branch_sample_type; | |
396 | ||
397 | if (has_branch_stack(event)) { | |
398 | if (!precise_br_compat(event)) | |
399 | return -EOPNOTSUPP; | |
400 | ||
401 | /* branch_sample_type is compatible */ | |
402 | ||
403 | } else { | |
404 | /* | |
405 | * user did not specify branch_sample_type | |
406 | * | |
407 | * For PEBS fixups, we capture all | |
408 | * the branches at the priv level of the | |
409 | * event. | |
410 | */ | |
411 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
412 | ||
413 | if (!event->attr.exclude_user) | |
414 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
415 | ||
416 | if (!event->attr.exclude_kernel) | |
417 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
418 | } | |
419 | } | |
ab608344 PZ |
420 | } |
421 | ||
a072738e CG |
422 | /* |
423 | * Generate PMC IRQs: | |
424 | * (keep 'enabled' bit clear for now) | |
425 | */ | |
b4cdc5c2 | 426 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
427 | |
428 | /* | |
429 | * Count user and OS events unless requested not to | |
430 | */ | |
b4cdc5c2 PZ |
431 | if (!event->attr.exclude_user) |
432 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
433 | if (!event->attr.exclude_kernel) | |
434 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 435 | |
b4cdc5c2 PZ |
436 | if (event->attr.type == PERF_TYPE_RAW) |
437 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 438 | |
9d0fcba6 | 439 | return x86_setup_perfctr(event); |
a098f448 RR |
440 | } |
441 | ||
241771ef | 442 | /* |
0d48696f | 443 | * Setup the hardware configuration for a given attr_type |
241771ef | 444 | */ |
b0a873eb | 445 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 446 | { |
4e935e47 | 447 | int err; |
241771ef | 448 | |
85cf9dba RR |
449 | if (!x86_pmu_initialized()) |
450 | return -ENODEV; | |
241771ef | 451 | |
4e935e47 | 452 | err = 0; |
cdd6c482 | 453 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 454 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 455 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
456 | if (!reserve_pmc_hardware()) |
457 | err = -EBUSY; | |
f80c9e30 PZ |
458 | else |
459 | reserve_ds_buffers(); | |
30dd568c MM |
460 | } |
461 | if (!err) | |
cdd6c482 | 462 | atomic_inc(&active_events); |
4e935e47 PZ |
463 | mutex_unlock(&pmc_reserve_mutex); |
464 | } | |
465 | if (err) | |
466 | return err; | |
467 | ||
cdd6c482 | 468 | event->destroy = hw_perf_event_destroy; |
a1792cda | 469 | |
4261e0e0 RR |
470 | event->hw.idx = -1; |
471 | event->hw.last_cpu = -1; | |
472 | event->hw.last_tag = ~0ULL; | |
b690081d | 473 | |
efc9f05d SE |
474 | /* mark unused */ |
475 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
476 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
477 | ||
9d0fcba6 | 478 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
479 | } |
480 | ||
de0428a7 | 481 | void x86_pmu_disable_all(void) |
f87ad35d | 482 | { |
cdd6c482 | 483 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
484 | int idx; |
485 | ||
948b1bb8 | 486 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
487 | u64 val; |
488 | ||
43f6201a | 489 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 490 | continue; |
41bf4989 | 491 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 492 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 493 | continue; |
bb1165d6 | 494 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 495 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 496 | } |
f87ad35d JSR |
497 | } |
498 | ||
a4eaf7f1 | 499 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 500 | { |
1da53e02 SE |
501 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
502 | ||
85cf9dba | 503 | if (!x86_pmu_initialized()) |
9e35ad38 | 504 | return; |
1da53e02 | 505 | |
1a6e21f7 PZ |
506 | if (!cpuc->enabled) |
507 | return; | |
508 | ||
509 | cpuc->n_added = 0; | |
510 | cpuc->enabled = 0; | |
511 | barrier(); | |
1da53e02 SE |
512 | |
513 | x86_pmu.disable_all(); | |
b56a3802 | 514 | } |
241771ef | 515 | |
de0428a7 | 516 | void x86_pmu_enable_all(int added) |
f87ad35d | 517 | { |
cdd6c482 | 518 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
519 | int idx; |
520 | ||
948b1bb8 | 521 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 522 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 523 | |
43f6201a | 524 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 525 | continue; |
984b838c | 526 | |
d45dd923 | 527 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
528 | } |
529 | } | |
530 | ||
51b0fe39 | 531 | static struct pmu pmu; |
1da53e02 SE |
532 | |
533 | static inline int is_x86_event(struct perf_event *event) | |
534 | { | |
535 | return event->pmu == &pmu; | |
536 | } | |
537 | ||
1e2ad28f RR |
538 | /* |
539 | * Event scheduler state: | |
540 | * | |
541 | * Assign events iterating over all events and counters, beginning | |
542 | * with events with least weights first. Keep the current iterator | |
543 | * state in struct sched_state. | |
544 | */ | |
545 | struct sched_state { | |
546 | int weight; | |
547 | int event; /* event index */ | |
548 | int counter; /* counter index */ | |
549 | int unassigned; /* number of events to be assigned left */ | |
550 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
551 | }; | |
552 | ||
bc1738f6 RR |
553 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
554 | #define SCHED_STATES_MAX 2 | |
555 | ||
1e2ad28f RR |
556 | struct perf_sched { |
557 | int max_weight; | |
558 | int max_events; | |
559 | struct event_constraint **constraints; | |
560 | struct sched_state state; | |
bc1738f6 RR |
561 | int saved_states; |
562 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
563 | }; |
564 | ||
565 | /* | |
566 | * Initialize interator that runs through all events and counters. | |
567 | */ | |
568 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c, | |
569 | int num, int wmin, int wmax) | |
570 | { | |
571 | int idx; | |
572 | ||
573 | memset(sched, 0, sizeof(*sched)); | |
574 | sched->max_events = num; | |
575 | sched->max_weight = wmax; | |
576 | sched->constraints = c; | |
577 | ||
578 | for (idx = 0; idx < num; idx++) { | |
579 | if (c[idx]->weight == wmin) | |
580 | break; | |
581 | } | |
582 | ||
583 | sched->state.event = idx; /* start with min weight */ | |
584 | sched->state.weight = wmin; | |
585 | sched->state.unassigned = num; | |
586 | } | |
587 | ||
bc1738f6 RR |
588 | static void perf_sched_save_state(struct perf_sched *sched) |
589 | { | |
590 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
591 | return; | |
592 | ||
593 | sched->saved[sched->saved_states] = sched->state; | |
594 | sched->saved_states++; | |
595 | } | |
596 | ||
597 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
598 | { | |
599 | if (!sched->saved_states) | |
600 | return false; | |
601 | ||
602 | sched->saved_states--; | |
603 | sched->state = sched->saved[sched->saved_states]; | |
604 | ||
605 | /* continue with next counter: */ | |
606 | clear_bit(sched->state.counter++, sched->state.used); | |
607 | ||
608 | return true; | |
609 | } | |
610 | ||
1e2ad28f RR |
611 | /* |
612 | * Select a counter for the current event to schedule. Return true on | |
613 | * success. | |
614 | */ | |
bc1738f6 | 615 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
616 | { |
617 | struct event_constraint *c; | |
618 | int idx; | |
619 | ||
620 | if (!sched->state.unassigned) | |
621 | return false; | |
622 | ||
623 | if (sched->state.event >= sched->max_events) | |
624 | return false; | |
625 | ||
626 | c = sched->constraints[sched->state.event]; | |
627 | ||
4defea85 | 628 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
629 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
630 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 631 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
632 | if (!__test_and_set_bit(idx, sched->state.used)) |
633 | goto done; | |
634 | } | |
635 | } | |
1e2ad28f RR |
636 | /* Grab the first unused counter starting with idx */ |
637 | idx = sched->state.counter; | |
15c7ad51 | 638 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 639 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 640 | goto done; |
1e2ad28f | 641 | } |
1e2ad28f | 642 | |
4defea85 PZ |
643 | return false; |
644 | ||
645 | done: | |
646 | sched->state.counter = idx; | |
1e2ad28f | 647 | |
bc1738f6 RR |
648 | if (c->overlap) |
649 | perf_sched_save_state(sched); | |
650 | ||
651 | return true; | |
652 | } | |
653 | ||
654 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
655 | { | |
656 | while (!__perf_sched_find_counter(sched)) { | |
657 | if (!perf_sched_restore_state(sched)) | |
658 | return false; | |
659 | } | |
660 | ||
1e2ad28f RR |
661 | return true; |
662 | } | |
663 | ||
664 | /* | |
665 | * Go through all unassigned events and find the next one to schedule. | |
666 | * Take events with the least weight first. Return true on success. | |
667 | */ | |
668 | static bool perf_sched_next_event(struct perf_sched *sched) | |
669 | { | |
670 | struct event_constraint *c; | |
671 | ||
672 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
673 | return false; | |
674 | ||
675 | do { | |
676 | /* next event */ | |
677 | sched->state.event++; | |
678 | if (sched->state.event >= sched->max_events) { | |
679 | /* next weight */ | |
680 | sched->state.event = 0; | |
681 | sched->state.weight++; | |
682 | if (sched->state.weight > sched->max_weight) | |
683 | return false; | |
684 | } | |
685 | c = sched->constraints[sched->state.event]; | |
686 | } while (c->weight != sched->state.weight); | |
687 | ||
688 | sched->state.counter = 0; /* start with first counter */ | |
689 | ||
690 | return true; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Assign a counter for each event. | |
695 | */ | |
4b4969b1 YZ |
696 | int perf_assign_events(struct event_constraint **constraints, int n, |
697 | int wmin, int wmax, int *assign) | |
1e2ad28f RR |
698 | { |
699 | struct perf_sched sched; | |
700 | ||
701 | perf_sched_init(&sched, constraints, n, wmin, wmax); | |
702 | ||
703 | do { | |
704 | if (!perf_sched_find_counter(&sched)) | |
705 | break; /* failed */ | |
706 | if (assign) | |
707 | assign[sched.state.event] = sched.state.counter; | |
708 | } while (perf_sched_next_event(&sched)); | |
709 | ||
710 | return sched.state.unassigned; | |
711 | } | |
712 | ||
de0428a7 | 713 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 714 | { |
63b14649 | 715 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 716 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 717 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
718 | struct hw_perf_event *hwc; |
719 | ||
720 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
721 | ||
1e2ad28f | 722 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b622d644 PZ |
723 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
724 | constraints[i] = c; | |
1e2ad28f RR |
725 | wmin = min(wmin, c->weight); |
726 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
727 | } |
728 | ||
8113070d SE |
729 | /* |
730 | * fastpath, try to reuse previous register | |
731 | */ | |
c933c1a6 | 732 | for (i = 0; i < n; i++) { |
8113070d | 733 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 734 | c = constraints[i]; |
8113070d SE |
735 | |
736 | /* never assigned */ | |
737 | if (hwc->idx == -1) | |
738 | break; | |
739 | ||
740 | /* constraint still honored */ | |
63b14649 | 741 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
742 | break; |
743 | ||
744 | /* not already used */ | |
745 | if (test_bit(hwc->idx, used_mask)) | |
746 | break; | |
747 | ||
34538ee7 | 748 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
749 | if (assign) |
750 | assign[i] = hwc->idx; | |
751 | } | |
8113070d | 752 | |
1e2ad28f RR |
753 | /* slow path */ |
754 | if (i != n) | |
755 | num = perf_assign_events(constraints, n, wmin, wmax, assign); | |
8113070d | 756 | |
1da53e02 SE |
757 | /* |
758 | * scheduling failed or is just a simulation, | |
759 | * free resources if necessary | |
760 | */ | |
761 | if (!assign || num) { | |
762 | for (i = 0; i < n; i++) { | |
763 | if (x86_pmu.put_event_constraints) | |
764 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
765 | } | |
766 | } | |
aa2bc1ad | 767 | return num ? -EINVAL : 0; |
1da53e02 SE |
768 | } |
769 | ||
770 | /* | |
771 | * dogrp: true if must collect siblings events (group) | |
772 | * returns total number of events and error code | |
773 | */ | |
774 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
775 | { | |
776 | struct perf_event *event; | |
777 | int n, max_count; | |
778 | ||
948b1bb8 | 779 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
780 | |
781 | /* current number of events already accepted */ | |
782 | n = cpuc->n_events; | |
783 | ||
784 | if (is_x86_event(leader)) { | |
785 | if (n >= max_count) | |
aa2bc1ad | 786 | return -EINVAL; |
1da53e02 SE |
787 | cpuc->event_list[n] = leader; |
788 | n++; | |
789 | } | |
790 | if (!dogrp) | |
791 | return n; | |
792 | ||
793 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
794 | if (!is_x86_event(event) || | |
8113070d | 795 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
796 | continue; |
797 | ||
798 | if (n >= max_count) | |
aa2bc1ad | 799 | return -EINVAL; |
1da53e02 SE |
800 | |
801 | cpuc->event_list[n] = event; | |
802 | n++; | |
803 | } | |
804 | return n; | |
805 | } | |
806 | ||
1da53e02 | 807 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 808 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 809 | { |
447a194b SE |
810 | struct hw_perf_event *hwc = &event->hw; |
811 | ||
812 | hwc->idx = cpuc->assign[i]; | |
813 | hwc->last_cpu = smp_processor_id(); | |
814 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 815 | |
15c7ad51 | 816 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
817 | hwc->config_base = 0; |
818 | hwc->event_base = 0; | |
15c7ad51 | 819 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 820 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
821 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
822 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 823 | } else { |
73d6e522 RR |
824 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
825 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
76958a61 | 826 | hwc->event_base_rdpmc = hwc->idx; |
1da53e02 SE |
827 | } |
828 | } | |
829 | ||
447a194b SE |
830 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
831 | struct cpu_hw_events *cpuc, | |
832 | int i) | |
833 | { | |
834 | return hwc->idx == cpuc->assign[i] && | |
835 | hwc->last_cpu == smp_processor_id() && | |
836 | hwc->last_tag == cpuc->tags[i]; | |
837 | } | |
838 | ||
a4eaf7f1 | 839 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 840 | |
a4eaf7f1 | 841 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 842 | { |
1da53e02 SE |
843 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
844 | struct perf_event *event; | |
845 | struct hw_perf_event *hwc; | |
11164cd4 | 846 | int i, added = cpuc->n_added; |
1da53e02 | 847 | |
85cf9dba | 848 | if (!x86_pmu_initialized()) |
2b9ff0db | 849 | return; |
1a6e21f7 PZ |
850 | |
851 | if (cpuc->enabled) | |
852 | return; | |
853 | ||
1da53e02 | 854 | if (cpuc->n_added) { |
19925ce7 | 855 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
856 | /* |
857 | * apply assignment obtained either from | |
858 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
859 | * | |
860 | * step1: save events moving to new counters | |
861 | * step2: reprogram moved events into new counters | |
862 | */ | |
19925ce7 | 863 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
864 | event = cpuc->event_list[i]; |
865 | hwc = &event->hw; | |
866 | ||
447a194b SE |
867 | /* |
868 | * we can avoid reprogramming counter if: | |
869 | * - assigned same counter as last time | |
870 | * - running on same CPU as last time | |
871 | * - no other event has used the counter since | |
872 | */ | |
873 | if (hwc->idx == -1 || | |
874 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
875 | continue; |
876 | ||
a4eaf7f1 PZ |
877 | /* |
878 | * Ensure we don't accidentally enable a stopped | |
879 | * counter simply because we rescheduled. | |
880 | */ | |
881 | if (hwc->state & PERF_HES_STOPPED) | |
882 | hwc->state |= PERF_HES_ARCH; | |
883 | ||
884 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
885 | } |
886 | ||
887 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
888 | event = cpuc->event_list[i]; |
889 | hwc = &event->hw; | |
890 | ||
45e16a68 | 891 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 892 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
893 | else if (i < n_running) |
894 | continue; | |
1da53e02 | 895 | |
a4eaf7f1 PZ |
896 | if (hwc->state & PERF_HES_ARCH) |
897 | continue; | |
898 | ||
899 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
900 | } |
901 | cpuc->n_added = 0; | |
902 | perf_events_lapic_init(); | |
903 | } | |
1a6e21f7 PZ |
904 | |
905 | cpuc->enabled = 1; | |
906 | barrier(); | |
907 | ||
11164cd4 | 908 | x86_pmu.enable_all(added); |
ee06094f | 909 | } |
ee06094f | 910 | |
245b2e70 | 911 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 912 | |
ee06094f IM |
913 | /* |
914 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 915 | * To be called with the event disabled in hw: |
ee06094f | 916 | */ |
de0428a7 | 917 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 918 | { |
07088edb | 919 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 920 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 921 | s64 period = hwc->sample_period; |
7645a24c | 922 | int ret = 0, idx = hwc->idx; |
ee06094f | 923 | |
15c7ad51 | 924 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
925 | return 0; |
926 | ||
ee06094f | 927 | /* |
af901ca1 | 928 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
929 | */ |
930 | if (unlikely(left <= -period)) { | |
931 | left = period; | |
e7850595 | 932 | local64_set(&hwc->period_left, left); |
9e350de3 | 933 | hwc->last_period = period; |
e4abb5d4 | 934 | ret = 1; |
ee06094f IM |
935 | } |
936 | ||
937 | if (unlikely(left <= 0)) { | |
938 | left += period; | |
e7850595 | 939 | local64_set(&hwc->period_left, left); |
9e350de3 | 940 | hwc->last_period = period; |
e4abb5d4 | 941 | ret = 1; |
ee06094f | 942 | } |
1c80f4b5 | 943 | /* |
dfc65094 | 944 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
945 | */ |
946 | if (unlikely(left < 2)) | |
947 | left = 2; | |
241771ef | 948 | |
e4abb5d4 PZ |
949 | if (left > x86_pmu.max_period) |
950 | left = x86_pmu.max_period; | |
951 | ||
245b2e70 | 952 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
953 | |
954 | /* | |
cdd6c482 | 955 | * The hw event starts counting from this event offset, |
ee06094f IM |
956 | * mark it to be able to extra future deltas: |
957 | */ | |
e7850595 | 958 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 959 | |
73d6e522 | 960 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
961 | |
962 | /* | |
963 | * Due to erratum on certan cpu we need | |
964 | * a second write to be sure the register | |
965 | * is updated properly | |
966 | */ | |
967 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 968 | wrmsrl(hwc->event_base, |
948b1bb8 | 969 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 970 | } |
e4abb5d4 | 971 | |
cdd6c482 | 972 | perf_event_update_userpage(event); |
194002b2 | 973 | |
e4abb5d4 | 974 | return ret; |
2f18d1e8 IM |
975 | } |
976 | ||
de0428a7 | 977 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 978 | { |
0a3aee0d | 979 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
980 | __x86_pmu_enable_event(&event->hw, |
981 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
982 | } |
983 | ||
b690081d | 984 | /* |
a4eaf7f1 | 985 | * Add a single event to the PMU. |
1da53e02 SE |
986 | * |
987 | * The event is added to the group of enabled events | |
988 | * but only if it can be scehduled with existing events. | |
fe9081cc | 989 | */ |
a4eaf7f1 | 990 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
991 | { |
992 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
993 | struct hw_perf_event *hwc; |
994 | int assign[X86_PMC_IDX_MAX]; | |
995 | int n, n0, ret; | |
fe9081cc | 996 | |
1da53e02 | 997 | hwc = &event->hw; |
fe9081cc | 998 | |
33696fc0 | 999 | perf_pmu_disable(event->pmu); |
1da53e02 | 1000 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1001 | ret = n = collect_events(cpuc, event, false); |
1002 | if (ret < 0) | |
1003 | goto out; | |
53b441a5 | 1004 | |
a4eaf7f1 PZ |
1005 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1006 | if (!(flags & PERF_EF_START)) | |
1007 | hwc->state |= PERF_HES_ARCH; | |
1008 | ||
4d1c52b0 LM |
1009 | /* |
1010 | * If group events scheduling transaction was started, | |
0d2eb44f | 1011 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1012 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1013 | */ |
8d2cacbb | 1014 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1015 | goto done_collect; |
4d1c52b0 | 1016 | |
a072738e | 1017 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1018 | if (ret) |
24cd7f54 | 1019 | goto out; |
1da53e02 SE |
1020 | /* |
1021 | * copy new assignment, now we know it is possible | |
1022 | * will be used by hw_perf_enable() | |
1023 | */ | |
1024 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1025 | |
24cd7f54 | 1026 | done_collect: |
1da53e02 | 1027 | cpuc->n_events = n; |
356e1f2e | 1028 | cpuc->n_added += n - n0; |
90151c35 | 1029 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1030 | |
24cd7f54 PZ |
1031 | ret = 0; |
1032 | out: | |
33696fc0 | 1033 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1034 | return ret; |
241771ef IM |
1035 | } |
1036 | ||
a4eaf7f1 | 1037 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1038 | { |
c08053e6 PZ |
1039 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1040 | int idx = event->hw.idx; | |
1041 | ||
a4eaf7f1 PZ |
1042 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1043 | return; | |
1044 | ||
1045 | if (WARN_ON_ONCE(idx == -1)) | |
1046 | return; | |
1047 | ||
1048 | if (flags & PERF_EF_RELOAD) { | |
1049 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1050 | x86_perf_event_set_period(event); | |
1051 | } | |
1052 | ||
1053 | event->hw.state = 0; | |
d76a0812 | 1054 | |
c08053e6 PZ |
1055 | cpuc->events[idx] = event; |
1056 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1057 | __set_bit(idx, cpuc->running); |
aff3d91a | 1058 | x86_pmu.enable(event); |
c08053e6 | 1059 | perf_event_update_userpage(event); |
a78ac325 PZ |
1060 | } |
1061 | ||
cdd6c482 | 1062 | void perf_event_print_debug(void) |
241771ef | 1063 | { |
2f18d1e8 | 1064 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1065 | u64 pebs; |
cdd6c482 | 1066 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1067 | unsigned long flags; |
1e125676 IM |
1068 | int cpu, idx; |
1069 | ||
948b1bb8 | 1070 | if (!x86_pmu.num_counters) |
1e125676 | 1071 | return; |
241771ef | 1072 | |
5bb9efe3 | 1073 | local_irq_save(flags); |
241771ef IM |
1074 | |
1075 | cpu = smp_processor_id(); | |
cdd6c482 | 1076 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1077 | |
faa28ae0 | 1078 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1079 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1080 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1081 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1082 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1083 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1084 | |
1085 | pr_info("\n"); | |
1086 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1087 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1088 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1089 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1090 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1091 | } |
7645a24c | 1092 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1093 | |
948b1bb8 | 1094 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1095 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1096 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1097 | |
245b2e70 | 1098 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1099 | |
a1ef58f4 | 1100 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1101 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1102 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1103 | cpu, idx, pmc_count); |
a1ef58f4 | 1104 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1105 | cpu, idx, prev_left); |
241771ef | 1106 | } |
948b1bb8 | 1107 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1108 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1109 | ||
a1ef58f4 | 1110 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1111 | cpu, idx, pmc_count); |
1112 | } | |
5bb9efe3 | 1113 | local_irq_restore(flags); |
241771ef IM |
1114 | } |
1115 | ||
de0428a7 | 1116 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1117 | { |
d76a0812 | 1118 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1119 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1120 | |
a4eaf7f1 PZ |
1121 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1122 | x86_pmu.disable(event); | |
1123 | cpuc->events[hwc->idx] = NULL; | |
1124 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1125 | hwc->state |= PERF_HES_STOPPED; | |
1126 | } | |
30dd568c | 1127 | |
a4eaf7f1 PZ |
1128 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1129 | /* | |
1130 | * Drain the remaining delta count out of a event | |
1131 | * that we are disabling: | |
1132 | */ | |
1133 | x86_perf_event_update(event); | |
1134 | hwc->state |= PERF_HES_UPTODATE; | |
1135 | } | |
2e841873 PZ |
1136 | } |
1137 | ||
a4eaf7f1 | 1138 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1139 | { |
1140 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1141 | int i; | |
1142 | ||
90151c35 SE |
1143 | /* |
1144 | * If we're called during a txn, we don't need to do anything. | |
1145 | * The events never got scheduled and ->cancel_txn will truncate | |
1146 | * the event_list. | |
1147 | */ | |
8d2cacbb | 1148 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1149 | return; |
1150 | ||
a4eaf7f1 | 1151 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1152 | |
1da53e02 SE |
1153 | for (i = 0; i < cpuc->n_events; i++) { |
1154 | if (event == cpuc->event_list[i]) { | |
1155 | ||
1156 | if (x86_pmu.put_event_constraints) | |
1157 | x86_pmu.put_event_constraints(cpuc, event); | |
1158 | ||
1159 | while (++i < cpuc->n_events) | |
1160 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1161 | ||
1162 | --cpuc->n_events; | |
6c9687ab | 1163 | break; |
1da53e02 SE |
1164 | } |
1165 | } | |
cdd6c482 | 1166 | perf_event_update_userpage(event); |
241771ef IM |
1167 | } |
1168 | ||
de0428a7 | 1169 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1170 | { |
df1a132b | 1171 | struct perf_sample_data data; |
cdd6c482 IM |
1172 | struct cpu_hw_events *cpuc; |
1173 | struct perf_event *event; | |
11d1578f | 1174 | int idx, handled = 0; |
9029a5e3 IM |
1175 | u64 val; |
1176 | ||
cdd6c482 | 1177 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1178 | |
2bce5dac DZ |
1179 | /* |
1180 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1181 | * inside the nmi handler. As a result, the unmasking was pushed | |
1182 | * into all the nmi handlers. | |
1183 | * | |
1184 | * This generic handler doesn't seem to have any issues where the | |
1185 | * unmasking occurs so it was left at the top. | |
1186 | */ | |
1187 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1188 | ||
948b1bb8 | 1189 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1190 | if (!test_bit(idx, cpuc->active_mask)) { |
1191 | /* | |
1192 | * Though we deactivated the counter some cpus | |
1193 | * might still deliver spurious interrupts still | |
1194 | * in flight. Catch them: | |
1195 | */ | |
1196 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1197 | handled++; | |
a29aa8a7 | 1198 | continue; |
63e6be6d | 1199 | } |
962bf7a6 | 1200 | |
cdd6c482 | 1201 | event = cpuc->events[idx]; |
a4016a79 | 1202 | |
cc2ad4ba | 1203 | val = x86_perf_event_update(event); |
948b1bb8 | 1204 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1205 | continue; |
962bf7a6 | 1206 | |
9e350de3 | 1207 | /* |
cdd6c482 | 1208 | * event overflow |
9e350de3 | 1209 | */ |
4177c42a | 1210 | handled++; |
fd0d000b | 1211 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1212 | |
07088edb | 1213 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1214 | continue; |
1215 | ||
a8b0ca17 | 1216 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1217 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1218 | } |
962bf7a6 | 1219 | |
9e350de3 PZ |
1220 | if (handled) |
1221 | inc_irq_stat(apic_perf_irqs); | |
1222 | ||
a29aa8a7 RR |
1223 | return handled; |
1224 | } | |
39d81eab | 1225 | |
cdd6c482 | 1226 | void perf_events_lapic_init(void) |
241771ef | 1227 | { |
04da8a43 | 1228 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1229 | return; |
85cf9dba | 1230 | |
241771ef | 1231 | /* |
c323d95f | 1232 | * Always use NMI for PMU |
241771ef | 1233 | */ |
c323d95f | 1234 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1235 | } |
1236 | ||
1237 | static int __kprobes | |
9c48f1c6 | 1238 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1239 | { |
cdd6c482 | 1240 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1241 | return NMI_DONE; |
4177c42a | 1242 | |
9c48f1c6 | 1243 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1244 | } |
1245 | ||
de0428a7 KW |
1246 | struct event_constraint emptyconstraint; |
1247 | struct event_constraint unconstrained; | |
f87ad35d | 1248 | |
3f6da390 PZ |
1249 | static int __cpuinit |
1250 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1251 | { | |
1252 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1253 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1254 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1255 | |
1256 | switch (action & ~CPU_TASKS_FROZEN) { | |
1257 | case CPU_UP_PREPARE: | |
7fdba1ca | 1258 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1259 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1260 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1261 | break; |
1262 | ||
1263 | case CPU_STARTING: | |
0c9d42ed PZ |
1264 | if (x86_pmu.attr_rdpmc) |
1265 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1266 | if (x86_pmu.cpu_starting) |
1267 | x86_pmu.cpu_starting(cpu); | |
1268 | break; | |
1269 | ||
7fdba1ca PZ |
1270 | case CPU_ONLINE: |
1271 | kfree(cpuc->kfree_on_online); | |
1272 | break; | |
1273 | ||
3f6da390 PZ |
1274 | case CPU_DYING: |
1275 | if (x86_pmu.cpu_dying) | |
1276 | x86_pmu.cpu_dying(cpu); | |
1277 | break; | |
1278 | ||
b38b24ea | 1279 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1280 | case CPU_DEAD: |
1281 | if (x86_pmu.cpu_dead) | |
1282 | x86_pmu.cpu_dead(cpu); | |
1283 | break; | |
1284 | ||
1285 | default: | |
1286 | break; | |
1287 | } | |
1288 | ||
b38b24ea | 1289 | return ret; |
3f6da390 PZ |
1290 | } |
1291 | ||
12558038 CG |
1292 | static void __init pmu_check_apic(void) |
1293 | { | |
1294 | if (cpu_has_apic) | |
1295 | return; | |
1296 | ||
1297 | x86_pmu.apic = 0; | |
1298 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1299 | pr_info("no hardware sampling interrupt available.\n"); | |
1300 | } | |
1301 | ||
641cc938 JO |
1302 | static struct attribute_group x86_pmu_format_group = { |
1303 | .name = "format", | |
1304 | .attrs = NULL, | |
1305 | }; | |
1306 | ||
dda99116 | 1307 | static int __init init_hw_perf_events(void) |
b56a3802 | 1308 | { |
c1d6f42f | 1309 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1310 | int err; |
1311 | ||
cdd6c482 | 1312 | pr_info("Performance Events: "); |
1123e3ad | 1313 | |
b56a3802 JSR |
1314 | switch (boot_cpu_data.x86_vendor) { |
1315 | case X86_VENDOR_INTEL: | |
72eae04d | 1316 | err = intel_pmu_init(); |
b56a3802 | 1317 | break; |
f87ad35d | 1318 | case X86_VENDOR_AMD: |
72eae04d | 1319 | err = amd_pmu_init(); |
f87ad35d | 1320 | break; |
4138960a | 1321 | default: |
004417a6 | 1322 | return 0; |
b56a3802 | 1323 | } |
1123e3ad | 1324 | if (err != 0) { |
cdd6c482 | 1325 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1326 | return 0; |
1123e3ad | 1327 | } |
b56a3802 | 1328 | |
12558038 CG |
1329 | pmu_check_apic(); |
1330 | ||
33c6d6a7 | 1331 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1332 | if (!check_hw_exists()) |
004417a6 | 1333 | return 0; |
33c6d6a7 | 1334 | |
1123e3ad | 1335 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1336 | |
c1d6f42f PZ |
1337 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1338 | quirk->func(); | |
3c44780b | 1339 | |
a1eac7ac RR |
1340 | if (!x86_pmu.intel_ctrl) |
1341 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1342 | |
cdd6c482 | 1343 | perf_events_lapic_init(); |
9c48f1c6 | 1344 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1345 | |
63b14649 | 1346 | unconstrained = (struct event_constraint) |
948b1bb8 | 1347 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
bc1738f6 | 1348 | 0, x86_pmu.num_counters, 0); |
63b14649 | 1349 | |
0c9d42ed | 1350 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
641cc938 | 1351 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1352 | |
57c0c15b | 1353 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1354 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1355 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1356 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1357 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1358 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1359 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1360 | |
2e80a82a | 1361 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1362 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1363 | |
1364 | return 0; | |
241771ef | 1365 | } |
004417a6 | 1366 | early_initcall(init_hw_perf_events); |
621a01ea | 1367 | |
cdd6c482 | 1368 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1369 | { |
cc2ad4ba | 1370 | x86_perf_event_update(event); |
ee06094f IM |
1371 | } |
1372 | ||
4d1c52b0 LM |
1373 | /* |
1374 | * Start group events scheduling transaction | |
1375 | * Set the flag to make pmu::enable() not perform the | |
1376 | * schedulability test, it will be performed at commit time | |
1377 | */ | |
51b0fe39 | 1378 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1379 | { |
33696fc0 | 1380 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1381 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1382 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1383 | } |
1384 | ||
1385 | /* | |
1386 | * Stop group events scheduling transaction | |
1387 | * Clear the flag and pmu::enable() will perform the | |
1388 | * schedulability test. | |
1389 | */ | |
51b0fe39 | 1390 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1391 | { |
0a3aee0d | 1392 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1393 | /* |
1394 | * Truncate the collected events. | |
1395 | */ | |
0a3aee0d TH |
1396 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1397 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1398 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1399 | } |
1400 | ||
1401 | /* | |
1402 | * Commit group events scheduling transaction | |
1403 | * Perform the group schedulability test as a whole | |
1404 | * Return 0 if success | |
1405 | */ | |
51b0fe39 | 1406 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1407 | { |
1408 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1409 | int assign[X86_PMC_IDX_MAX]; | |
1410 | int n, ret; | |
1411 | ||
1412 | n = cpuc->n_events; | |
1413 | ||
1414 | if (!x86_pmu_initialized()) | |
1415 | return -EAGAIN; | |
1416 | ||
1417 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1418 | if (ret) | |
1419 | return ret; | |
1420 | ||
1421 | /* | |
1422 | * copy new assignment, now we know it is possible | |
1423 | * will be used by hw_perf_enable() | |
1424 | */ | |
1425 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1426 | ||
8d2cacbb | 1427 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1428 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1429 | return 0; |
1430 | } | |
cd8a38d3 SE |
1431 | /* |
1432 | * a fake_cpuc is used to validate event groups. Due to | |
1433 | * the extra reg logic, we need to also allocate a fake | |
1434 | * per_core and per_cpu structure. Otherwise, group events | |
1435 | * using extra reg may conflict without the kernel being | |
1436 | * able to catch this when the last event gets added to | |
1437 | * the group. | |
1438 | */ | |
1439 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1440 | { | |
1441 | kfree(cpuc->shared_regs); | |
1442 | kfree(cpuc); | |
1443 | } | |
1444 | ||
1445 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1446 | { | |
1447 | struct cpu_hw_events *cpuc; | |
1448 | int cpu = raw_smp_processor_id(); | |
1449 | ||
1450 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1451 | if (!cpuc) | |
1452 | return ERR_PTR(-ENOMEM); | |
1453 | ||
1454 | /* only needed, if we have extra_regs */ | |
1455 | if (x86_pmu.extra_regs) { | |
1456 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1457 | if (!cpuc->shared_regs) | |
1458 | goto error; | |
1459 | } | |
b430f7c4 | 1460 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1461 | return cpuc; |
1462 | error: | |
1463 | free_fake_cpuc(cpuc); | |
1464 | return ERR_PTR(-ENOMEM); | |
1465 | } | |
4d1c52b0 | 1466 | |
ca037701 PZ |
1467 | /* |
1468 | * validate that we can schedule this event | |
1469 | */ | |
1470 | static int validate_event(struct perf_event *event) | |
1471 | { | |
1472 | struct cpu_hw_events *fake_cpuc; | |
1473 | struct event_constraint *c; | |
1474 | int ret = 0; | |
1475 | ||
cd8a38d3 SE |
1476 | fake_cpuc = allocate_fake_cpuc(); |
1477 | if (IS_ERR(fake_cpuc)) | |
1478 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1479 | |
1480 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1481 | ||
1482 | if (!c || !c->weight) | |
aa2bc1ad | 1483 | ret = -EINVAL; |
ca037701 PZ |
1484 | |
1485 | if (x86_pmu.put_event_constraints) | |
1486 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1487 | ||
cd8a38d3 | 1488 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1489 | |
1490 | return ret; | |
1491 | } | |
1492 | ||
1da53e02 SE |
1493 | /* |
1494 | * validate a single event group | |
1495 | * | |
1496 | * validation include: | |
184f412c IM |
1497 | * - check events are compatible which each other |
1498 | * - events do not compete for the same counter | |
1499 | * - number of events <= number of counters | |
1da53e02 SE |
1500 | * |
1501 | * validation ensures the group can be loaded onto the | |
1502 | * PMU if it was the only group available. | |
1503 | */ | |
fe9081cc PZ |
1504 | static int validate_group(struct perf_event *event) |
1505 | { | |
1da53e02 | 1506 | struct perf_event *leader = event->group_leader; |
502568d5 | 1507 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1508 | int ret = -EINVAL, n; |
fe9081cc | 1509 | |
cd8a38d3 SE |
1510 | fake_cpuc = allocate_fake_cpuc(); |
1511 | if (IS_ERR(fake_cpuc)) | |
1512 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1513 | /* |
1514 | * the event is not yet connected with its | |
1515 | * siblings therefore we must first collect | |
1516 | * existing siblings, then add the new event | |
1517 | * before we can simulate the scheduling | |
1518 | */ | |
502568d5 | 1519 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1520 | if (n < 0) |
cd8a38d3 | 1521 | goto out; |
fe9081cc | 1522 | |
502568d5 PZ |
1523 | fake_cpuc->n_events = n; |
1524 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1525 | if (n < 0) |
cd8a38d3 | 1526 | goto out; |
fe9081cc | 1527 | |
502568d5 | 1528 | fake_cpuc->n_events = n; |
1da53e02 | 1529 | |
a072738e | 1530 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1531 | |
502568d5 | 1532 | out: |
cd8a38d3 | 1533 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1534 | return ret; |
fe9081cc PZ |
1535 | } |
1536 | ||
dda99116 | 1537 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1538 | { |
51b0fe39 | 1539 | struct pmu *tmp; |
621a01ea IM |
1540 | int err; |
1541 | ||
b0a873eb PZ |
1542 | switch (event->attr.type) { |
1543 | case PERF_TYPE_RAW: | |
1544 | case PERF_TYPE_HARDWARE: | |
1545 | case PERF_TYPE_HW_CACHE: | |
1546 | break; | |
1547 | ||
1548 | default: | |
1549 | return -ENOENT; | |
1550 | } | |
1551 | ||
1552 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1553 | if (!err) { |
8113070d SE |
1554 | /* |
1555 | * we temporarily connect event to its pmu | |
1556 | * such that validate_group() can classify | |
1557 | * it as an x86 event using is_x86_event() | |
1558 | */ | |
1559 | tmp = event->pmu; | |
1560 | event->pmu = &pmu; | |
1561 | ||
fe9081cc PZ |
1562 | if (event->group_leader != event) |
1563 | err = validate_group(event); | |
ca037701 PZ |
1564 | else |
1565 | err = validate_event(event); | |
8113070d SE |
1566 | |
1567 | event->pmu = tmp; | |
fe9081cc | 1568 | } |
a1792cda | 1569 | if (err) { |
cdd6c482 IM |
1570 | if (event->destroy) |
1571 | event->destroy(event); | |
a1792cda | 1572 | } |
621a01ea | 1573 | |
b0a873eb | 1574 | return err; |
621a01ea | 1575 | } |
d7d59fb3 | 1576 | |
fe4a3308 PZ |
1577 | static int x86_pmu_event_idx(struct perf_event *event) |
1578 | { | |
1579 | int idx = event->hw.idx; | |
1580 | ||
c7206205 PZ |
1581 | if (!x86_pmu.attr_rdpmc) |
1582 | return 0; | |
1583 | ||
15c7ad51 RR |
1584 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1585 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1586 | idx |= 1 << 30; |
1587 | } | |
1588 | ||
1589 | return idx + 1; | |
1590 | } | |
1591 | ||
0c9d42ed PZ |
1592 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1593 | struct device_attribute *attr, | |
1594 | char *buf) | |
1595 | { | |
1596 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1597 | } | |
1598 | ||
1599 | static void change_rdpmc(void *info) | |
1600 | { | |
1601 | bool enable = !!(unsigned long)info; | |
1602 | ||
1603 | if (enable) | |
1604 | set_in_cr4(X86_CR4_PCE); | |
1605 | else | |
1606 | clear_in_cr4(X86_CR4_PCE); | |
1607 | } | |
1608 | ||
1609 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1610 | struct device_attribute *attr, | |
1611 | const char *buf, size_t count) | |
1612 | { | |
e2b297fc SK |
1613 | unsigned long val; |
1614 | ssize_t ret; | |
1615 | ||
1616 | ret = kstrtoul(buf, 0, &val); | |
1617 | if (ret) | |
1618 | return ret; | |
0c9d42ed PZ |
1619 | |
1620 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1621 | x86_pmu.attr_rdpmc = !!val; | |
1622 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1623 | } | |
1624 | ||
1625 | return count; | |
1626 | } | |
1627 | ||
1628 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1629 | ||
1630 | static struct attribute *x86_pmu_attrs[] = { | |
1631 | &dev_attr_rdpmc.attr, | |
1632 | NULL, | |
1633 | }; | |
1634 | ||
1635 | static struct attribute_group x86_pmu_attr_group = { | |
1636 | .attrs = x86_pmu_attrs, | |
1637 | }; | |
1638 | ||
1639 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1640 | &x86_pmu_attr_group, | |
641cc938 | 1641 | &x86_pmu_format_group, |
0c9d42ed PZ |
1642 | NULL, |
1643 | }; | |
1644 | ||
d010b332 SE |
1645 | static void x86_pmu_flush_branch_stack(void) |
1646 | { | |
1647 | if (x86_pmu.flush_branch_stack) | |
1648 | x86_pmu.flush_branch_stack(); | |
1649 | } | |
1650 | ||
b0a873eb | 1651 | static struct pmu pmu = { |
d010b332 SE |
1652 | .pmu_enable = x86_pmu_enable, |
1653 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1654 | |
0c9d42ed PZ |
1655 | .attr_groups = x86_pmu_attr_groups, |
1656 | ||
b0a873eb | 1657 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1658 | |
d010b332 SE |
1659 | .add = x86_pmu_add, |
1660 | .del = x86_pmu_del, | |
1661 | .start = x86_pmu_start, | |
1662 | .stop = x86_pmu_stop, | |
1663 | .read = x86_pmu_read, | |
a4eaf7f1 | 1664 | |
b0a873eb PZ |
1665 | .start_txn = x86_pmu_start_txn, |
1666 | .cancel_txn = x86_pmu_cancel_txn, | |
1667 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 PZ |
1668 | |
1669 | .event_idx = x86_pmu_event_idx, | |
d010b332 | 1670 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1671 | }; |
1672 | ||
c7206205 | 1673 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1674 | { |
c7206205 PZ |
1675 | userpg->cap_usr_time = 0; |
1676 | userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc; | |
1677 | userpg->pmc_width = x86_pmu.cntval_bits; | |
1678 | ||
e3f3541c PZ |
1679 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
1680 | return; | |
1681 | ||
1682 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
1683 | return; | |
1684 | ||
c7206205 | 1685 | userpg->cap_usr_time = 1; |
e3f3541c PZ |
1686 | userpg->time_mult = this_cpu_read(cyc2ns); |
1687 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1688 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
1689 | } | |
1690 | ||
d7d59fb3 PZ |
1691 | /* |
1692 | * callchain support | |
1693 | */ | |
1694 | ||
d7d59fb3 PZ |
1695 | static int backtrace_stack(void *data, char *name) |
1696 | { | |
038e836e | 1697 | return 0; |
d7d59fb3 PZ |
1698 | } |
1699 | ||
1700 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1701 | { | |
1702 | struct perf_callchain_entry *entry = data; | |
1703 | ||
70791ce9 | 1704 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1705 | } |
1706 | ||
1707 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1708 | .stack = backtrace_stack, |
1709 | .address = backtrace_address, | |
06d65bda | 1710 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1711 | }; |
1712 | ||
56962b44 FW |
1713 | void |
1714 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1715 | { |
927c7a9e FW |
1716 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1717 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1718 | return; |
927c7a9e FW |
1719 | } |
1720 | ||
70791ce9 | 1721 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1722 | |
e8e999cf | 1723 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1724 | } |
1725 | ||
bc6ca7b3 AS |
1726 | static inline int |
1727 | valid_user_frame(const void __user *fp, unsigned long size) | |
1728 | { | |
1729 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1730 | } | |
1731 | ||
257ef9d2 | 1732 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
1733 | |
1734 | #include <asm/compat.h> | |
1735 | ||
257ef9d2 TE |
1736 | static inline int |
1737 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1738 | { |
257ef9d2 TE |
1739 | /* 32-bit process in 64-bit kernel. */ |
1740 | struct stack_frame_ia32 frame; | |
1741 | const void __user *fp; | |
74193ef0 | 1742 | |
257ef9d2 TE |
1743 | if (!test_thread_flag(TIF_IA32)) |
1744 | return 0; | |
1745 | ||
1746 | fp = compat_ptr(regs->bp); | |
1747 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1748 | unsigned long bytes; | |
1749 | frame.next_frame = 0; | |
1750 | frame.return_address = 0; | |
1751 | ||
1752 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1753 | if (bytes != sizeof(frame)) | |
1754 | break; | |
74193ef0 | 1755 | |
bc6ca7b3 AS |
1756 | if (!valid_user_frame(fp, sizeof(frame))) |
1757 | break; | |
1758 | ||
70791ce9 | 1759 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1760 | fp = compat_ptr(frame.next_frame); |
1761 | } | |
1762 | return 1; | |
d7d59fb3 | 1763 | } |
257ef9d2 TE |
1764 | #else |
1765 | static inline int | |
1766 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1767 | { | |
1768 | return 0; | |
1769 | } | |
1770 | #endif | |
d7d59fb3 | 1771 | |
56962b44 FW |
1772 | void |
1773 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1774 | { |
1775 | struct stack_frame frame; | |
1776 | const void __user *fp; | |
1777 | ||
927c7a9e FW |
1778 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1779 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1780 | return; |
927c7a9e | 1781 | } |
5a6cec3a | 1782 | |
74193ef0 | 1783 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1784 | |
70791ce9 | 1785 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1786 | |
20afc60f AV |
1787 | if (!current->mm) |
1788 | return; | |
1789 | ||
257ef9d2 TE |
1790 | if (perf_callchain_user32(regs, entry)) |
1791 | return; | |
1792 | ||
f9188e02 | 1793 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1794 | unsigned long bytes; |
038e836e | 1795 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1796 | frame.return_address = 0; |
1797 | ||
257ef9d2 TE |
1798 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1799 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1800 | break; |
1801 | ||
bc6ca7b3 AS |
1802 | if (!valid_user_frame(fp, sizeof(frame))) |
1803 | break; | |
1804 | ||
70791ce9 | 1805 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1806 | fp = frame.next_frame; |
d7d59fb3 PZ |
1807 | } |
1808 | } | |
1809 | ||
39447b38 ZY |
1810 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1811 | { | |
1812 | unsigned long ip; | |
dcf46b94 | 1813 | |
39447b38 ZY |
1814 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1815 | ip = perf_guest_cbs->get_guest_ip(); | |
1816 | else | |
1817 | ip = instruction_pointer(regs); | |
dcf46b94 | 1818 | |
39447b38 ZY |
1819 | return ip; |
1820 | } | |
1821 | ||
1822 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1823 | { | |
1824 | int misc = 0; | |
dcf46b94 | 1825 | |
39447b38 | 1826 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1827 | if (perf_guest_cbs->is_user_mode()) |
1828 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1829 | else | |
1830 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1831 | } else { | |
ce5c1fe9 | 1832 | if (!kernel_ip(regs->ip)) |
dcf46b94 ZY |
1833 | misc |= PERF_RECORD_MISC_USER; |
1834 | else | |
1835 | misc |= PERF_RECORD_MISC_KERNEL; | |
1836 | } | |
1837 | ||
39447b38 | 1838 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1839 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1840 | |
1841 | return misc; | |
1842 | } | |
b3d9468a GN |
1843 | |
1844 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
1845 | { | |
1846 | cap->version = x86_pmu.version; | |
1847 | cap->num_counters_gp = x86_pmu.num_counters; | |
1848 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
1849 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
1850 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
1851 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
1852 | cap->events_mask_len = x86_pmu.events_mask_len; | |
1853 | } | |
1854 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |