Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
ef21f683 PZ |
52 | unsigned long size, len = 0; |
53 | struct page *page; | |
54 | void *map; | |
55 | int ret; | |
56 | ||
57 | do { | |
58 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
59 | if (!ret) | |
60 | break; | |
61 | ||
62 | offset = addr & (PAGE_SIZE - 1); | |
63 | size = min(PAGE_SIZE - offset, n - len); | |
64 | ||
7a837d1b | 65 | map = kmap_atomic(page); |
ef21f683 | 66 | memcpy(to, map+offset, size); |
7a837d1b | 67 | kunmap_atomic(map); |
ef21f683 PZ |
68 | put_page(page); |
69 | ||
70 | len += size; | |
71 | to += size; | |
72 | addr += size; | |
73 | ||
74 | } while (len < n); | |
75 | ||
76 | return len; | |
77 | } | |
78 | ||
1da53e02 | 79 | struct event_constraint { |
c91e0f5d PZ |
80 | union { |
81 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 82 | u64 idxmsk64; |
c91e0f5d | 83 | }; |
b622d644 PZ |
84 | u64 code; |
85 | u64 cmask; | |
272d30be | 86 | int weight; |
1da53e02 SE |
87 | }; |
88 | ||
38331f62 SE |
89 | struct amd_nb { |
90 | int nb_id; /* NorthBridge id */ | |
91 | int refcnt; /* reference count */ | |
92 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
93 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
94 | }; | |
95 | ||
caff2bef PZ |
96 | #define MAX_LBR_ENTRIES 16 |
97 | ||
cdd6c482 | 98 | struct cpu_hw_events { |
ca037701 PZ |
99 | /* |
100 | * Generic x86 PMC bits | |
101 | */ | |
1da53e02 | 102 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 103 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 104 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 105 | int enabled; |
241771ef | 106 | |
1da53e02 SE |
107 | int n_events; |
108 | int n_added; | |
90151c35 | 109 | int n_txn; |
1da53e02 | 110 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 111 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 112 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 113 | |
4d1c52b0 LM |
114 | unsigned int group_flag; |
115 | ||
ca037701 PZ |
116 | /* |
117 | * Intel DebugStore bits | |
118 | */ | |
119 | struct debug_store *ds; | |
120 | u64 pebs_enabled; | |
121 | ||
caff2bef PZ |
122 | /* |
123 | * Intel LBR bits | |
124 | */ | |
125 | int lbr_users; | |
126 | void *lbr_context; | |
127 | struct perf_branch_stack lbr_stack; | |
128 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
129 | ||
ca037701 PZ |
130 | /* |
131 | * AMD specific bits | |
132 | */ | |
38331f62 | 133 | struct amd_nb *amd_nb; |
b690081d SE |
134 | }; |
135 | ||
fce877e3 | 136 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 137 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
138 | .code = (c), \ |
139 | .cmask = (m), \ | |
fce877e3 | 140 | .weight = (w), \ |
c91e0f5d | 141 | } |
b690081d | 142 | |
fce877e3 PZ |
143 | #define EVENT_CONSTRAINT(c, n, m) \ |
144 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
145 | ||
ca037701 PZ |
146 | /* |
147 | * Constraint on the Event code. | |
148 | */ | |
ed8777fc | 149 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 150 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 151 | |
ca037701 PZ |
152 | /* |
153 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
154 | * |
155 | * filter mask to validate fixed counter events. | |
156 | * the following filters disqualify for fixed counters: | |
157 | * - inv | |
158 | * - edge | |
159 | * - cnt-mask | |
160 | * The other filters are supported by fixed counters. | |
161 | * The any-thread option is supported starting with v3. | |
ca037701 | 162 | */ |
ed8777fc | 163 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 164 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 165 | |
ca037701 PZ |
166 | /* |
167 | * Constraint on the Event code + UMask | |
168 | */ | |
169 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
170 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
171 | ||
ed8777fc PZ |
172 | #define EVENT_CONSTRAINT_END \ |
173 | EVENT_CONSTRAINT(0, 0, 0) | |
174 | ||
175 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 176 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 177 | |
8db909a7 PZ |
178 | union perf_capabilities { |
179 | struct { | |
180 | u64 lbr_format : 6; | |
181 | u64 pebs_trap : 1; | |
182 | u64 pebs_arch_reg : 1; | |
183 | u64 pebs_format : 4; | |
184 | u64 smm_freeze : 1; | |
185 | }; | |
186 | u64 capabilities; | |
187 | }; | |
188 | ||
241771ef | 189 | /* |
5f4ec28f | 190 | * struct x86_pmu - generic x86 pmu |
241771ef | 191 | */ |
5f4ec28f | 192 | struct x86_pmu { |
ca037701 PZ |
193 | /* |
194 | * Generic x86 PMC bits | |
195 | */ | |
faa28ae0 RR |
196 | const char *name; |
197 | int version; | |
a3288106 | 198 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 199 | void (*disable_all)(void); |
11164cd4 | 200 | void (*enable_all)(int added); |
aff3d91a PZ |
201 | void (*enable)(struct perf_event *); |
202 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 203 | int (*hw_config)(struct perf_event *event); |
a072738e | 204 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
205 | unsigned eventsel; |
206 | unsigned perfctr; | |
b0f3f28e | 207 | u64 (*event_map)(int); |
169e41eb | 208 | int max_events; |
948b1bb8 RR |
209 | int num_counters; |
210 | int num_counters_fixed; | |
211 | int cntval_bits; | |
212 | u64 cntval_mask; | |
04da8a43 | 213 | int apic; |
c619b8ff | 214 | u64 max_period; |
63b14649 PZ |
215 | struct event_constraint * |
216 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
217 | struct perf_event *event); | |
218 | ||
c91e0f5d PZ |
219 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
220 | struct perf_event *event); | |
63b14649 | 221 | struct event_constraint *event_constraints; |
3c44780b | 222 | void (*quirks)(void); |
68aa00ac | 223 | int perfctr_second_write; |
3f6da390 | 224 | |
b38b24ea | 225 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
226 | void (*cpu_starting)(int cpu); |
227 | void (*cpu_dying)(int cpu); | |
228 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
229 | |
230 | /* | |
231 | * Intel Arch Perfmon v2+ | |
232 | */ | |
8db909a7 PZ |
233 | u64 intel_ctrl; |
234 | union perf_capabilities intel_cap; | |
ca037701 PZ |
235 | |
236 | /* | |
237 | * Intel DebugStore bits | |
238 | */ | |
239 | int bts, pebs; | |
6809b6ea | 240 | int bts_active, pebs_active; |
ca037701 PZ |
241 | int pebs_record_size; |
242 | void (*drain_pebs)(struct pt_regs *regs); | |
243 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
244 | |
245 | /* | |
246 | * Intel LBR | |
247 | */ | |
248 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
249 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
250 | }; |
251 | ||
4a06bd85 | 252 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 253 | |
cdd6c482 | 254 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
255 | .enabled = 1, |
256 | }; | |
241771ef | 257 | |
07088edb | 258 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 259 | |
8326f44d | 260 | /* |
dfc65094 | 261 | * Generalized hw caching related hw_event table, filled |
8326f44d | 262 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
263 | * 'not supported', -1 means 'hw_event makes no sense on |
264 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
265 | * ID. |
266 | */ | |
267 | ||
268 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
269 | ||
270 | static u64 __read_mostly hw_cache_event_ids | |
271 | [PERF_COUNT_HW_CACHE_MAX] | |
272 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
273 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
274 | ||
ee06094f | 275 | /* |
cdd6c482 IM |
276 | * Propagate event elapsed time into the generic event. |
277 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
278 | * Returns the delta events processed. |
279 | */ | |
4b7bfd0d | 280 | static u64 |
cc2ad4ba | 281 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 282 | { |
cc2ad4ba | 283 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 284 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 285 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 286 | int idx = hwc->idx; |
ec3232bd | 287 | s64 delta; |
ee06094f | 288 | |
30dd568c MM |
289 | if (idx == X86_PMC_IDX_FIXED_BTS) |
290 | return 0; | |
291 | ||
ee06094f | 292 | /* |
cdd6c482 | 293 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
294 | * |
295 | * Our tactic to handle this is to first atomically read and | |
296 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 297 | * count to the generic event atomically: |
ee06094f IM |
298 | */ |
299 | again: | |
e7850595 | 300 | prev_raw_count = local64_read(&hwc->prev_count); |
cdd6c482 | 301 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f | 302 | |
e7850595 | 303 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
304 | new_raw_count) != prev_raw_count) |
305 | goto again; | |
306 | ||
307 | /* | |
308 | * Now we have the new raw value and have updated the prev | |
309 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 310 | * (event-)time and add that to the generic event. |
ee06094f IM |
311 | * |
312 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 313 | * of the count. |
ee06094f | 314 | */ |
ec3232bd PZ |
315 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
316 | delta >>= shift; | |
ee06094f | 317 | |
e7850595 PZ |
318 | local64_add(delta, &event->count); |
319 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
320 | |
321 | return new_raw_count; | |
ee06094f IM |
322 | } |
323 | ||
cdd6c482 | 324 | static atomic_t active_events; |
4e935e47 PZ |
325 | static DEFINE_MUTEX(pmc_reserve_mutex); |
326 | ||
b27ea29c RR |
327 | #ifdef CONFIG_X86_LOCAL_APIC |
328 | ||
4e935e47 PZ |
329 | static bool reserve_pmc_hardware(void) |
330 | { | |
331 | int i; | |
332 | ||
333 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
334 | disable_lapic_nmi_watchdog(); | |
335 | ||
948b1bb8 | 336 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 337 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
338 | goto perfctr_fail; |
339 | } | |
340 | ||
948b1bb8 | 341 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 342 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
343 | goto eventsel_fail; |
344 | } | |
345 | ||
346 | return true; | |
347 | ||
348 | eventsel_fail: | |
349 | for (i--; i >= 0; i--) | |
4a06bd85 | 350 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 351 | |
948b1bb8 | 352 | i = x86_pmu.num_counters; |
4e935e47 PZ |
353 | |
354 | perfctr_fail: | |
355 | for (i--; i >= 0; i--) | |
4a06bd85 | 356 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
357 | |
358 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
359 | enable_lapic_nmi_watchdog(); | |
360 | ||
361 | return false; | |
362 | } | |
363 | ||
364 | static void release_pmc_hardware(void) | |
365 | { | |
366 | int i; | |
367 | ||
948b1bb8 | 368 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
369 | release_perfctr_nmi(x86_pmu.perfctr + i); |
370 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
371 | } |
372 | ||
373 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
374 | enable_lapic_nmi_watchdog(); | |
375 | } | |
376 | ||
b27ea29c RR |
377 | #else |
378 | ||
379 | static bool reserve_pmc_hardware(void) { return true; } | |
380 | static void release_pmc_hardware(void) {} | |
381 | ||
382 | #endif | |
383 | ||
f80c9e30 | 384 | static void reserve_ds_buffers(void); |
ca037701 | 385 | static void release_ds_buffers(void); |
30dd568c | 386 | |
cdd6c482 | 387 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 388 | { |
cdd6c482 | 389 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 390 | release_pmc_hardware(); |
ca037701 | 391 | release_ds_buffers(); |
4e935e47 PZ |
392 | mutex_unlock(&pmc_reserve_mutex); |
393 | } | |
394 | } | |
395 | ||
85cf9dba RR |
396 | static inline int x86_pmu_initialized(void) |
397 | { | |
398 | return x86_pmu.handle_irq != NULL; | |
399 | } | |
400 | ||
8326f44d | 401 | static inline int |
cdd6c482 | 402 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
403 | { |
404 | unsigned int cache_type, cache_op, cache_result; | |
405 | u64 config, val; | |
406 | ||
407 | config = attr->config; | |
408 | ||
409 | cache_type = (config >> 0) & 0xff; | |
410 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
411 | return -EINVAL; | |
412 | ||
413 | cache_op = (config >> 8) & 0xff; | |
414 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
415 | return -EINVAL; | |
416 | ||
417 | cache_result = (config >> 16) & 0xff; | |
418 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
419 | return -EINVAL; | |
420 | ||
421 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
422 | ||
423 | if (val == 0) | |
424 | return -ENOENT; | |
425 | ||
426 | if (val == -1) | |
427 | return -EINVAL; | |
428 | ||
429 | hwc->config |= val; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
c1726f34 RR |
434 | static int x86_setup_perfctr(struct perf_event *event) |
435 | { | |
436 | struct perf_event_attr *attr = &event->attr; | |
437 | struct hw_perf_event *hwc = &event->hw; | |
438 | u64 config; | |
439 | ||
440 | if (!hwc->sample_period) { | |
441 | hwc->sample_period = x86_pmu.max_period; | |
442 | hwc->last_period = hwc->sample_period; | |
e7850595 | 443 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
444 | } else { |
445 | /* | |
446 | * If we have a PMU initialized but no APIC | |
447 | * interrupts, we cannot sample hardware | |
448 | * events (user-space has to fall back and | |
449 | * sample via a hrtimer based software event): | |
450 | */ | |
451 | if (!x86_pmu.apic) | |
452 | return -EOPNOTSUPP; | |
453 | } | |
454 | ||
455 | if (attr->type == PERF_TYPE_RAW) | |
456 | return 0; | |
457 | ||
458 | if (attr->type == PERF_TYPE_HW_CACHE) | |
459 | return set_ext_hw_attr(hwc, attr); | |
460 | ||
461 | if (attr->config >= x86_pmu.max_events) | |
462 | return -EINVAL; | |
463 | ||
464 | /* | |
465 | * The generic map: | |
466 | */ | |
467 | config = x86_pmu.event_map(attr->config); | |
468 | ||
469 | if (config == 0) | |
470 | return -ENOENT; | |
471 | ||
472 | if (config == -1LL) | |
473 | return -EINVAL; | |
474 | ||
475 | /* | |
476 | * Branch tracing: | |
477 | */ | |
478 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
479 | (hwc->sample_period == 1)) { | |
480 | /* BTS is not supported by this architecture. */ | |
6809b6ea | 481 | if (!x86_pmu.bts_active) |
c1726f34 RR |
482 | return -EOPNOTSUPP; |
483 | ||
484 | /* BTS is currently only allowed for user-mode. */ | |
485 | if (!attr->exclude_kernel) | |
486 | return -EOPNOTSUPP; | |
487 | } | |
488 | ||
489 | hwc->config |= config; | |
490 | ||
491 | return 0; | |
492 | } | |
4261e0e0 | 493 | |
b4cdc5c2 | 494 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 495 | { |
ab608344 PZ |
496 | if (event->attr.precise_ip) { |
497 | int precise = 0; | |
498 | ||
499 | /* Support for constant skid */ | |
6809b6ea | 500 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
501 | precise++; |
502 | ||
5553be26 PZ |
503 | /* Support for IP fixup */ |
504 | if (x86_pmu.lbr_nr) | |
505 | precise++; | |
506 | } | |
ab608344 PZ |
507 | |
508 | if (event->attr.precise_ip > precise) | |
509 | return -EOPNOTSUPP; | |
510 | } | |
511 | ||
a072738e CG |
512 | /* |
513 | * Generate PMC IRQs: | |
514 | * (keep 'enabled' bit clear for now) | |
515 | */ | |
b4cdc5c2 | 516 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
517 | |
518 | /* | |
519 | * Count user and OS events unless requested not to | |
520 | */ | |
b4cdc5c2 PZ |
521 | if (!event->attr.exclude_user) |
522 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
523 | if (!event->attr.exclude_kernel) | |
524 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 525 | |
b4cdc5c2 PZ |
526 | if (event->attr.type == PERF_TYPE_RAW) |
527 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 528 | |
9d0fcba6 | 529 | return x86_setup_perfctr(event); |
a098f448 RR |
530 | } |
531 | ||
241771ef | 532 | /* |
0d48696f | 533 | * Setup the hardware configuration for a given attr_type |
241771ef | 534 | */ |
b0a873eb | 535 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 536 | { |
4e935e47 | 537 | int err; |
241771ef | 538 | |
85cf9dba RR |
539 | if (!x86_pmu_initialized()) |
540 | return -ENODEV; | |
241771ef | 541 | |
4e935e47 | 542 | err = 0; |
cdd6c482 | 543 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 544 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 545 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
546 | if (!reserve_pmc_hardware()) |
547 | err = -EBUSY; | |
f80c9e30 PZ |
548 | else |
549 | reserve_ds_buffers(); | |
30dd568c MM |
550 | } |
551 | if (!err) | |
cdd6c482 | 552 | atomic_inc(&active_events); |
4e935e47 PZ |
553 | mutex_unlock(&pmc_reserve_mutex); |
554 | } | |
555 | if (err) | |
556 | return err; | |
557 | ||
cdd6c482 | 558 | event->destroy = hw_perf_event_destroy; |
a1792cda | 559 | |
4261e0e0 RR |
560 | event->hw.idx = -1; |
561 | event->hw.last_cpu = -1; | |
562 | event->hw.last_tag = ~0ULL; | |
b690081d | 563 | |
9d0fcba6 | 564 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
565 | } |
566 | ||
8c48e444 | 567 | static void x86_pmu_disable_all(void) |
f87ad35d | 568 | { |
cdd6c482 | 569 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
570 | int idx; |
571 | ||
948b1bb8 | 572 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
573 | u64 val; |
574 | ||
43f6201a | 575 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 576 | continue; |
8c48e444 | 577 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 578 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 579 | continue; |
bb1165d6 | 580 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 581 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 582 | } |
f87ad35d JSR |
583 | } |
584 | ||
a4eaf7f1 | 585 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 586 | { |
1da53e02 SE |
587 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
588 | ||
85cf9dba | 589 | if (!x86_pmu_initialized()) |
9e35ad38 | 590 | return; |
1da53e02 | 591 | |
1a6e21f7 PZ |
592 | if (!cpuc->enabled) |
593 | return; | |
594 | ||
595 | cpuc->n_added = 0; | |
596 | cpuc->enabled = 0; | |
597 | barrier(); | |
1da53e02 SE |
598 | |
599 | x86_pmu.disable_all(); | |
b56a3802 | 600 | } |
241771ef | 601 | |
11164cd4 | 602 | static void x86_pmu_enable_all(int added) |
f87ad35d | 603 | { |
cdd6c482 | 604 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
605 | int idx; |
606 | ||
948b1bb8 | 607 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 608 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 609 | u64 val; |
b0f3f28e | 610 | |
43f6201a | 611 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 612 | continue; |
984b838c | 613 | |
cdd6c482 | 614 | val = event->hw.config; |
bb1165d6 | 615 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 616 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
617 | } |
618 | } | |
619 | ||
51b0fe39 | 620 | static struct pmu pmu; |
1da53e02 SE |
621 | |
622 | static inline int is_x86_event(struct perf_event *event) | |
623 | { | |
624 | return event->pmu == &pmu; | |
625 | } | |
626 | ||
627 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
628 | { | |
63b14649 | 629 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 630 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 631 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
632 | struct hw_perf_event *hwc; |
633 | ||
634 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
635 | ||
636 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
637 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
638 | constraints[i] = c; | |
1da53e02 SE |
639 | } |
640 | ||
8113070d SE |
641 | /* |
642 | * fastpath, try to reuse previous register | |
643 | */ | |
c933c1a6 | 644 | for (i = 0; i < n; i++) { |
8113070d | 645 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 646 | c = constraints[i]; |
8113070d SE |
647 | |
648 | /* never assigned */ | |
649 | if (hwc->idx == -1) | |
650 | break; | |
651 | ||
652 | /* constraint still honored */ | |
63b14649 | 653 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
654 | break; |
655 | ||
656 | /* not already used */ | |
657 | if (test_bit(hwc->idx, used_mask)) | |
658 | break; | |
659 | ||
34538ee7 | 660 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
661 | if (assign) |
662 | assign[i] = hwc->idx; | |
663 | } | |
c933c1a6 | 664 | if (i == n) |
8113070d SE |
665 | goto done; |
666 | ||
667 | /* | |
668 | * begin slow path | |
669 | */ | |
670 | ||
671 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
672 | ||
1da53e02 SE |
673 | /* |
674 | * weight = number of possible counters | |
675 | * | |
676 | * 1 = most constrained, only works on one counter | |
677 | * wmax = least constrained, works on any counter | |
678 | * | |
679 | * assign events to counters starting with most | |
680 | * constrained events. | |
681 | */ | |
948b1bb8 | 682 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
683 | |
684 | /* | |
685 | * when fixed event counters are present, | |
686 | * wmax is incremented by 1 to account | |
687 | * for one more choice | |
688 | */ | |
948b1bb8 | 689 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
690 | wmax++; |
691 | ||
8113070d | 692 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 693 | /* for each event */ |
8113070d | 694 | for (i = 0; num && i < n; i++) { |
81269a08 | 695 | c = constraints[i]; |
1da53e02 SE |
696 | hwc = &cpuc->event_list[i]->hw; |
697 | ||
272d30be | 698 | if (c->weight != w) |
1da53e02 SE |
699 | continue; |
700 | ||
984b3f57 | 701 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
702 | if (!test_bit(j, used_mask)) |
703 | break; | |
704 | } | |
705 | ||
706 | if (j == X86_PMC_IDX_MAX) | |
707 | break; | |
1da53e02 | 708 | |
34538ee7 | 709 | __set_bit(j, used_mask); |
8113070d | 710 | |
1da53e02 SE |
711 | if (assign) |
712 | assign[i] = j; | |
713 | num--; | |
714 | } | |
715 | } | |
8113070d | 716 | done: |
1da53e02 SE |
717 | /* |
718 | * scheduling failed or is just a simulation, | |
719 | * free resources if necessary | |
720 | */ | |
721 | if (!assign || num) { | |
722 | for (i = 0; i < n; i++) { | |
723 | if (x86_pmu.put_event_constraints) | |
724 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
725 | } | |
726 | } | |
727 | return num ? -ENOSPC : 0; | |
728 | } | |
729 | ||
730 | /* | |
731 | * dogrp: true if must collect siblings events (group) | |
732 | * returns total number of events and error code | |
733 | */ | |
734 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
735 | { | |
736 | struct perf_event *event; | |
737 | int n, max_count; | |
738 | ||
948b1bb8 | 739 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
740 | |
741 | /* current number of events already accepted */ | |
742 | n = cpuc->n_events; | |
743 | ||
744 | if (is_x86_event(leader)) { | |
745 | if (n >= max_count) | |
746 | return -ENOSPC; | |
747 | cpuc->event_list[n] = leader; | |
748 | n++; | |
749 | } | |
750 | if (!dogrp) | |
751 | return n; | |
752 | ||
753 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
754 | if (!is_x86_event(event) || | |
8113070d | 755 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
756 | continue; |
757 | ||
758 | if (n >= max_count) | |
759 | return -ENOSPC; | |
760 | ||
761 | cpuc->event_list[n] = event; | |
762 | n++; | |
763 | } | |
764 | return n; | |
765 | } | |
766 | ||
1da53e02 | 767 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 768 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 769 | { |
447a194b SE |
770 | struct hw_perf_event *hwc = &event->hw; |
771 | ||
772 | hwc->idx = cpuc->assign[i]; | |
773 | hwc->last_cpu = smp_processor_id(); | |
774 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
775 | |
776 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
777 | hwc->config_base = 0; | |
778 | hwc->event_base = 0; | |
779 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
780 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
781 | /* | |
782 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
783 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
784 | */ | |
785 | hwc->event_base = | |
786 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
787 | } else { | |
788 | hwc->config_base = x86_pmu.eventsel; | |
789 | hwc->event_base = x86_pmu.perfctr; | |
790 | } | |
791 | } | |
792 | ||
447a194b SE |
793 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
794 | struct cpu_hw_events *cpuc, | |
795 | int i) | |
796 | { | |
797 | return hwc->idx == cpuc->assign[i] && | |
798 | hwc->last_cpu == smp_processor_id() && | |
799 | hwc->last_tag == cpuc->tags[i]; | |
800 | } | |
801 | ||
a4eaf7f1 PZ |
802 | static void x86_pmu_start(struct perf_event *event, int flags); |
803 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 804 | |
a4eaf7f1 | 805 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 806 | { |
1da53e02 SE |
807 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
808 | struct perf_event *event; | |
809 | struct hw_perf_event *hwc; | |
11164cd4 | 810 | int i, added = cpuc->n_added; |
1da53e02 | 811 | |
85cf9dba | 812 | if (!x86_pmu_initialized()) |
2b9ff0db | 813 | return; |
1a6e21f7 PZ |
814 | |
815 | if (cpuc->enabled) | |
816 | return; | |
817 | ||
1da53e02 | 818 | if (cpuc->n_added) { |
19925ce7 | 819 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
820 | /* |
821 | * apply assignment obtained either from | |
822 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
823 | * | |
824 | * step1: save events moving to new counters | |
825 | * step2: reprogram moved events into new counters | |
826 | */ | |
19925ce7 | 827 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
828 | event = cpuc->event_list[i]; |
829 | hwc = &event->hw; | |
830 | ||
447a194b SE |
831 | /* |
832 | * we can avoid reprogramming counter if: | |
833 | * - assigned same counter as last time | |
834 | * - running on same CPU as last time | |
835 | * - no other event has used the counter since | |
836 | */ | |
837 | if (hwc->idx == -1 || | |
838 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
839 | continue; |
840 | ||
a4eaf7f1 PZ |
841 | /* |
842 | * Ensure we don't accidentally enable a stopped | |
843 | * counter simply because we rescheduled. | |
844 | */ | |
845 | if (hwc->state & PERF_HES_STOPPED) | |
846 | hwc->state |= PERF_HES_ARCH; | |
847 | ||
848 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
849 | } |
850 | ||
851 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
852 | event = cpuc->event_list[i]; |
853 | hwc = &event->hw; | |
854 | ||
45e16a68 | 855 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 856 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
857 | else if (i < n_running) |
858 | continue; | |
1da53e02 | 859 | |
a4eaf7f1 PZ |
860 | if (hwc->state & PERF_HES_ARCH) |
861 | continue; | |
862 | ||
863 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
864 | } |
865 | cpuc->n_added = 0; | |
866 | perf_events_lapic_init(); | |
867 | } | |
1a6e21f7 PZ |
868 | |
869 | cpuc->enabled = 1; | |
870 | barrier(); | |
871 | ||
11164cd4 | 872 | x86_pmu.enable_all(added); |
ee06094f | 873 | } |
ee06094f | 874 | |
31fa58af RR |
875 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
876 | u64 enable_mask) | |
b0f3f28e | 877 | { |
31fa58af | 878 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
b0f3f28e PZ |
879 | } |
880 | ||
aff3d91a | 881 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 882 | { |
aff3d91a | 883 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
884 | |
885 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
886 | } |
887 | ||
245b2e70 | 888 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 889 | |
ee06094f IM |
890 | /* |
891 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 892 | * To be called with the event disabled in hw: |
ee06094f | 893 | */ |
e4abb5d4 | 894 | static int |
07088edb | 895 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 896 | { |
07088edb | 897 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 898 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 899 | s64 period = hwc->sample_period; |
7645a24c | 900 | int ret = 0, idx = hwc->idx; |
ee06094f | 901 | |
30dd568c MM |
902 | if (idx == X86_PMC_IDX_FIXED_BTS) |
903 | return 0; | |
904 | ||
ee06094f | 905 | /* |
af901ca1 | 906 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
907 | */ |
908 | if (unlikely(left <= -period)) { | |
909 | left = period; | |
e7850595 | 910 | local64_set(&hwc->period_left, left); |
9e350de3 | 911 | hwc->last_period = period; |
e4abb5d4 | 912 | ret = 1; |
ee06094f IM |
913 | } |
914 | ||
915 | if (unlikely(left <= 0)) { | |
916 | left += period; | |
e7850595 | 917 | local64_set(&hwc->period_left, left); |
9e350de3 | 918 | hwc->last_period = period; |
e4abb5d4 | 919 | ret = 1; |
ee06094f | 920 | } |
1c80f4b5 | 921 | /* |
dfc65094 | 922 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
923 | */ |
924 | if (unlikely(left < 2)) | |
925 | left = 2; | |
241771ef | 926 | |
e4abb5d4 PZ |
927 | if (left > x86_pmu.max_period) |
928 | left = x86_pmu.max_period; | |
929 | ||
245b2e70 | 930 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
931 | |
932 | /* | |
cdd6c482 | 933 | * The hw event starts counting from this event offset, |
ee06094f IM |
934 | * mark it to be able to extra future deltas: |
935 | */ | |
e7850595 | 936 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 937 | |
68aa00ac CG |
938 | wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); |
939 | ||
940 | /* | |
941 | * Due to erratum on certan cpu we need | |
942 | * a second write to be sure the register | |
943 | * is updated properly | |
944 | */ | |
945 | if (x86_pmu.perfctr_second_write) { | |
946 | wrmsrl(hwc->event_base + idx, | |
948b1bb8 | 947 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 948 | } |
e4abb5d4 | 949 | |
cdd6c482 | 950 | perf_event_update_userpage(event); |
194002b2 | 951 | |
e4abb5d4 | 952 | return ret; |
2f18d1e8 IM |
953 | } |
954 | ||
aff3d91a | 955 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 956 | { |
cdd6c482 | 957 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 958 | if (cpuc->enabled) |
31fa58af RR |
959 | __x86_pmu_enable_event(&event->hw, |
960 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
961 | } |
962 | ||
b690081d | 963 | /* |
a4eaf7f1 | 964 | * Add a single event to the PMU. |
1da53e02 SE |
965 | * |
966 | * The event is added to the group of enabled events | |
967 | * but only if it can be scehduled with existing events. | |
fe9081cc | 968 | */ |
a4eaf7f1 | 969 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
970 | { |
971 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
972 | struct hw_perf_event *hwc; |
973 | int assign[X86_PMC_IDX_MAX]; | |
974 | int n, n0, ret; | |
fe9081cc | 975 | |
1da53e02 | 976 | hwc = &event->hw; |
fe9081cc | 977 | |
33696fc0 | 978 | perf_pmu_disable(event->pmu); |
1da53e02 | 979 | n0 = cpuc->n_events; |
24cd7f54 PZ |
980 | ret = n = collect_events(cpuc, event, false); |
981 | if (ret < 0) | |
982 | goto out; | |
53b441a5 | 983 | |
a4eaf7f1 PZ |
984 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
985 | if (!(flags & PERF_EF_START)) | |
986 | hwc->state |= PERF_HES_ARCH; | |
987 | ||
4d1c52b0 LM |
988 | /* |
989 | * If group events scheduling transaction was started, | |
990 | * skip the schedulability test here, it will be peformed | |
a4eaf7f1 | 991 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 992 | */ |
8d2cacbb | 993 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 994 | goto done_collect; |
4d1c52b0 | 995 | |
a072738e | 996 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 997 | if (ret) |
24cd7f54 | 998 | goto out; |
1da53e02 SE |
999 | /* |
1000 | * copy new assignment, now we know it is possible | |
1001 | * will be used by hw_perf_enable() | |
1002 | */ | |
1003 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1004 | |
24cd7f54 | 1005 | done_collect: |
1da53e02 | 1006 | cpuc->n_events = n; |
356e1f2e | 1007 | cpuc->n_added += n - n0; |
90151c35 | 1008 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1009 | |
24cd7f54 PZ |
1010 | ret = 0; |
1011 | out: | |
33696fc0 | 1012 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1013 | return ret; |
241771ef IM |
1014 | } |
1015 | ||
a4eaf7f1 | 1016 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1017 | { |
c08053e6 PZ |
1018 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1019 | int idx = event->hw.idx; | |
1020 | ||
a4eaf7f1 PZ |
1021 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1022 | return; | |
1023 | ||
1024 | if (WARN_ON_ONCE(idx == -1)) | |
1025 | return; | |
1026 | ||
1027 | if (flags & PERF_EF_RELOAD) { | |
1028 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1029 | x86_perf_event_set_period(event); | |
1030 | } | |
1031 | ||
1032 | event->hw.state = 0; | |
d76a0812 | 1033 | |
c08053e6 PZ |
1034 | cpuc->events[idx] = event; |
1035 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1036 | __set_bit(idx, cpuc->running); |
aff3d91a | 1037 | x86_pmu.enable(event); |
c08053e6 | 1038 | perf_event_update_userpage(event); |
a78ac325 PZ |
1039 | } |
1040 | ||
cdd6c482 | 1041 | void perf_event_print_debug(void) |
241771ef | 1042 | { |
2f18d1e8 | 1043 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1044 | u64 pebs; |
cdd6c482 | 1045 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1046 | unsigned long flags; |
1e125676 IM |
1047 | int cpu, idx; |
1048 | ||
948b1bb8 | 1049 | if (!x86_pmu.num_counters) |
1e125676 | 1050 | return; |
241771ef | 1051 | |
5bb9efe3 | 1052 | local_irq_save(flags); |
241771ef IM |
1053 | |
1054 | cpu = smp_processor_id(); | |
cdd6c482 | 1055 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1056 | |
faa28ae0 | 1057 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1058 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1059 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1060 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1061 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1062 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1063 | |
1064 | pr_info("\n"); | |
1065 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1066 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1067 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1068 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1069 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1070 | } |
7645a24c | 1071 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1072 | |
948b1bb8 | 1073 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1074 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1075 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1076 | |
245b2e70 | 1077 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1078 | |
a1ef58f4 | 1079 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1080 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1081 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1082 | cpu, idx, pmc_count); |
a1ef58f4 | 1083 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1084 | cpu, idx, prev_left); |
241771ef | 1085 | } |
948b1bb8 | 1086 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1087 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1088 | ||
a1ef58f4 | 1089 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1090 | cpu, idx, pmc_count); |
1091 | } | |
5bb9efe3 | 1092 | local_irq_restore(flags); |
241771ef IM |
1093 | } |
1094 | ||
a4eaf7f1 | 1095 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1096 | { |
d76a0812 | 1097 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1098 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1099 | |
a4eaf7f1 PZ |
1100 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1101 | x86_pmu.disable(event); | |
1102 | cpuc->events[hwc->idx] = NULL; | |
1103 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1104 | hwc->state |= PERF_HES_STOPPED; | |
1105 | } | |
30dd568c | 1106 | |
a4eaf7f1 PZ |
1107 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1108 | /* | |
1109 | * Drain the remaining delta count out of a event | |
1110 | * that we are disabling: | |
1111 | */ | |
1112 | x86_perf_event_update(event); | |
1113 | hwc->state |= PERF_HES_UPTODATE; | |
1114 | } | |
2e841873 PZ |
1115 | } |
1116 | ||
a4eaf7f1 | 1117 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1118 | { |
1119 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1120 | int i; | |
1121 | ||
90151c35 SE |
1122 | /* |
1123 | * If we're called during a txn, we don't need to do anything. | |
1124 | * The events never got scheduled and ->cancel_txn will truncate | |
1125 | * the event_list. | |
1126 | */ | |
8d2cacbb | 1127 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1128 | return; |
1129 | ||
a4eaf7f1 | 1130 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1131 | |
1da53e02 SE |
1132 | for (i = 0; i < cpuc->n_events; i++) { |
1133 | if (event == cpuc->event_list[i]) { | |
1134 | ||
1135 | if (x86_pmu.put_event_constraints) | |
1136 | x86_pmu.put_event_constraints(cpuc, event); | |
1137 | ||
1138 | while (++i < cpuc->n_events) | |
1139 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1140 | ||
1141 | --cpuc->n_events; | |
6c9687ab | 1142 | break; |
1da53e02 SE |
1143 | } |
1144 | } | |
cdd6c482 | 1145 | perf_event_update_userpage(event); |
241771ef IM |
1146 | } |
1147 | ||
8c48e444 | 1148 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1149 | { |
df1a132b | 1150 | struct perf_sample_data data; |
cdd6c482 IM |
1151 | struct cpu_hw_events *cpuc; |
1152 | struct perf_event *event; | |
11d1578f | 1153 | int idx, handled = 0; |
9029a5e3 IM |
1154 | u64 val; |
1155 | ||
dc1d628a | 1156 | perf_sample_data_init(&data, 0); |
df1a132b | 1157 | |
cdd6c482 | 1158 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1159 | |
948b1bb8 | 1160 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1161 | if (!test_bit(idx, cpuc->active_mask)) { |
1162 | /* | |
1163 | * Though we deactivated the counter some cpus | |
1164 | * might still deliver spurious interrupts still | |
1165 | * in flight. Catch them: | |
1166 | */ | |
1167 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1168 | handled++; | |
a29aa8a7 | 1169 | continue; |
63e6be6d | 1170 | } |
962bf7a6 | 1171 | |
cdd6c482 | 1172 | event = cpuc->events[idx]; |
a4016a79 | 1173 | |
cc2ad4ba | 1174 | val = x86_perf_event_update(event); |
948b1bb8 | 1175 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1176 | continue; |
962bf7a6 | 1177 | |
9e350de3 | 1178 | /* |
cdd6c482 | 1179 | * event overflow |
9e350de3 | 1180 | */ |
4177c42a | 1181 | handled++; |
cdd6c482 | 1182 | data.period = event->hw.last_period; |
9e350de3 | 1183 | |
07088edb | 1184 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1185 | continue; |
1186 | ||
cdd6c482 | 1187 | if (perf_event_overflow(event, 1, &data, regs)) |
a4eaf7f1 | 1188 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1189 | } |
962bf7a6 | 1190 | |
9e350de3 PZ |
1191 | if (handled) |
1192 | inc_irq_stat(apic_perf_irqs); | |
1193 | ||
a29aa8a7 RR |
1194 | return handled; |
1195 | } | |
39d81eab | 1196 | |
cdd6c482 | 1197 | void perf_events_lapic_init(void) |
241771ef | 1198 | { |
04da8a43 | 1199 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1200 | return; |
85cf9dba | 1201 | |
241771ef | 1202 | /* |
c323d95f | 1203 | * Always use NMI for PMU |
241771ef | 1204 | */ |
c323d95f | 1205 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1206 | } |
1207 | ||
4177c42a RR |
1208 | struct pmu_nmi_state { |
1209 | unsigned int marked; | |
1210 | int handled; | |
1211 | }; | |
1212 | ||
1213 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1214 | ||
241771ef | 1215 | static int __kprobes |
cdd6c482 | 1216 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1217 | unsigned long cmd, void *__args) |
1218 | { | |
1219 | struct die_args *args = __args; | |
4177c42a RR |
1220 | unsigned int this_nmi; |
1221 | int handled; | |
b0f3f28e | 1222 | |
cdd6c482 | 1223 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1224 | return NOTIFY_DONE; |
1225 | ||
b0f3f28e PZ |
1226 | switch (cmd) { |
1227 | case DIE_NMI: | |
1228 | case DIE_NMI_IPI: | |
1229 | break; | |
4177c42a RR |
1230 | case DIE_NMIUNKNOWN: |
1231 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1232 | if (this_nmi != __get_cpu_var(pmu_nmi).marked) | |
1233 | /* let the kernel handle the unknown nmi */ | |
1234 | return NOTIFY_DONE; | |
1235 | /* | |
1236 | * This one is a PMU back-to-back nmi. Two events | |
1237 | * trigger 'simultaneously' raising two back-to-back | |
1238 | * NMIs. If the first NMI handles both, the latter | |
1239 | * will be empty and daze the CPU. So, we drop it to | |
1240 | * avoid false-positive 'unknown nmi' messages. | |
1241 | */ | |
1242 | return NOTIFY_STOP; | |
b0f3f28e | 1243 | default: |
241771ef | 1244 | return NOTIFY_DONE; |
b0f3f28e | 1245 | } |
241771ef | 1246 | |
241771ef | 1247 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1248 | |
1249 | handled = x86_pmu.handle_irq(args->regs); | |
1250 | if (!handled) | |
1251 | return NOTIFY_DONE; | |
1252 | ||
1253 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1254 | if ((handled > 1) || | |
1255 | /* the next nmi could be a back-to-back nmi */ | |
1256 | ((__get_cpu_var(pmu_nmi).marked == this_nmi) && | |
1257 | (__get_cpu_var(pmu_nmi).handled > 1))) { | |
1258 | /* | |
1259 | * We could have two subsequent back-to-back nmis: The | |
1260 | * first handles more than one counter, the 2nd | |
1261 | * handles only one counter and the 3rd handles no | |
1262 | * counter. | |
1263 | * | |
1264 | * This is the 2nd nmi because the previous was | |
1265 | * handling more than one counter. We will mark the | |
1266 | * next (3rd) and then drop it if unhandled. | |
1267 | */ | |
1268 | __get_cpu_var(pmu_nmi).marked = this_nmi + 1; | |
1269 | __get_cpu_var(pmu_nmi).handled = handled; | |
1270 | } | |
241771ef | 1271 | |
a4016a79 | 1272 | return NOTIFY_STOP; |
241771ef IM |
1273 | } |
1274 | ||
f22f54f4 PZ |
1275 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1276 | .notifier_call = perf_event_nmi_handler, | |
1277 | .next = NULL, | |
1278 | .priority = 1 | |
1279 | }; | |
1280 | ||
63b14649 | 1281 | static struct event_constraint unconstrained; |
38331f62 | 1282 | static struct event_constraint emptyconstraint; |
63b14649 | 1283 | |
63b14649 | 1284 | static struct event_constraint * |
f22f54f4 | 1285 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1286 | { |
63b14649 | 1287 | struct event_constraint *c; |
1da53e02 | 1288 | |
1da53e02 SE |
1289 | if (x86_pmu.event_constraints) { |
1290 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1291 | if ((event->hw.config & c->cmask) == c->code) |
1292 | return c; | |
1da53e02 SE |
1293 | } |
1294 | } | |
63b14649 PZ |
1295 | |
1296 | return &unconstrained; | |
1da53e02 SE |
1297 | } |
1298 | ||
f22f54f4 PZ |
1299 | #include "perf_event_amd.c" |
1300 | #include "perf_event_p6.c" | |
a072738e | 1301 | #include "perf_event_p4.c" |
caff2bef | 1302 | #include "perf_event_intel_lbr.c" |
ca037701 | 1303 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1304 | #include "perf_event_intel.c" |
f87ad35d | 1305 | |
3f6da390 PZ |
1306 | static int __cpuinit |
1307 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1308 | { | |
1309 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1310 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1311 | |
1312 | switch (action & ~CPU_TASKS_FROZEN) { | |
1313 | case CPU_UP_PREPARE: | |
1314 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1315 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1316 | break; |
1317 | ||
1318 | case CPU_STARTING: | |
1319 | if (x86_pmu.cpu_starting) | |
1320 | x86_pmu.cpu_starting(cpu); | |
1321 | break; | |
1322 | ||
1323 | case CPU_DYING: | |
1324 | if (x86_pmu.cpu_dying) | |
1325 | x86_pmu.cpu_dying(cpu); | |
1326 | break; | |
1327 | ||
b38b24ea | 1328 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1329 | case CPU_DEAD: |
1330 | if (x86_pmu.cpu_dead) | |
1331 | x86_pmu.cpu_dead(cpu); | |
1332 | break; | |
1333 | ||
1334 | default: | |
1335 | break; | |
1336 | } | |
1337 | ||
b38b24ea | 1338 | return ret; |
3f6da390 PZ |
1339 | } |
1340 | ||
12558038 CG |
1341 | static void __init pmu_check_apic(void) |
1342 | { | |
1343 | if (cpu_has_apic) | |
1344 | return; | |
1345 | ||
1346 | x86_pmu.apic = 0; | |
1347 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1348 | pr_info("no hardware sampling interrupt available.\n"); | |
1349 | } | |
1350 | ||
cdd6c482 | 1351 | void __init init_hw_perf_events(void) |
b56a3802 | 1352 | { |
b622d644 | 1353 | struct event_constraint *c; |
72eae04d RR |
1354 | int err; |
1355 | ||
cdd6c482 | 1356 | pr_info("Performance Events: "); |
1123e3ad | 1357 | |
b56a3802 JSR |
1358 | switch (boot_cpu_data.x86_vendor) { |
1359 | case X86_VENDOR_INTEL: | |
72eae04d | 1360 | err = intel_pmu_init(); |
b56a3802 | 1361 | break; |
f87ad35d | 1362 | case X86_VENDOR_AMD: |
72eae04d | 1363 | err = amd_pmu_init(); |
f87ad35d | 1364 | break; |
4138960a RR |
1365 | default: |
1366 | return; | |
b56a3802 | 1367 | } |
1123e3ad | 1368 | if (err != 0) { |
cdd6c482 | 1369 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1370 | return; |
1123e3ad | 1371 | } |
b56a3802 | 1372 | |
12558038 CG |
1373 | pmu_check_apic(); |
1374 | ||
1123e3ad | 1375 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1376 | |
3c44780b PZ |
1377 | if (x86_pmu.quirks) |
1378 | x86_pmu.quirks(); | |
1379 | ||
948b1bb8 | 1380 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1381 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1382 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1383 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1384 | } |
948b1bb8 | 1385 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1386 | |
948b1bb8 | 1387 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1388 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1389 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1390 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1391 | } |
862a1a5f | 1392 | |
d6dc0b4e | 1393 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1394 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1395 | |
cdd6c482 IM |
1396 | perf_events_lapic_init(); |
1397 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1398 | |
63b14649 | 1399 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1400 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1401 | 0, x86_pmu.num_counters); | |
63b14649 | 1402 | |
b622d644 PZ |
1403 | if (x86_pmu.event_constraints) { |
1404 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1405 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1406 | continue; |
1407 | ||
948b1bb8 RR |
1408 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1409 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1410 | } |
1411 | } | |
1412 | ||
57c0c15b | 1413 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1414 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1415 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1416 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1417 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1418 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1419 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1420 | |
b0a873eb | 1421 | perf_pmu_register(&pmu); |
3f6da390 | 1422 | perf_cpu_notifier(x86_pmu_notifier); |
241771ef | 1423 | } |
621a01ea | 1424 | |
cdd6c482 | 1425 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1426 | { |
cc2ad4ba | 1427 | x86_perf_event_update(event); |
ee06094f IM |
1428 | } |
1429 | ||
4d1c52b0 LM |
1430 | /* |
1431 | * Start group events scheduling transaction | |
1432 | * Set the flag to make pmu::enable() not perform the | |
1433 | * schedulability test, it will be performed at commit time | |
1434 | */ | |
51b0fe39 | 1435 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 LM |
1436 | { |
1437 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1438 | ||
33696fc0 | 1439 | perf_pmu_disable(pmu); |
8d2cacbb | 1440 | cpuc->group_flag |= PERF_EVENT_TXN; |
90151c35 | 1441 | cpuc->n_txn = 0; |
4d1c52b0 LM |
1442 | } |
1443 | ||
1444 | /* | |
1445 | * Stop group events scheduling transaction | |
1446 | * Clear the flag and pmu::enable() will perform the | |
1447 | * schedulability test. | |
1448 | */ | |
51b0fe39 | 1449 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 LM |
1450 | { |
1451 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1452 | ||
8d2cacbb | 1453 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 SE |
1454 | /* |
1455 | * Truncate the collected events. | |
1456 | */ | |
1457 | cpuc->n_added -= cpuc->n_txn; | |
1458 | cpuc->n_events -= cpuc->n_txn; | |
33696fc0 | 1459 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1460 | } |
1461 | ||
1462 | /* | |
1463 | * Commit group events scheduling transaction | |
1464 | * Perform the group schedulability test as a whole | |
1465 | * Return 0 if success | |
1466 | */ | |
51b0fe39 | 1467 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1468 | { |
1469 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1470 | int assign[X86_PMC_IDX_MAX]; | |
1471 | int n, ret; | |
1472 | ||
1473 | n = cpuc->n_events; | |
1474 | ||
1475 | if (!x86_pmu_initialized()) | |
1476 | return -EAGAIN; | |
1477 | ||
1478 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1479 | if (ret) | |
1480 | return ret; | |
1481 | ||
1482 | /* | |
1483 | * copy new assignment, now we know it is possible | |
1484 | * will be used by hw_perf_enable() | |
1485 | */ | |
1486 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1487 | ||
8d2cacbb | 1488 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1489 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1490 | return 0; |
1491 | } | |
1492 | ||
ca037701 PZ |
1493 | /* |
1494 | * validate that we can schedule this event | |
1495 | */ | |
1496 | static int validate_event(struct perf_event *event) | |
1497 | { | |
1498 | struct cpu_hw_events *fake_cpuc; | |
1499 | struct event_constraint *c; | |
1500 | int ret = 0; | |
1501 | ||
1502 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1503 | if (!fake_cpuc) | |
1504 | return -ENOMEM; | |
1505 | ||
1506 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1507 | ||
1508 | if (!c || !c->weight) | |
1509 | ret = -ENOSPC; | |
1510 | ||
1511 | if (x86_pmu.put_event_constraints) | |
1512 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1513 | ||
1514 | kfree(fake_cpuc); | |
1515 | ||
1516 | return ret; | |
1517 | } | |
1518 | ||
1da53e02 SE |
1519 | /* |
1520 | * validate a single event group | |
1521 | * | |
1522 | * validation include: | |
184f412c IM |
1523 | * - check events are compatible which each other |
1524 | * - events do not compete for the same counter | |
1525 | * - number of events <= number of counters | |
1da53e02 SE |
1526 | * |
1527 | * validation ensures the group can be loaded onto the | |
1528 | * PMU if it was the only group available. | |
1529 | */ | |
fe9081cc PZ |
1530 | static int validate_group(struct perf_event *event) |
1531 | { | |
1da53e02 | 1532 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1533 | struct cpu_hw_events *fake_cpuc; |
1534 | int ret, n; | |
fe9081cc | 1535 | |
502568d5 PZ |
1536 | ret = -ENOMEM; |
1537 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1538 | if (!fake_cpuc) | |
1539 | goto out; | |
fe9081cc | 1540 | |
1da53e02 SE |
1541 | /* |
1542 | * the event is not yet connected with its | |
1543 | * siblings therefore we must first collect | |
1544 | * existing siblings, then add the new event | |
1545 | * before we can simulate the scheduling | |
1546 | */ | |
502568d5 PZ |
1547 | ret = -ENOSPC; |
1548 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1549 | if (n < 0) |
502568d5 | 1550 | goto out_free; |
fe9081cc | 1551 | |
502568d5 PZ |
1552 | fake_cpuc->n_events = n; |
1553 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1554 | if (n < 0) |
502568d5 | 1555 | goto out_free; |
fe9081cc | 1556 | |
502568d5 | 1557 | fake_cpuc->n_events = n; |
1da53e02 | 1558 | |
a072738e | 1559 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1560 | |
1561 | out_free: | |
1562 | kfree(fake_cpuc); | |
1563 | out: | |
1564 | return ret; | |
fe9081cc PZ |
1565 | } |
1566 | ||
b0a873eb | 1567 | int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1568 | { |
51b0fe39 | 1569 | struct pmu *tmp; |
621a01ea IM |
1570 | int err; |
1571 | ||
b0a873eb PZ |
1572 | switch (event->attr.type) { |
1573 | case PERF_TYPE_RAW: | |
1574 | case PERF_TYPE_HARDWARE: | |
1575 | case PERF_TYPE_HW_CACHE: | |
1576 | break; | |
1577 | ||
1578 | default: | |
1579 | return -ENOENT; | |
1580 | } | |
1581 | ||
1582 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1583 | if (!err) { |
8113070d SE |
1584 | /* |
1585 | * we temporarily connect event to its pmu | |
1586 | * such that validate_group() can classify | |
1587 | * it as an x86 event using is_x86_event() | |
1588 | */ | |
1589 | tmp = event->pmu; | |
1590 | event->pmu = &pmu; | |
1591 | ||
fe9081cc PZ |
1592 | if (event->group_leader != event) |
1593 | err = validate_group(event); | |
ca037701 PZ |
1594 | else |
1595 | err = validate_event(event); | |
8113070d SE |
1596 | |
1597 | event->pmu = tmp; | |
fe9081cc | 1598 | } |
a1792cda | 1599 | if (err) { |
cdd6c482 IM |
1600 | if (event->destroy) |
1601 | event->destroy(event); | |
a1792cda | 1602 | } |
621a01ea | 1603 | |
b0a873eb | 1604 | return err; |
621a01ea | 1605 | } |
d7d59fb3 | 1606 | |
b0a873eb | 1607 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1608 | .pmu_enable = x86_pmu_enable, |
1609 | .pmu_disable = x86_pmu_disable, | |
1610 | ||
b0a873eb | 1611 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1612 | |
1613 | .add = x86_pmu_add, | |
1614 | .del = x86_pmu_del, | |
b0a873eb PZ |
1615 | .start = x86_pmu_start, |
1616 | .stop = x86_pmu_stop, | |
1617 | .read = x86_pmu_read, | |
a4eaf7f1 | 1618 | |
b0a873eb PZ |
1619 | .start_txn = x86_pmu_start_txn, |
1620 | .cancel_txn = x86_pmu_cancel_txn, | |
1621 | .commit_txn = x86_pmu_commit_txn, | |
1622 | }; | |
1623 | ||
d7d59fb3 PZ |
1624 | /* |
1625 | * callchain support | |
1626 | */ | |
1627 | ||
d7d59fb3 PZ |
1628 | static void |
1629 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1630 | { | |
1631 | /* Ignore warnings */ | |
1632 | } | |
1633 | ||
1634 | static void backtrace_warning(void *data, char *msg) | |
1635 | { | |
1636 | /* Ignore warnings */ | |
1637 | } | |
1638 | ||
1639 | static int backtrace_stack(void *data, char *name) | |
1640 | { | |
038e836e | 1641 | return 0; |
d7d59fb3 PZ |
1642 | } |
1643 | ||
1644 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1645 | { | |
1646 | struct perf_callchain_entry *entry = data; | |
1647 | ||
70791ce9 | 1648 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1649 | } |
1650 | ||
1651 | static const struct stacktrace_ops backtrace_ops = { | |
1652 | .warning = backtrace_warning, | |
1653 | .warning_symbol = backtrace_warning_symbol, | |
1654 | .stack = backtrace_stack, | |
1655 | .address = backtrace_address, | |
06d65bda | 1656 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1657 | }; |
1658 | ||
56962b44 FW |
1659 | void |
1660 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1661 | { |
927c7a9e FW |
1662 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1663 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1664 | return; |
927c7a9e FW |
1665 | } |
1666 | ||
70791ce9 | 1667 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1668 | |
48b5ba9c | 1669 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1670 | } |
1671 | ||
257ef9d2 TE |
1672 | #ifdef CONFIG_COMPAT |
1673 | static inline int | |
1674 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1675 | { |
257ef9d2 TE |
1676 | /* 32-bit process in 64-bit kernel. */ |
1677 | struct stack_frame_ia32 frame; | |
1678 | const void __user *fp; | |
74193ef0 | 1679 | |
257ef9d2 TE |
1680 | if (!test_thread_flag(TIF_IA32)) |
1681 | return 0; | |
1682 | ||
1683 | fp = compat_ptr(regs->bp); | |
1684 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1685 | unsigned long bytes; | |
1686 | frame.next_frame = 0; | |
1687 | frame.return_address = 0; | |
1688 | ||
1689 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1690 | if (bytes != sizeof(frame)) | |
1691 | break; | |
74193ef0 | 1692 | |
257ef9d2 TE |
1693 | if (fp < compat_ptr(regs->sp)) |
1694 | break; | |
74193ef0 | 1695 | |
70791ce9 | 1696 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1697 | fp = compat_ptr(frame.next_frame); |
1698 | } | |
1699 | return 1; | |
d7d59fb3 | 1700 | } |
257ef9d2 TE |
1701 | #else |
1702 | static inline int | |
1703 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1704 | { | |
1705 | return 0; | |
1706 | } | |
1707 | #endif | |
d7d59fb3 | 1708 | |
56962b44 FW |
1709 | void |
1710 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1711 | { |
1712 | struct stack_frame frame; | |
1713 | const void __user *fp; | |
1714 | ||
927c7a9e FW |
1715 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1716 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1717 | return; |
927c7a9e | 1718 | } |
5a6cec3a | 1719 | |
74193ef0 | 1720 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1721 | |
70791ce9 | 1722 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1723 | |
257ef9d2 TE |
1724 | if (perf_callchain_user32(regs, entry)) |
1725 | return; | |
1726 | ||
f9188e02 | 1727 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1728 | unsigned long bytes; |
038e836e | 1729 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1730 | frame.return_address = 0; |
1731 | ||
257ef9d2 TE |
1732 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1733 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1734 | break; |
1735 | ||
5a6cec3a | 1736 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1737 | break; |
1738 | ||
70791ce9 | 1739 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1740 | fp = frame.next_frame; |
d7d59fb3 PZ |
1741 | } |
1742 | } | |
1743 | ||
39447b38 ZY |
1744 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1745 | { | |
1746 | unsigned long ip; | |
dcf46b94 | 1747 | |
39447b38 ZY |
1748 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1749 | ip = perf_guest_cbs->get_guest_ip(); | |
1750 | else | |
1751 | ip = instruction_pointer(regs); | |
dcf46b94 | 1752 | |
39447b38 ZY |
1753 | return ip; |
1754 | } | |
1755 | ||
1756 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1757 | { | |
1758 | int misc = 0; | |
dcf46b94 | 1759 | |
39447b38 | 1760 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1761 | if (perf_guest_cbs->is_user_mode()) |
1762 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1763 | else | |
1764 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1765 | } else { | |
1766 | if (user_mode(regs)) | |
1767 | misc |= PERF_RECORD_MISC_USER; | |
1768 | else | |
1769 | misc |= PERF_RECORD_MISC_KERNEL; | |
1770 | } | |
1771 | ||
39447b38 | 1772 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1773 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1774 | |
1775 | return misc; | |
1776 | } |