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de0428a7 KW |
1 | /* |
2 | * Performance events x86 architecture header | |
3 | * | |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian | |
11 | * | |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
15 | #include <linux/perf_event.h> | |
16 | ||
1c2ac3fd PZ |
17 | #if 0 |
18 | #undef wrmsrl | |
19 | #define wrmsrl(msr, val) \ | |
20 | do { \ | |
21 | unsigned int _msr = (msr); \ | |
22 | u64 _val = (val); \ | |
23 | trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \ | |
24 | (unsigned long long)(_val)); \ | |
25 | native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \ | |
26 | } while (0) | |
27 | #endif | |
28 | ||
de0428a7 KW |
29 | /* |
30 | * | NHM/WSM | SNB | | |
31 | * register ------------------------------- | |
32 | * | HT | no HT | HT | no HT | | |
33 | *----------------------------------------- | |
34 | * offcore | core | core | cpu | core | | |
35 | * lbr_sel | core | core | cpu | core | | |
36 | * ld_lat | cpu | core | cpu | core | | |
37 | *----------------------------------------- | |
38 | * | |
39 | * Given that there is a small number of shared regs, | |
40 | * we can pre-allocate their slot in the per-cpu | |
41 | * per-core reg tables. | |
42 | */ | |
43 | enum extra_reg_type { | |
44 | EXTRA_REG_NONE = -1, /* not used */ | |
45 | ||
46 | EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ | |
47 | EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ | |
b36817e8 | 48 | EXTRA_REG_LBR = 2, /* lbr_select */ |
f20093ee | 49 | EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ |
de0428a7 KW |
50 | |
51 | EXTRA_REG_MAX /* number of entries needed */ | |
52 | }; | |
53 | ||
54 | struct event_constraint { | |
55 | union { | |
56 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
57 | u64 idxmsk64; | |
58 | }; | |
59 | u64 code; | |
60 | u64 cmask; | |
61 | int weight; | |
bc1738f6 | 62 | int overlap; |
9fac2cf3 | 63 | int flags; |
de0428a7 | 64 | }; |
f20093ee | 65 | /* |
2f7f73a5 | 66 | * struct hw_perf_event.flags flags |
f20093ee | 67 | */ |
c857eb56 PZ |
68 | #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ |
69 | #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ | |
70 | #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ | |
71 | #define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */ | |
72 | #define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */ | |
73 | #define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */ | |
74 | #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */ | |
75 | #define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */ | |
76 | #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */ | |
cc1790cf | 77 | #define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */ |
851559e3 | 78 | #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */ |
3569c0d7 | 79 | #define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */ |
7911d3f7 | 80 | |
de0428a7 KW |
81 | |
82 | struct amd_nb { | |
83 | int nb_id; /* NorthBridge id */ | |
84 | int refcnt; /* reference count */ | |
85 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
86 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
87 | }; | |
88 | ||
89 | /* The maximal number of PEBS events: */ | |
70ab7003 | 90 | #define MAX_PEBS_EVENTS 8 |
de0428a7 | 91 | |
3569c0d7 YZ |
92 | /* |
93 | * Flags PEBS can handle without an PMI. | |
94 | * | |
9c964efa YZ |
95 | * TID can only be handled by flushing at context switch. |
96 | * | |
3569c0d7 YZ |
97 | */ |
98 | #define PEBS_FREERUNNING_FLAGS \ | |
9c964efa | 99 | (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ |
3569c0d7 YZ |
100 | PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ |
101 | PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ | |
102 | PERF_SAMPLE_TRANSACTION) | |
103 | ||
de0428a7 KW |
104 | /* |
105 | * A debug store configuration. | |
106 | * | |
107 | * We only support architectures that use 64bit fields. | |
108 | */ | |
109 | struct debug_store { | |
110 | u64 bts_buffer_base; | |
111 | u64 bts_index; | |
112 | u64 bts_absolute_maximum; | |
113 | u64 bts_interrupt_threshold; | |
114 | u64 pebs_buffer_base; | |
115 | u64 pebs_index; | |
116 | u64 pebs_absolute_maximum; | |
117 | u64 pebs_interrupt_threshold; | |
118 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; | |
119 | }; | |
120 | ||
121 | /* | |
122 | * Per register state. | |
123 | */ | |
124 | struct er_account { | |
125 | raw_spinlock_t lock; /* per-core: protect structure */ | |
126 | u64 config; /* extra MSR config */ | |
127 | u64 reg; /* extra MSR number */ | |
128 | atomic_t ref; /* reference count */ | |
129 | }; | |
130 | ||
131 | /* | |
132 | * Per core/cpu state | |
133 | * | |
134 | * Used to coordinate shared registers between HT threads or | |
135 | * among events on a single PMU. | |
136 | */ | |
137 | struct intel_shared_regs { | |
138 | struct er_account regs[EXTRA_REG_MAX]; | |
139 | int refcnt; /* per-core: #HT threads */ | |
140 | unsigned core_id; /* per-core: core id */ | |
141 | }; | |
142 | ||
6f6539ca MD |
143 | enum intel_excl_state_type { |
144 | INTEL_EXCL_UNUSED = 0, /* counter is unused */ | |
145 | INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ | |
146 | INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ | |
147 | }; | |
148 | ||
149 | struct intel_excl_states { | |
6f6539ca | 150 | enum intel_excl_state_type state[X86_PMC_IDX_MAX]; |
e979121b | 151 | bool sched_started; /* true if scheduling has started */ |
6f6539ca MD |
152 | }; |
153 | ||
154 | struct intel_excl_cntrs { | |
155 | raw_spinlock_t lock; | |
156 | ||
157 | struct intel_excl_states states[2]; | |
158 | ||
cc1790cf PZ |
159 | union { |
160 | u16 has_exclusive[2]; | |
161 | u32 exclusive_present; | |
162 | }; | |
163 | ||
6f6539ca MD |
164 | int refcnt; /* per-core: #HT threads */ |
165 | unsigned core_id; /* per-core: core id */ | |
166 | }; | |
167 | ||
9a92e16f | 168 | #define MAX_LBR_ENTRIES 32 |
de0428a7 | 169 | |
90413464 SE |
170 | enum { |
171 | X86_PERF_KFREE_SHARED = 0, | |
172 | X86_PERF_KFREE_EXCL = 1, | |
173 | X86_PERF_KFREE_MAX | |
174 | }; | |
175 | ||
de0428a7 KW |
176 | struct cpu_hw_events { |
177 | /* | |
178 | * Generic x86 PMC bits | |
179 | */ | |
180 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ | |
181 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
182 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
183 | int enabled; | |
184 | ||
c347a2f1 PZ |
185 | int n_events; /* the # of events in the below arrays */ |
186 | int n_added; /* the # last events in the below arrays; | |
187 | they've never been enabled yet */ | |
188 | int n_txn; /* the # last events in the below arrays; | |
189 | added in the current transaction */ | |
de0428a7 KW |
190 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
191 | u64 tags[X86_PMC_IDX_MAX]; | |
b371b594 | 192 | |
de0428a7 | 193 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
b371b594 PZ |
194 | struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; |
195 | ||
cc1790cf | 196 | int n_excl; /* the number of exclusive events */ |
de0428a7 KW |
197 | |
198 | unsigned int group_flag; | |
5a425294 | 199 | int is_fake; |
de0428a7 KW |
200 | |
201 | /* | |
202 | * Intel DebugStore bits | |
203 | */ | |
204 | struct debug_store *ds; | |
205 | u64 pebs_enabled; | |
206 | ||
207 | /* | |
208 | * Intel LBR bits | |
209 | */ | |
210 | int lbr_users; | |
211 | void *lbr_context; | |
212 | struct perf_branch_stack lbr_stack; | |
213 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
b36817e8 | 214 | struct er_account *lbr_sel; |
3e702ff6 | 215 | u64 br_sel; |
de0428a7 | 216 | |
144d31e6 GN |
217 | /* |
218 | * Intel host/guest exclude bits | |
219 | */ | |
220 | u64 intel_ctrl_guest_mask; | |
221 | u64 intel_ctrl_host_mask; | |
222 | struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; | |
223 | ||
2b9e344d PZ |
224 | /* |
225 | * Intel checkpoint mask | |
226 | */ | |
227 | u64 intel_cp_status; | |
228 | ||
de0428a7 KW |
229 | /* |
230 | * manage shared (per-core, per-cpu) registers | |
231 | * used on Intel NHM/WSM/SNB | |
232 | */ | |
233 | struct intel_shared_regs *shared_regs; | |
6f6539ca MD |
234 | /* |
235 | * manage exclusive counter access between hyperthread | |
236 | */ | |
237 | struct event_constraint *constraint_list; /* in enable order */ | |
238 | struct intel_excl_cntrs *excl_cntrs; | |
239 | int excl_thread_id; /* 0 or 1 */ | |
de0428a7 KW |
240 | |
241 | /* | |
242 | * AMD specific bits | |
243 | */ | |
1018faa6 JR |
244 | struct amd_nb *amd_nb; |
245 | /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ | |
246 | u64 perf_ctr_virt_mask; | |
de0428a7 | 247 | |
90413464 | 248 | void *kfree_on_online[X86_PERF_KFREE_MAX]; |
de0428a7 KW |
249 | }; |
250 | ||
9fac2cf3 | 251 | #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\ |
de0428a7 KW |
252 | { .idxmsk64 = (n) }, \ |
253 | .code = (c), \ | |
254 | .cmask = (m), \ | |
255 | .weight = (w), \ | |
bc1738f6 | 256 | .overlap = (o), \ |
9fac2cf3 | 257 | .flags = f, \ |
de0428a7 KW |
258 | } |
259 | ||
260 | #define EVENT_CONSTRAINT(c, n, m) \ | |
9fac2cf3 | 261 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) |
bc1738f6 | 262 | |
6f6539ca MD |
263 | #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ |
264 | __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ | |
265 | 0, PERF_X86_EVENT_EXCL) | |
266 | ||
bc1738f6 RR |
267 | /* |
268 | * The overlap flag marks event constraints with overlapping counter | |
269 | * masks. This is the case if the counter mask of such an event is not | |
270 | * a subset of any other counter mask of a constraint with an equal or | |
271 | * higher weight, e.g.: | |
272 | * | |
273 | * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); | |
274 | * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); | |
275 | * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); | |
276 | * | |
277 | * The event scheduler may not select the correct counter in the first | |
278 | * cycle because it needs to know which subsequent events will be | |
279 | * scheduled. It may fail to schedule the events then. So we set the | |
280 | * overlap flag for such constraints to give the scheduler a hint which | |
281 | * events to select for counter rescheduling. | |
282 | * | |
283 | * Care must be taken as the rescheduling algorithm is O(n!) which | |
284 | * will increase scheduling cycles for an over-commited system | |
285 | * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros | |
286 | * and its counter masks must be kept at a minimum. | |
287 | */ | |
288 | #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ | |
9fac2cf3 | 289 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) |
de0428a7 KW |
290 | |
291 | /* | |
292 | * Constraint on the Event code. | |
293 | */ | |
294 | #define INTEL_EVENT_CONSTRAINT(c, n) \ | |
295 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) | |
296 | ||
297 | /* | |
298 | * Constraint on the Event code + UMask + fixed-mask | |
299 | * | |
300 | * filter mask to validate fixed counter events. | |
301 | * the following filters disqualify for fixed counters: | |
302 | * - inv | |
303 | * - edge | |
304 | * - cnt-mask | |
3a632cb2 AK |
305 | * - in_tx |
306 | * - in_tx_checkpointed | |
de0428a7 KW |
307 | * The other filters are supported by fixed counters. |
308 | * The any-thread option is supported starting with v3. | |
309 | */ | |
3a632cb2 | 310 | #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) |
de0428a7 | 311 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
3a632cb2 | 312 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) |
de0428a7 KW |
313 | |
314 | /* | |
315 | * Constraint on the Event code + UMask | |
316 | */ | |
317 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ | |
318 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
319 | ||
7550ddff AK |
320 | /* Like UEVENT_CONSTRAINT, but match flags too */ |
321 | #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ | |
322 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
323 | ||
e979121b MD |
324 | #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ |
325 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ | |
326 | HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) | |
327 | ||
f20093ee | 328 | #define INTEL_PLD_CONSTRAINT(c, n) \ |
86a04461 | 329 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
f20093ee SE |
330 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) |
331 | ||
9ad64c0f | 332 | #define INTEL_PST_CONSTRAINT(c, n) \ |
86a04461 | 333 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
9ad64c0f SE |
334 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) |
335 | ||
86a04461 AK |
336 | /* Event constraint, but match on all event flags too. */ |
337 | #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ | |
338 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
339 | ||
340 | /* Check only flags, but allow all event/umask */ | |
341 | #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ | |
342 | EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) | |
343 | ||
344 | /* Check flags and event code, and set the HSW store flag */ | |
345 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
346 | __EVENT_CONSTRAINT(code, n, \ | |
347 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
348 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) | |
349 | ||
350 | /* Check flags and event code, and set the HSW load flag */ | |
351 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
b63b4b45 | 352 | __EVENT_CONSTRAINT(code, n, \ |
86a04461 AK |
353 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ |
354 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
355 | ||
b63b4b45 MD |
356 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ |
357 | __EVENT_CONSTRAINT(code, n, \ | |
358 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
359 | HWEIGHT(n), 0, \ | |
360 | PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) | |
361 | ||
86a04461 AK |
362 | /* Check flags and event code/umask, and set the HSW store flag */ |
363 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
364 | __EVENT_CONSTRAINT(code, n, \ | |
365 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
f9134f36 AK |
366 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) |
367 | ||
b63b4b45 MD |
368 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ |
369 | __EVENT_CONSTRAINT(code, n, \ | |
370 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
371 | HWEIGHT(n), 0, \ | |
372 | PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) | |
373 | ||
86a04461 AK |
374 | /* Check flags and event code/umask, and set the HSW load flag */ |
375 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
376 | __EVENT_CONSTRAINT(code, n, \ | |
377 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
378 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
379 | ||
b63b4b45 MD |
380 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ |
381 | __EVENT_CONSTRAINT(code, n, \ | |
382 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
383 | HWEIGHT(n), 0, \ | |
384 | PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) | |
385 | ||
86a04461 AK |
386 | /* Check flags and event code/umask, and set the HSW N/A flag */ |
387 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ | |
388 | __EVENT_CONSTRAINT(code, n, \ | |
389 | INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \ | |
390 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) | |
391 | ||
392 | ||
cf30d52e MD |
393 | /* |
394 | * We define the end marker as having a weight of -1 | |
395 | * to enable blacklisting of events using a counter bitmask | |
396 | * of zero and thus a weight of zero. | |
397 | * The end marker has a weight that cannot possibly be | |
398 | * obtained from counting the bits in the bitmask. | |
399 | */ | |
400 | #define EVENT_CONSTRAINT_END { .weight = -1 } | |
de0428a7 | 401 | |
cf30d52e MD |
402 | /* |
403 | * Check for end marker with weight == -1 | |
404 | */ | |
de0428a7 | 405 | #define for_each_event_constraint(e, c) \ |
cf30d52e | 406 | for ((e) = (c); (e)->weight != -1; (e)++) |
de0428a7 KW |
407 | |
408 | /* | |
409 | * Extra registers for specific events. | |
410 | * | |
411 | * Some events need large masks and require external MSRs. | |
412 | * Those extra MSRs end up being shared for all events on | |
413 | * a PMU and sometimes between PMU of sibling HT threads. | |
414 | * In either case, the kernel needs to handle conflicting | |
415 | * accesses to those extra, shared, regs. The data structure | |
416 | * to manage those registers is stored in cpu_hw_event. | |
417 | */ | |
418 | struct extra_reg { | |
419 | unsigned int event; | |
420 | unsigned int msr; | |
421 | u64 config_mask; | |
422 | u64 valid_mask; | |
423 | int idx; /* per_xxx->regs[] reg index */ | |
338b522c | 424 | bool extra_msr_access; |
de0428a7 KW |
425 | }; |
426 | ||
427 | #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ | |
338b522c KL |
428 | .event = (e), \ |
429 | .msr = (ms), \ | |
430 | .config_mask = (m), \ | |
431 | .valid_mask = (vm), \ | |
432 | .idx = EXTRA_REG_##i, \ | |
433 | .extra_msr_access = true, \ | |
de0428a7 KW |
434 | } |
435 | ||
436 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ | |
437 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) | |
438 | ||
f20093ee SE |
439 | #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ |
440 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ | |
441 | ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) | |
442 | ||
443 | #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ | |
444 | INTEL_UEVENT_EXTRA_REG(c, \ | |
445 | MSR_PEBS_LD_LAT_THRESHOLD, \ | |
446 | 0xffff, \ | |
447 | LDLAT) | |
448 | ||
de0428a7 KW |
449 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) |
450 | ||
451 | union perf_capabilities { | |
452 | struct { | |
453 | u64 lbr_format:6; | |
454 | u64 pebs_trap:1; | |
455 | u64 pebs_arch_reg:1; | |
456 | u64 pebs_format:4; | |
457 | u64 smm_freeze:1; | |
069e0c3c AK |
458 | /* |
459 | * PMU supports separate counter range for writing | |
460 | * values > 32bit. | |
461 | */ | |
462 | u64 full_width_write:1; | |
de0428a7 KW |
463 | }; |
464 | u64 capabilities; | |
465 | }; | |
466 | ||
c1d6f42f PZ |
467 | struct x86_pmu_quirk { |
468 | struct x86_pmu_quirk *next; | |
469 | void (*func)(void); | |
470 | }; | |
471 | ||
f9b4eeb8 PZ |
472 | union x86_pmu_config { |
473 | struct { | |
474 | u64 event:8, | |
475 | umask:8, | |
476 | usr:1, | |
477 | os:1, | |
478 | edge:1, | |
479 | pc:1, | |
480 | interrupt:1, | |
481 | __reserved1:1, | |
482 | en:1, | |
483 | inv:1, | |
484 | cmask:8, | |
485 | event2:4, | |
486 | __reserved2:4, | |
487 | go:1, | |
488 | ho:1; | |
489 | } bits; | |
490 | u64 value; | |
491 | }; | |
492 | ||
493 | #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value | |
494 | ||
48070342 AS |
495 | enum { |
496 | x86_lbr_exclusive_lbr, | |
8062382c | 497 | x86_lbr_exclusive_bts, |
48070342 AS |
498 | x86_lbr_exclusive_pt, |
499 | x86_lbr_exclusive_max, | |
500 | }; | |
501 | ||
de0428a7 KW |
502 | /* |
503 | * struct x86_pmu - generic x86 pmu | |
504 | */ | |
505 | struct x86_pmu { | |
506 | /* | |
507 | * Generic x86 PMC bits | |
508 | */ | |
509 | const char *name; | |
510 | int version; | |
511 | int (*handle_irq)(struct pt_regs *); | |
512 | void (*disable_all)(void); | |
513 | void (*enable_all)(int added); | |
514 | void (*enable)(struct perf_event *); | |
515 | void (*disable)(struct perf_event *); | |
516 | int (*hw_config)(struct perf_event *event); | |
517 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
518 | unsigned eventsel; | |
519 | unsigned perfctr; | |
4c1fd17a | 520 | int (*addr_offset)(int index, bool eventsel); |
0fbdad07 | 521 | int (*rdpmc_index)(int index); |
de0428a7 KW |
522 | u64 (*event_map)(int); |
523 | int max_events; | |
524 | int num_counters; | |
525 | int num_counters_fixed; | |
526 | int cntval_bits; | |
527 | u64 cntval_mask; | |
ffb871bc GN |
528 | union { |
529 | unsigned long events_maskl; | |
530 | unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; | |
531 | }; | |
532 | int events_mask_len; | |
de0428a7 KW |
533 | int apic; |
534 | u64 max_period; | |
535 | struct event_constraint * | |
536 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
79cba822 | 537 | int idx, |
de0428a7 KW |
538 | struct perf_event *event); |
539 | ||
540 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, | |
541 | struct perf_event *event); | |
c5362c0c | 542 | |
c5362c0c MD |
543 | void (*start_scheduling)(struct cpu_hw_events *cpuc); |
544 | ||
0c41e756 PZ |
545 | void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); |
546 | ||
c5362c0c MD |
547 | void (*stop_scheduling)(struct cpu_hw_events *cpuc); |
548 | ||
de0428a7 | 549 | struct event_constraint *event_constraints; |
c1d6f42f | 550 | struct x86_pmu_quirk *quirks; |
de0428a7 | 551 | int perfctr_second_write; |
72db5596 | 552 | bool late_ack; |
294fe0f5 | 553 | unsigned (*limit_period)(struct perf_event *event, unsigned l); |
de0428a7 | 554 | |
0c9d42ed PZ |
555 | /* |
556 | * sysfs attrs | |
557 | */ | |
e97df763 | 558 | int attr_rdpmc_broken; |
0c9d42ed | 559 | int attr_rdpmc; |
641cc938 | 560 | struct attribute **format_attrs; |
f20093ee | 561 | struct attribute **event_attrs; |
0c9d42ed | 562 | |
a4747393 | 563 | ssize_t (*events_sysfs_show)(char *page, u64 config); |
1a6461b1 | 564 | struct attribute **cpu_events; |
a4747393 | 565 | |
0c9d42ed PZ |
566 | /* |
567 | * CPU Hotplug hooks | |
568 | */ | |
de0428a7 KW |
569 | int (*cpu_prepare)(int cpu); |
570 | void (*cpu_starting)(int cpu); | |
571 | void (*cpu_dying)(int cpu); | |
572 | void (*cpu_dead)(int cpu); | |
c93dc84c PZ |
573 | |
574 | void (*check_microcode)(void); | |
ba532500 YZ |
575 | void (*sched_task)(struct perf_event_context *ctx, |
576 | bool sched_in); | |
de0428a7 KW |
577 | |
578 | /* | |
579 | * Intel Arch Perfmon v2+ | |
580 | */ | |
581 | u64 intel_ctrl; | |
582 | union perf_capabilities intel_cap; | |
583 | ||
584 | /* | |
585 | * Intel DebugStore bits | |
586 | */ | |
597ed953 | 587 | unsigned int bts :1, |
3e0091e2 PZ |
588 | bts_active :1, |
589 | pebs :1, | |
590 | pebs_active :1, | |
591 | pebs_broken :1; | |
de0428a7 KW |
592 | int pebs_record_size; |
593 | void (*drain_pebs)(struct pt_regs *regs); | |
594 | struct event_constraint *pebs_constraints; | |
0780c927 | 595 | void (*pebs_aliases)(struct perf_event *event); |
70ab7003 | 596 | int max_pebs_events; |
a7b58d21 | 597 | unsigned long free_running_flags; |
de0428a7 KW |
598 | |
599 | /* | |
600 | * Intel LBR | |
601 | */ | |
602 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
603 | int lbr_nr; /* hardware stack size */ | |
b36817e8 SE |
604 | u64 lbr_sel_mask; /* LBR_SELECT valid bits */ |
605 | const int *lbr_sel_map; /* lbr_select mappings */ | |
b7af41a1 | 606 | bool lbr_double_abort; /* duplicated lbr aborts */ |
de0428a7 | 607 | |
48070342 AS |
608 | /* |
609 | * Intel PT/LBR/BTS are exclusive | |
610 | */ | |
611 | atomic_t lbr_exclusive[x86_lbr_exclusive_max]; | |
612 | ||
de0428a7 KW |
613 | /* |
614 | * Extra registers for events | |
615 | */ | |
616 | struct extra_reg *extra_regs; | |
9a5e3fb5 | 617 | unsigned int flags; |
144d31e6 GN |
618 | |
619 | /* | |
620 | * Intel host/guest support (KVM) | |
621 | */ | |
622 | struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); | |
de0428a7 KW |
623 | }; |
624 | ||
e18bf526 YZ |
625 | struct x86_perf_task_context { |
626 | u64 lbr_from[MAX_LBR_ENTRIES]; | |
627 | u64 lbr_to[MAX_LBR_ENTRIES]; | |
50eab8f6 | 628 | u64 lbr_info[MAX_LBR_ENTRIES]; |
e18bf526 YZ |
629 | int lbr_callstack_users; |
630 | int lbr_stack_state; | |
631 | }; | |
632 | ||
c1d6f42f PZ |
633 | #define x86_add_quirk(func_) \ |
634 | do { \ | |
635 | static struct x86_pmu_quirk __quirk __initdata = { \ | |
636 | .func = func_, \ | |
637 | }; \ | |
638 | __quirk.next = x86_pmu.quirks; \ | |
639 | x86_pmu.quirks = &__quirk; \ | |
640 | } while (0) | |
641 | ||
9a5e3fb5 SE |
642 | /* |
643 | * x86_pmu flags | |
644 | */ | |
645 | #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ | |
646 | #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ | |
6f6539ca | 647 | #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ |
b37609c3 | 648 | #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ |
de0428a7 | 649 | |
3a54aaa0 SE |
650 | #define EVENT_VAR(_id) event_attr_##_id |
651 | #define EVENT_PTR(_id) &event_attr_##_id.attr.attr | |
652 | ||
653 | #define EVENT_ATTR(_name, _id) \ | |
654 | static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ | |
655 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
656 | .id = PERF_COUNT_HW_##_id, \ | |
657 | .event_str = NULL, \ | |
658 | }; | |
659 | ||
660 | #define EVENT_ATTR_STR(_name, v, str) \ | |
661 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
662 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
663 | .id = 0, \ | |
664 | .event_str = str, \ | |
665 | }; | |
666 | ||
de0428a7 KW |
667 | extern struct x86_pmu x86_pmu __read_mostly; |
668 | ||
e9d7f7cd YZ |
669 | static inline bool x86_pmu_has_lbr_callstack(void) |
670 | { | |
671 | return x86_pmu.lbr_sel_map && | |
672 | x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; | |
673 | } | |
674 | ||
de0428a7 KW |
675 | DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
676 | ||
677 | int x86_perf_event_set_period(struct perf_event *event); | |
678 | ||
679 | /* | |
680 | * Generalized hw caching related hw_event table, filled | |
681 | * in on a per model basis. A value of 0 means | |
682 | * 'not supported', -1 means 'hw_event makes no sense on | |
683 | * this CPU', any other value means the raw hw_event | |
684 | * ID. | |
685 | */ | |
686 | ||
687 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
688 | ||
689 | extern u64 __read_mostly hw_cache_event_ids | |
690 | [PERF_COUNT_HW_CACHE_MAX] | |
691 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
692 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
693 | extern u64 __read_mostly hw_cache_extra_regs | |
694 | [PERF_COUNT_HW_CACHE_MAX] | |
695 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
696 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
697 | ||
698 | u64 x86_perf_event_update(struct perf_event *event); | |
699 | ||
de0428a7 KW |
700 | static inline unsigned int x86_pmu_config_addr(int index) |
701 | { | |
4c1fd17a JS |
702 | return x86_pmu.eventsel + (x86_pmu.addr_offset ? |
703 | x86_pmu.addr_offset(index, true) : index); | |
de0428a7 KW |
704 | } |
705 | ||
706 | static inline unsigned int x86_pmu_event_addr(int index) | |
707 | { | |
4c1fd17a JS |
708 | return x86_pmu.perfctr + (x86_pmu.addr_offset ? |
709 | x86_pmu.addr_offset(index, false) : index); | |
de0428a7 KW |
710 | } |
711 | ||
0fbdad07 JS |
712 | static inline int x86_pmu_rdpmc_index(int index) |
713 | { | |
714 | return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; | |
715 | } | |
716 | ||
48070342 AS |
717 | int x86_add_exclusive(unsigned int what); |
718 | ||
719 | void x86_del_exclusive(unsigned int what); | |
720 | ||
6b099d9b AS |
721 | int x86_reserve_hardware(void); |
722 | ||
723 | void x86_release_hardware(void); | |
724 | ||
48070342 AS |
725 | void hw_perf_lbr_event_destroy(struct perf_event *event); |
726 | ||
de0428a7 KW |
727 | int x86_setup_perfctr(struct perf_event *event); |
728 | ||
729 | int x86_pmu_hw_config(struct perf_event *event); | |
730 | ||
731 | void x86_pmu_disable_all(void); | |
732 | ||
733 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, | |
734 | u64 enable_mask) | |
735 | { | |
1018faa6 JR |
736 | u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); |
737 | ||
de0428a7 KW |
738 | if (hwc->extra_reg.reg) |
739 | wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); | |
1018faa6 | 740 | wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); |
de0428a7 KW |
741 | } |
742 | ||
743 | void x86_pmu_enable_all(int added); | |
744 | ||
b371b594 | 745 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 746 | int wmin, int wmax, int gpmax, int *assign); |
de0428a7 KW |
747 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); |
748 | ||
749 | void x86_pmu_stop(struct perf_event *event, int flags); | |
750 | ||
751 | static inline void x86_pmu_disable_event(struct perf_event *event) | |
752 | { | |
753 | struct hw_perf_event *hwc = &event->hw; | |
754 | ||
755 | wrmsrl(hwc->config_base, hwc->config); | |
756 | } | |
757 | ||
758 | void x86_pmu_enable_event(struct perf_event *event); | |
759 | ||
760 | int x86_pmu_handle_irq(struct pt_regs *regs); | |
761 | ||
762 | extern struct event_constraint emptyconstraint; | |
763 | ||
764 | extern struct event_constraint unconstrained; | |
765 | ||
3e702ff6 SE |
766 | static inline bool kernel_ip(unsigned long ip) |
767 | { | |
768 | #ifdef CONFIG_X86_32 | |
769 | return ip > PAGE_OFFSET; | |
770 | #else | |
771 | return (long)ip < 0; | |
772 | #endif | |
773 | } | |
774 | ||
d07bdfd3 PZ |
775 | /* |
776 | * Not all PMUs provide the right context information to place the reported IP | |
777 | * into full context. Specifically segment registers are typically not | |
778 | * supplied. | |
779 | * | |
780 | * Assuming the address is a linear address (it is for IBS), we fake the CS and | |
781 | * vm86 mode using the known zero-based code segment and 'fix up' the registers | |
782 | * to reflect this. | |
783 | * | |
784 | * Intel PEBS/LBR appear to typically provide the effective address, nothing | |
785 | * much we can do about that but pray and treat it like a linear address. | |
786 | */ | |
787 | static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) | |
788 | { | |
789 | regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; | |
790 | if (regs->flags & X86_VM_MASK) | |
791 | regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); | |
792 | regs->ip = ip; | |
793 | } | |
794 | ||
0bf79d44 | 795 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); |
20550a43 | 796 | ssize_t intel_event_sysfs_show(char *page, u64 config); |
43c032fe | 797 | |
47732d88 AK |
798 | struct attribute **merge_attr(struct attribute **a, struct attribute **b); |
799 | ||
de0428a7 KW |
800 | #ifdef CONFIG_CPU_SUP_AMD |
801 | ||
802 | int amd_pmu_init(void); | |
803 | ||
804 | #else /* CONFIG_CPU_SUP_AMD */ | |
805 | ||
806 | static inline int amd_pmu_init(void) | |
807 | { | |
808 | return 0; | |
809 | } | |
810 | ||
811 | #endif /* CONFIG_CPU_SUP_AMD */ | |
812 | ||
813 | #ifdef CONFIG_CPU_SUP_INTEL | |
814 | ||
48070342 AS |
815 | static inline bool intel_pmu_has_bts(struct perf_event *event) |
816 | { | |
817 | if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && | |
818 | !event->attr.freq && event->hw.sample_period == 1) | |
819 | return true; | |
820 | ||
821 | return false; | |
822 | } | |
823 | ||
de0428a7 KW |
824 | int intel_pmu_save_and_restart(struct perf_event *event); |
825 | ||
826 | struct event_constraint * | |
79cba822 SE |
827 | x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
828 | struct perf_event *event); | |
de0428a7 KW |
829 | |
830 | struct intel_shared_regs *allocate_shared_regs(int cpu); | |
831 | ||
832 | int intel_pmu_init(void); | |
833 | ||
834 | void init_debug_store_on_cpu(int cpu); | |
835 | ||
836 | void fini_debug_store_on_cpu(int cpu); | |
837 | ||
838 | void release_ds_buffers(void); | |
839 | ||
840 | void reserve_ds_buffers(void); | |
841 | ||
842 | extern struct event_constraint bts_constraint; | |
843 | ||
844 | void intel_pmu_enable_bts(u64 config); | |
845 | ||
846 | void intel_pmu_disable_bts(void); | |
847 | ||
848 | int intel_pmu_drain_bts_buffer(void); | |
849 | ||
850 | extern struct event_constraint intel_core2_pebs_event_constraints[]; | |
851 | ||
852 | extern struct event_constraint intel_atom_pebs_event_constraints[]; | |
853 | ||
1fa64180 YZ |
854 | extern struct event_constraint intel_slm_pebs_event_constraints[]; |
855 | ||
de0428a7 KW |
856 | extern struct event_constraint intel_nehalem_pebs_event_constraints[]; |
857 | ||
858 | extern struct event_constraint intel_westmere_pebs_event_constraints[]; | |
859 | ||
860 | extern struct event_constraint intel_snb_pebs_event_constraints[]; | |
861 | ||
20a36e39 SE |
862 | extern struct event_constraint intel_ivb_pebs_event_constraints[]; |
863 | ||
3044318f AK |
864 | extern struct event_constraint intel_hsw_pebs_event_constraints[]; |
865 | ||
9a92e16f AK |
866 | extern struct event_constraint intel_skl_pebs_event_constraints[]; |
867 | ||
de0428a7 KW |
868 | struct event_constraint *intel_pebs_constraints(struct perf_event *event); |
869 | ||
870 | void intel_pmu_pebs_enable(struct perf_event *event); | |
871 | ||
872 | void intel_pmu_pebs_disable(struct perf_event *event); | |
873 | ||
874 | void intel_pmu_pebs_enable_all(void); | |
875 | ||
876 | void intel_pmu_pebs_disable_all(void); | |
877 | ||
9c964efa YZ |
878 | void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in); |
879 | ||
de0428a7 KW |
880 | void intel_ds_init(void); |
881 | ||
2a0ad3b3 YZ |
882 | void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); |
883 | ||
de0428a7 KW |
884 | void intel_pmu_lbr_reset(void); |
885 | ||
886 | void intel_pmu_lbr_enable(struct perf_event *event); | |
887 | ||
888 | void intel_pmu_lbr_disable(struct perf_event *event); | |
889 | ||
1a78d937 | 890 | void intel_pmu_lbr_enable_all(bool pmi); |
de0428a7 KW |
891 | |
892 | void intel_pmu_lbr_disable_all(void); | |
893 | ||
894 | void intel_pmu_lbr_read(void); | |
895 | ||
896 | void intel_pmu_lbr_init_core(void); | |
897 | ||
898 | void intel_pmu_lbr_init_nhm(void); | |
899 | ||
900 | void intel_pmu_lbr_init_atom(void); | |
901 | ||
c5cc2cd9 SE |
902 | void intel_pmu_lbr_init_snb(void); |
903 | ||
e9d7f7cd YZ |
904 | void intel_pmu_lbr_init_hsw(void); |
905 | ||
9a92e16f AK |
906 | void intel_pmu_lbr_init_skl(void); |
907 | ||
60ce0fbd SE |
908 | int intel_pmu_setup_lbr_filter(struct perf_event *event); |
909 | ||
52ca9ced AS |
910 | void intel_pt_interrupt(void); |
911 | ||
8062382c AS |
912 | int intel_bts_interrupt(void); |
913 | ||
914 | void intel_bts_enable_local(void); | |
915 | ||
916 | void intel_bts_disable_local(void); | |
917 | ||
de0428a7 KW |
918 | int p4_pmu_init(void); |
919 | ||
920 | int p6_pmu_init(void); | |
921 | ||
e717bf4e VW |
922 | int knc_pmu_init(void); |
923 | ||
f20093ee SE |
924 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
925 | char *page); | |
926 | ||
b37609c3 SE |
927 | static inline int is_ht_workaround_enabled(void) |
928 | { | |
929 | return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); | |
930 | } | |
47732d88 | 931 | |
de0428a7 KW |
932 | #else /* CONFIG_CPU_SUP_INTEL */ |
933 | ||
934 | static inline void reserve_ds_buffers(void) | |
935 | { | |
936 | } | |
937 | ||
938 | static inline void release_ds_buffers(void) | |
939 | { | |
940 | } | |
941 | ||
942 | static inline int intel_pmu_init(void) | |
943 | { | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static inline struct intel_shared_regs *allocate_shared_regs(int cpu) | |
948 | { | |
949 | return NULL; | |
950 | } | |
951 | ||
cc1790cf PZ |
952 | static inline int is_ht_workaround_enabled(void) |
953 | { | |
954 | return 0; | |
955 | } | |
de0428a7 | 956 | #endif /* CONFIG_CPU_SUP_INTEL */ |