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perf/x86: Add memory profiling via PEBS Load Latency
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7
KW		 15
16#include <asm/hardirq.h>
17#include <asm/apic.h>
18
19#include "perf_event.h"
a7e3ed1e 20
f22f54f4 21/*
b622d644 22 * Intel PerfMon, used on Core and later.
f22f54f4 23 */
ec75a716 24static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 25{
c3b7cdf1
PE		 26 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
27 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
28 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
29 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
30 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
31 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
32 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
33 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 34};
35
5c543e3c 36static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 37{
38 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
39 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
40 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
41 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
42 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
43 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
44 EVENT_CONSTRAINT_END
45};
46
5c543e3c 47static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 48{
b622d644
PZ		 49 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
50 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 51 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 52 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
53 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
54 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
55 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
56 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
57 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
58 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
59 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 60 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 61 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
62 EVENT_CONSTRAINT_END
63};
64
5c543e3c 65static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 66{
b622d644
PZ		 67 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
68 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 69 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 70 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
71 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
72 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
73 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
74 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
75 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
76 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
77 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
78 EVENT_CONSTRAINT_END
79};
80
5c543e3c 81static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 82{
efc9f05d 83 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 84 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 85 EVENT_EXTRA_END
86};
87
5c543e3c 88static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 89{
b622d644
PZ		 90 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
91 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 92 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 93 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
94 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
95 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 96 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 97 EVENT_CONSTRAINT_END
98};
99
5c543e3c 100static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 101{
102 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
103 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 104 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 105 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
106 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
107 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
108 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 109 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 110 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
111 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
112 EVENT_CONSTRAINT_END
113};
114
69943182
SE		 115static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
116{
117 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
118 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
119 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
120 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
121 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
122 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
123 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
124 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
126 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
127 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
129 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
130 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
131 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
132 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
133 EVENT_CONSTRAINT_END
134};
135
5c543e3c 136static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 137{
efc9f05d
SE		 138 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
139 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 140 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 141 EVENT_EXTRA_END
142};
143
0af3ac1f
AK		 144static struct event_constraint intel_v1_event_constraints[] __read_mostly =
145{
146 EVENT_CONSTRAINT_END
147};
148
5c543e3c 149static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 150{
b622d644
PZ		 151 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
152 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 153 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 154 EVENT_CONSTRAINT_END
155};
156
ee89cbc2
SE		 157static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
158 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
159 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
f20093ee 160 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 161 EVENT_EXTRA_END
162};
163
f20093ee
SE		 164EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
165EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
166
167struct attribute *nhm_events_attrs[] = {
168 EVENT_PTR(mem_ld_nhm),
169 NULL,
170};
171
172struct attribute *snb_events_attrs[] = {
173 EVENT_PTR(mem_ld_snb),
174 NULL,
175};
176
f22f54f4
PZ		 177static u64 intel_pmu_event_map(int hw_event)
178{
179 return intel_perfmon_event_map[hw_event];
180}
181
74e6543f
YZ		 182#define SNB_DMND_DATA_RD (1ULL << 0)
183#define SNB_DMND_RFO (1ULL << 1)
184#define SNB_DMND_IFETCH (1ULL << 2)
185#define SNB_DMND_WB (1ULL << 3)
186#define SNB_PF_DATA_RD (1ULL << 4)
187#define SNB_PF_RFO (1ULL << 5)
188#define SNB_PF_IFETCH (1ULL << 6)
189#define SNB_LLC_DATA_RD (1ULL << 7)
190#define SNB_LLC_RFO (1ULL << 8)
191#define SNB_LLC_IFETCH (1ULL << 9)
192#define SNB_BUS_LOCKS (1ULL << 10)
193#define SNB_STRM_ST (1ULL << 11)
194#define SNB_OTHER (1ULL << 15)
195#define SNB_RESP_ANY (1ULL << 16)
196#define SNB_NO_SUPP (1ULL << 17)
197#define SNB_LLC_HITM (1ULL << 18)
198#define SNB_LLC_HITE (1ULL << 19)
199#define SNB_LLC_HITS (1ULL << 20)
200#define SNB_LLC_HITF (1ULL << 21)
201#define SNB_LOCAL (1ULL << 22)
202#define SNB_REMOTE (0xffULL << 23)
203#define SNB_SNP_NONE (1ULL << 31)
204#define SNB_SNP_NOT_NEEDED (1ULL << 32)
205#define SNB_SNP_MISS (1ULL << 33)
206#define SNB_NO_FWD (1ULL << 34)
207#define SNB_SNP_FWD (1ULL << 35)
208#define SNB_HITM (1ULL << 36)
209#define SNB_NON_DRAM (1ULL << 37)
210
211#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
212#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
213#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
214
215#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
216 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
217 SNB_HITM)
218
219#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
220#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
221
222#define SNB_L3_ACCESS SNB_RESP_ANY
223#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
224
225static __initconst const u64 snb_hw_cache_extra_regs
226 [PERF_COUNT_HW_CACHE_MAX]
227 [PERF_COUNT_HW_CACHE_OP_MAX]
228 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
229{
230 [ C(LL ) ] = {
231 [ C(OP_READ) ] = {
232 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
233 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
234 },
235 [ C(OP_WRITE) ] = {
236 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
237 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
238 },
239 [ C(OP_PREFETCH) ] = {
240 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
241 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
242 },
243 },
244 [ C(NODE) ] = {
245 [ C(OP_READ) ] = {
246 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
247 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
248 },
249 [ C(OP_WRITE) ] = {
250 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
251 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
252 },
253 [ C(OP_PREFETCH) ] = {
254 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
255 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
256 },
257 },
258};
259
b06b3d49
LM		 260static __initconst const u64 snb_hw_cache_event_ids
261 [PERF_COUNT_HW_CACHE_MAX]
262 [PERF_COUNT_HW_CACHE_OP_MAX]
263 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
264{
265 [ C(L1D) ] = {
266 [ C(OP_READ) ] = {
267 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
268 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
269 },
270 [ C(OP_WRITE) ] = {
271 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
272 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
273 },
274 [ C(OP_PREFETCH) ] = {
275 [ C(RESULT_ACCESS) ] = 0x0,
276 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
277 },
278 },
279 [ C(L1I ) ] = {
280 [ C(OP_READ) ] = {
281 [ C(RESULT_ACCESS) ] = 0x0,
282 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
283 },
284 [ C(OP_WRITE) ] = {
285 [ C(RESULT_ACCESS) ] = -1,
286 [ C(RESULT_MISS) ] = -1,
287 },
288 [ C(OP_PREFETCH) ] = {
289 [ C(RESULT_ACCESS) ] = 0x0,
290 [ C(RESULT_MISS) ] = 0x0,
291 },
292 },
293 [ C(LL ) ] = {
b06b3d49 294 [ C(OP_READ) ] = {
63b6a675 295 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 296 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 297 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
298 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 299 },
300 [ C(OP_WRITE) ] = {
63b6a675 301 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 302 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 303 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
304 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 305 },
306 [ C(OP_PREFETCH) ] = {
63b6a675 307 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 308 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 309 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
310 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 311 },
312 },
313 [ C(DTLB) ] = {
314 [ C(OP_READ) ] = {
315 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
316 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
317 },
318 [ C(OP_WRITE) ] = {
319 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
320 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
321 },
322 [ C(OP_PREFETCH) ] = {
323 [ C(RESULT_ACCESS) ] = 0x0,
324 [ C(RESULT_MISS) ] = 0x0,
325 },
326 },
327 [ C(ITLB) ] = {
328 [ C(OP_READ) ] = {
329 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
330 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
331 },
332 [ C(OP_WRITE) ] = {
333 [ C(RESULT_ACCESS) ] = -1,
334 [ C(RESULT_MISS) ] = -1,
335 },
336 [ C(OP_PREFETCH) ] = {
337 [ C(RESULT_ACCESS) ] = -1,
338 [ C(RESULT_MISS) ] = -1,
339 },
340 },
341 [ C(BPU ) ] = {
342 [ C(OP_READ) ] = {
343 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
344 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
345 },
346 [ C(OP_WRITE) ] = {
347 [ C(RESULT_ACCESS) ] = -1,
348 [ C(RESULT_MISS) ] = -1,
349 },
350 [ C(OP_PREFETCH) ] = {
351 [ C(RESULT_ACCESS) ] = -1,
352 [ C(RESULT_MISS) ] = -1,
353 },
354 },
89d6c0b5
PZ		 355 [ C(NODE) ] = {
356 [ C(OP_READ) ] = {
74e6543f
YZ		 357 [ C(RESULT_ACCESS) ] = 0x01b7,
358 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 359 },
360 [ C(OP_WRITE) ] = {
74e6543f
YZ		 361 [ C(RESULT_ACCESS) ] = 0x01b7,
362 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 363 },
364 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 365 [ C(RESULT_ACCESS) ] = 0x01b7,
366 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 367 },
368 },
369
b06b3d49
LM		 370};
371
caaa8be3 372static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 373 [PERF_COUNT_HW_CACHE_MAX]
374 [PERF_COUNT_HW_CACHE_OP_MAX]
375 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
376{
377 [ C(L1D) ] = {
378 [ C(OP_READ) ] = {
379 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
380 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
381 },
382 [ C(OP_WRITE) ] = {
383 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
384 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
385 },
386 [ C(OP_PREFETCH) ] = {
387 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
388 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
389 },
390 },
391 [ C(L1I ) ] = {
392 [ C(OP_READ) ] = {
393 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
394 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
395 },
396 [ C(OP_WRITE) ] = {
397 [ C(RESULT_ACCESS) ] = -1,
398 [ C(RESULT_MISS) ] = -1,
399 },
400 [ C(OP_PREFETCH) ] = {
401 [ C(RESULT_ACCESS) ] = 0x0,
402 [ C(RESULT_MISS) ] = 0x0,
403 },
404 },
405 [ C(LL ) ] = {
406 [ C(OP_READ) ] = {
63b6a675 407 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 408 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 409 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
410 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 411 },
e994d7d2
AK		 412 /*
413 * Use RFO, not WRITEBACK, because a write miss would typically occur
414 * on RFO.
415 */
f22f54f4 416 [ C(OP_WRITE) ] = {
63b6a675
PZ		 417 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
418 [ C(RESULT_ACCESS) ] = 0x01b7,
419 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 420 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 421 },
422 [ C(OP_PREFETCH) ] = {
63b6a675 423 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 424 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 425 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
426 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 427 },
428 },
429 [ C(DTLB) ] = {
430 [ C(OP_READ) ] = {
431 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
432 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
433 },
434 [ C(OP_WRITE) ] = {
435 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
436 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
437 },
438 [ C(OP_PREFETCH) ] = {
439 [ C(RESULT_ACCESS) ] = 0x0,
440 [ C(RESULT_MISS) ] = 0x0,
441 },
442 },
443 [ C(ITLB) ] = {
444 [ C(OP_READ) ] = {
445 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
446 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
447 },
448 [ C(OP_WRITE) ] = {
449 [ C(RESULT_ACCESS) ] = -1,
450 [ C(RESULT_MISS) ] = -1,
451 },
452 [ C(OP_PREFETCH) ] = {
453 [ C(RESULT_ACCESS) ] = -1,
454 [ C(RESULT_MISS) ] = -1,
455 },
456 },
457 [ C(BPU ) ] = {
458 [ C(OP_READ) ] = {
459 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
460 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
461 },
462 [ C(OP_WRITE) ] = {
463 [ C(RESULT_ACCESS) ] = -1,
464 [ C(RESULT_MISS) ] = -1,
465 },
466 [ C(OP_PREFETCH) ] = {
467 [ C(RESULT_ACCESS) ] = -1,
468 [ C(RESULT_MISS) ] = -1,
469 },
470 },
89d6c0b5
PZ		 471 [ C(NODE) ] = {
472 [ C(OP_READ) ] = {
473 [ C(RESULT_ACCESS) ] = 0x01b7,
474 [ C(RESULT_MISS) ] = 0x01b7,
475 },
476 [ C(OP_WRITE) ] = {
477 [ C(RESULT_ACCESS) ] = 0x01b7,
478 [ C(RESULT_MISS) ] = 0x01b7,
479 },
480 [ C(OP_PREFETCH) ] = {
481 [ C(RESULT_ACCESS) ] = 0x01b7,
482 [ C(RESULT_MISS) ] = 0x01b7,
483 },
484 },
f22f54f4
PZ		 485};
486
e994d7d2 487/*
63b6a675
PZ		 488 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
489 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 490 */
491
63b6a675
PZ		 492#define NHM_DMND_DATA_RD (1 << 0)
493#define NHM_DMND_RFO (1 << 1)
494#define NHM_DMND_IFETCH (1 << 2)
495#define NHM_DMND_WB (1 << 3)
496#define NHM_PF_DATA_RD (1 << 4)
497#define NHM_PF_DATA_RFO (1 << 5)
498#define NHM_PF_IFETCH (1 << 6)
499#define NHM_OFFCORE_OTHER (1 << 7)
500#define NHM_UNCORE_HIT (1 << 8)
501#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
502#define NHM_OTHER_CORE_HITM (1 << 10)
503 /* reserved */
504#define NHM_REMOTE_CACHE_FWD (1 << 12)
505#define NHM_REMOTE_DRAM (1 << 13)
506#define NHM_LOCAL_DRAM (1 << 14)
507#define NHM_NON_DRAM (1 << 15)
508
87e24f4b
PZ		 509#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
510#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 511
512#define NHM_DMND_READ (NHM_DMND_DATA_RD)
513#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
514#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
515
516#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 517#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 518#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 519
520static __initconst const u64 nehalem_hw_cache_extra_regs
521 [PERF_COUNT_HW_CACHE_MAX]
522 [PERF_COUNT_HW_CACHE_OP_MAX]
523 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
524{
525 [ C(LL ) ] = {
526 [ C(OP_READ) ] = {
63b6a675
PZ		 527 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
528 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 529 },
530 [ C(OP_WRITE) ] = {
63b6a675
PZ		 531 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
532 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 533 },
534 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 535 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
536 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 537 },
89d6c0b5
PZ		 538 },
539 [ C(NODE) ] = {
540 [ C(OP_READ) ] = {
87e24f4b
PZ		 541 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
542 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 543 },
544 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 545 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
546 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 547 },
548 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 549 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
550 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 551 },
552 },
e994d7d2
AK		 553};
554
caaa8be3 555static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 556 [PERF_COUNT_HW_CACHE_MAX]
557 [PERF_COUNT_HW_CACHE_OP_MAX]
558 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
559{
560 [ C(L1D) ] = {
561 [ C(OP_READ) ] = {
f4929bd3
PZ		 562 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
563 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 564 },
565 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 566 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
567 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 568 },
569 [ C(OP_PREFETCH) ] = {
570 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
571 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
572 },
573 },
574 [ C(L1I ) ] = {
575 [ C(OP_READ) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
577 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
578 },
579 [ C(OP_WRITE) ] = {
580 [ C(RESULT_ACCESS) ] = -1,
581 [ C(RESULT_MISS) ] = -1,
582 },
583 [ C(OP_PREFETCH) ] = {
584 [ C(RESULT_ACCESS) ] = 0x0,
585 [ C(RESULT_MISS) ] = 0x0,
586 },
587 },
588 [ C(LL ) ] = {
589 [ C(OP_READ) ] = {
e994d7d2
AK		 590 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
591 [ C(RESULT_ACCESS) ] = 0x01b7,
592 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
593 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 594 },
e994d7d2
AK		 595 /*
596 * Use RFO, not WRITEBACK, because a write miss would typically occur
597 * on RFO.
598 */
f22f54f4 599 [ C(OP_WRITE) ] = {
e994d7d2
AK		 600 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
601 [ C(RESULT_ACCESS) ] = 0x01b7,
602 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
603 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 604 },
605 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 606 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
607 [ C(RESULT_ACCESS) ] = 0x01b7,
608 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
609 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 610 },
611 },
612 [ C(DTLB) ] = {
613 [ C(OP_READ) ] = {
614 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
615 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
616 },
617 [ C(OP_WRITE) ] = {
618 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
619 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
620 },
621 [ C(OP_PREFETCH) ] = {
622 [ C(RESULT_ACCESS) ] = 0x0,
623 [ C(RESULT_MISS) ] = 0x0,
624 },
625 },
626 [ C(ITLB) ] = {
627 [ C(OP_READ) ] = {
628 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
629 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
630 },
631 [ C(OP_WRITE) ] = {
632 [ C(RESULT_ACCESS) ] = -1,
633 [ C(RESULT_MISS) ] = -1,
634 },
635 [ C(OP_PREFETCH) ] = {
636 [ C(RESULT_ACCESS) ] = -1,
637 [ C(RESULT_MISS) ] = -1,
638 },
639 },
640 [ C(BPU ) ] = {
641 [ C(OP_READ) ] = {
642 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
643 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
644 },
645 [ C(OP_WRITE) ] = {
646 [ C(RESULT_ACCESS) ] = -1,
647 [ C(RESULT_MISS) ] = -1,
648 },
649 [ C(OP_PREFETCH) ] = {
650 [ C(RESULT_ACCESS) ] = -1,
651 [ C(RESULT_MISS) ] = -1,
652 },
653 },
89d6c0b5
PZ		 654 [ C(NODE) ] = {
655 [ C(OP_READ) ] = {
656 [ C(RESULT_ACCESS) ] = 0x01b7,
657 [ C(RESULT_MISS) ] = 0x01b7,
658 },
659 [ C(OP_WRITE) ] = {
660 [ C(RESULT_ACCESS) ] = 0x01b7,
661 [ C(RESULT_MISS) ] = 0x01b7,
662 },
663 [ C(OP_PREFETCH) ] = {
664 [ C(RESULT_ACCESS) ] = 0x01b7,
665 [ C(RESULT_MISS) ] = 0x01b7,
666 },
667 },
f22f54f4
PZ		 668};
669
caaa8be3 670static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 671 [PERF_COUNT_HW_CACHE_MAX]
672 [PERF_COUNT_HW_CACHE_OP_MAX]
673 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
674{
675 [ C(L1D) ] = {
676 [ C(OP_READ) ] = {
677 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
678 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
679 },
680 [ C(OP_WRITE) ] = {
681 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
682 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
683 },
684 [ C(OP_PREFETCH) ] = {
685 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
686 [ C(RESULT_MISS) ] = 0,
687 },
688 },
689 [ C(L1I ) ] = {
690 [ C(OP_READ) ] = {
691 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
692 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
693 },
694 [ C(OP_WRITE) ] = {
695 [ C(RESULT_ACCESS) ] = -1,
696 [ C(RESULT_MISS) ] = -1,
697 },
698 [ C(OP_PREFETCH) ] = {
699 [ C(RESULT_ACCESS) ] = 0,
700 [ C(RESULT_MISS) ] = 0,
701 },
702 },
703 [ C(LL ) ] = {
704 [ C(OP_READ) ] = {
705 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
706 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
707 },
708 [ C(OP_WRITE) ] = {
709 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
710 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
711 },
712 [ C(OP_PREFETCH) ] = {
713 [ C(RESULT_ACCESS) ] = 0,
714 [ C(RESULT_MISS) ] = 0,
715 },
716 },
717 [ C(DTLB) ] = {
718 [ C(OP_READ) ] = {
719 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
720 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
721 },
722 [ C(OP_WRITE) ] = {
723 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
724 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
725 },
726 [ C(OP_PREFETCH) ] = {
727 [ C(RESULT_ACCESS) ] = 0,
728 [ C(RESULT_MISS) ] = 0,
729 },
730 },
731 [ C(ITLB) ] = {
732 [ C(OP_READ) ] = {
733 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
734 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
735 },
736 [ C(OP_WRITE) ] = {
737 [ C(RESULT_ACCESS) ] = -1,
738 [ C(RESULT_MISS) ] = -1,
739 },
740 [ C(OP_PREFETCH) ] = {
741 [ C(RESULT_ACCESS) ] = -1,
742 [ C(RESULT_MISS) ] = -1,
743 },
744 },
745 [ C(BPU ) ] = {
746 [ C(OP_READ) ] = {
747 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
748 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
749 },
750 [ C(OP_WRITE) ] = {
751 [ C(RESULT_ACCESS) ] = -1,
752 [ C(RESULT_MISS) ] = -1,
753 },
754 [ C(OP_PREFETCH) ] = {
755 [ C(RESULT_ACCESS) ] = -1,
756 [ C(RESULT_MISS) ] = -1,
757 },
758 },
759};
760
caaa8be3 761static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 762 [PERF_COUNT_HW_CACHE_MAX]
763 [PERF_COUNT_HW_CACHE_OP_MAX]
764 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
765{
766 [ C(L1D) ] = {
767 [ C(OP_READ) ] = {
768 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
769 [ C(RESULT_MISS) ] = 0,
770 },
771 [ C(OP_WRITE) ] = {
772 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
773 [ C(RESULT_MISS) ] = 0,
774 },
775 [ C(OP_PREFETCH) ] = {
776 [ C(RESULT_ACCESS) ] = 0x0,
777 [ C(RESULT_MISS) ] = 0,
778 },
779 },
780 [ C(L1I ) ] = {
781 [ C(OP_READ) ] = {
782 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
783 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
784 },
785 [ C(OP_WRITE) ] = {
786 [ C(RESULT_ACCESS) ] = -1,
787 [ C(RESULT_MISS) ] = -1,
788 },
789 [ C(OP_PREFETCH) ] = {
790 [ C(RESULT_ACCESS) ] = 0,
791 [ C(RESULT_MISS) ] = 0,
792 },
793 },
794 [ C(LL ) ] = {
795 [ C(OP_READ) ] = {
796 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
797 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
798 },
799 [ C(OP_WRITE) ] = {
800 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
801 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
802 },
803 [ C(OP_PREFETCH) ] = {
804 [ C(RESULT_ACCESS) ] = 0,
805 [ C(RESULT_MISS) ] = 0,
806 },
807 },
808 [ C(DTLB) ] = {
809 [ C(OP_READ) ] = {
810 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
811 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
812 },
813 [ C(OP_WRITE) ] = {
814 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
815 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
816 },
817 [ C(OP_PREFETCH) ] = {
818 [ C(RESULT_ACCESS) ] = 0,
819 [ C(RESULT_MISS) ] = 0,
820 },
821 },
822 [ C(ITLB) ] = {
823 [ C(OP_READ) ] = {
824 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
825 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
826 },
827 [ C(OP_WRITE) ] = {
828 [ C(RESULT_ACCESS) ] = -1,
829 [ C(RESULT_MISS) ] = -1,
830 },
831 [ C(OP_PREFETCH) ] = {
832 [ C(RESULT_ACCESS) ] = -1,
833 [ C(RESULT_MISS) ] = -1,
834 },
835 },
836 [ C(BPU ) ] = {
837 [ C(OP_READ) ] = {
838 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
839 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
840 },
841 [ C(OP_WRITE) ] = {
842 [ C(RESULT_ACCESS) ] = -1,
843 [ C(RESULT_MISS) ] = -1,
844 },
845 [ C(OP_PREFETCH) ] = {
846 [ C(RESULT_ACCESS) ] = -1,
847 [ C(RESULT_MISS) ] = -1,
848 },
849 },
850};
851
60ce0fbd
SE		 852static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
853{
854 /* user explicitly requested branch sampling */
855 if (has_branch_stack(event))
856 return true;
857
858 /* implicit branch sampling to correct PEBS skid */
859 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
860 return true;
861
862 return false;
863}
864
f22f54f4
PZ		 865static void intel_pmu_disable_all(void)
866{
867 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
868
869 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
870
15c7ad51 871 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 872 intel_pmu_disable_bts();
ca037701
PZ		 873
874 intel_pmu_pebs_disable_all();
caff2bef 875 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 876}
877
11164cd4 878static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 879{
880 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
881
d329527e
PZ		 882 intel_pmu_pebs_enable_all();
883 intel_pmu_lbr_enable_all();
144d31e6
GN		 884 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
885 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 886
15c7ad51 887 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 888 struct perf_event *event =
15c7ad51 889 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 890
891 if (WARN_ON_ONCE(!event))
892 return;
893
894 intel_pmu_enable_bts(event->hw.config);
895 }
896}
897
11164cd4
PZ		 898/*
899 * Workaround for:
900 * Intel Errata AAK100 (model 26)
901 * Intel Errata AAP53 (model 30)
40b91cd1 902 * Intel Errata BD53 (model 44)
11164cd4 903 *
351af072
ZY		 904 * The official story:
905 * These chips need to be 'reset' when adding counters by programming the
906 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
907 * in sequence on the same PMC or on different PMCs.
908 *
909 * In practise it appears some of these events do in fact count, and
910 * we need to programm all 4 events.
11164cd4 911 */
351af072 912static void intel_pmu_nhm_workaround(void)
11164cd4 913{
351af072
ZY		 914 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
915 static const unsigned long nhm_magic[4] = {
916 0x4300B5,
917 0x4300D2,
918 0x4300B1,
919 0x4300B1
920 };
921 struct perf_event *event;
922 int i;
11164cd4 923
351af072
ZY		 924 /*
925 * The Errata requires below steps:
926 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
927 * 2) Configure 4 PERFEVTSELx with the magic events and clear
928 * the corresponding PMCx;
929 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
930 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
931 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
932 */
11164cd4 933
351af072
ZY		 934 /*
935 * The real steps we choose are a little different from above.
936 * A) To reduce MSR operations, we don't run step 1) as they
937 * are already cleared before this function is called;
938 * B) Call x86_perf_event_update to save PMCx before configuring
939 * PERFEVTSELx with magic number;
940 * C) With step 5), we do clear only when the PERFEVTSELx is
941 * not used currently.
942 * D) Call x86_perf_event_set_period to restore PMCx;
943 */
11164cd4 944
351af072
ZY		 945 /* We always operate 4 pairs of PERF Counters */
946 for (i = 0; i < 4; i++) {
947 event = cpuc->events[i];
948 if (event)
949 x86_perf_event_update(event);
950 }
11164cd4 951
351af072
ZY		 952 for (i = 0; i < 4; i++) {
953 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
954 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
955 }
956
957 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
958 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 959
351af072
ZY		 960 for (i = 0; i < 4; i++) {
961 event = cpuc->events[i];
962
963 if (event) {
964 x86_perf_event_set_period(event);
31fa58af 965 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 966 ARCH_PERFMON_EVENTSEL_ENABLE);
967 } else
968 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 969 }
351af072
ZY		 970}
971
972static void intel_pmu_nhm_enable_all(int added)
973{
974 if (added)
975 intel_pmu_nhm_workaround();
11164cd4
PZ		 976 intel_pmu_enable_all(added);
977}
978
f22f54f4
PZ		 979static inline u64 intel_pmu_get_status(void)
980{
981 u64 status;
982
983 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
984
985 return status;
986}
987
988static inline void intel_pmu_ack_status(u64 ack)
989{
990 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
991}
992
ca037701 993static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 994{
15c7ad51 995 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 996 u64 ctrl_val, mask;
997
998 mask = 0xfULL << (idx * 4);
999
1000 rdmsrl(hwc->config_base, ctrl_val);
1001 ctrl_val &= ~mask;
7645a24c 1002 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1003}
1004
ca037701 1005static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1006{
aff3d91a 1007 struct hw_perf_event *hwc = &event->hw;
144d31e6 1008 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1009
15c7ad51 1010 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1011 intel_pmu_disable_bts();
1012 intel_pmu_drain_bts_buffer();
1013 return;
1014 }
1015
144d31e6
GN		 1016 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1017 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1018
60ce0fbd
SE		 1019 /*
1020 * must disable before any actual event
1021 * because any event may be combined with LBR
1022 */
1023 if (intel_pmu_needs_lbr_smpl(event))
1024 intel_pmu_lbr_disable(event);
1025
f22f54f4 1026 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1027 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1028 return;
1029 }
1030
aff3d91a 1031 x86_pmu_disable_event(event);
ca037701 1032
ab608344 1033 if (unlikely(event->attr.precise_ip))
ef21f683 1034 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1035}
1036
ca037701 1037static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1038{
15c7ad51 1039 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1040 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1041
1042 /*
1043 * Enable IRQ generation (0x8),
1044 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1045 * if requested:
1046 */
1047 bits = 0x8ULL;
1048 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1049 bits |= 0x2;
1050 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1051 bits |= 0x1;
1052
1053 /*
1054 * ANY bit is supported in v3 and up
1055 */
1056 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1057 bits |= 0x4;
1058
1059 bits <<= (idx * 4);
1060 mask = 0xfULL << (idx * 4);
1061
1062 rdmsrl(hwc->config_base, ctrl_val);
1063 ctrl_val &= ~mask;
1064 ctrl_val |= bits;
7645a24c 1065 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1066}
1067
aff3d91a 1068static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1069{
aff3d91a 1070 struct hw_perf_event *hwc = &event->hw;
144d31e6 1071 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1072
15c7ad51 1073 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1074 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1075 return;
1076
1077 intel_pmu_enable_bts(hwc->config);
1078 return;
1079 }
60ce0fbd
SE		 1080 /*
1081 * must enabled before any actual event
1082 * because any event may be combined with LBR
1083 */
1084 if (intel_pmu_needs_lbr_smpl(event))
1085 intel_pmu_lbr_enable(event);
f22f54f4 1086
144d31e6
GN		 1087 if (event->attr.exclude_host)
1088 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1089 if (event->attr.exclude_guest)
1090 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1091
f22f54f4 1092 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1093 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1094 return;
1095 }
1096
ab608344 1097 if (unlikely(event->attr.precise_ip))
ef21f683 1098 intel_pmu_pebs_enable(event);
ca037701 1099
31fa58af 1100 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1101}
1102
1103/*
1104 * Save and restart an expired event. Called by NMI contexts,
1105 * so it has to be careful about preempting normal event ops:
1106 */
de0428a7 1107int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1108{
cc2ad4ba
PZ		 1109 x86_perf_event_update(event);
1110 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1111}
1112
1113static void intel_pmu_reset(void)
1114{
0a3aee0d 1115 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1116 unsigned long flags;
1117 int idx;
1118
948b1bb8 1119 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1120 return;
1121
1122 local_irq_save(flags);
1123
c767a54b 1124 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1125
948b1bb8 1126 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1127 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1128 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1129 }
948b1bb8 1130 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1131 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1132
f22f54f4
PZ		 1133 if (ds)
1134 ds->bts_index = ds->bts_buffer_base;
1135
1136 local_irq_restore(flags);
1137}
1138
1139/*
1140 * This handler is triggered by the local APIC, so the APIC IRQ handling
1141 * rules apply:
1142 */
1143static int intel_pmu_handle_irq(struct pt_regs *regs)
1144{
1145 struct perf_sample_data data;
1146 struct cpu_hw_events *cpuc;
1147 int bit, loops;
2e556b5b 1148 u64 status;
b0b2072d 1149 int handled;
f22f54f4 1150
f22f54f4
PZ		 1151 cpuc = &__get_cpu_var(cpu_hw_events);
1152
2bce5dac
DZ		 1153 /*
1154 * Some chipsets need to unmask the LVTPC in a particular spot
1155 * inside the nmi handler. As a result, the unmasking was pushed
1156 * into all the nmi handlers.
1157 *
1158 * This handler doesn't seem to have any issues with the unmasking
1159 * so it was left at the top.
1160 */
1161 apic_write(APIC_LVTPC, APIC_DM_NMI);
1162
3fb2b8dd 1163 intel_pmu_disable_all();
b0b2072d 1164 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1165 status = intel_pmu_get_status();
1166 if (!status) {
11164cd4 1167 intel_pmu_enable_all(0);
b0b2072d 1168 return handled;
f22f54f4
PZ		 1169 }
1170
1171 loops = 0;
1172again:
2e556b5b 1173 intel_pmu_ack_status(status);
f22f54f4
PZ		 1174 if (++loops > 100) {
1175 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1176 perf_event_print_debug();
1177 intel_pmu_reset();
3fb2b8dd 1178 goto done;
f22f54f4
PZ		 1179 }
1180
1181 inc_irq_stat(apic_perf_irqs);
ca037701 1182
caff2bef
PZ		 1183 intel_pmu_lbr_read();
1184
ca037701
PZ		 1185 /*
1186 * PEBS overflow sets bit 62 in the global status register
1187 */
de725dec
PZ		 1188 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1189 handled++;
ca037701 1190 x86_pmu.drain_pebs(regs);
de725dec 1191 }
ca037701 1192
984b3f57 1193 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1194 struct perf_event *event = cpuc->events[bit];
1195
de725dec
PZ		 1196 handled++;
1197
f22f54f4
PZ		 1198 if (!test_bit(bit, cpuc->active_mask))
1199 continue;
1200
1201 if (!intel_pmu_save_and_restart(event))
1202 continue;
1203
fd0d000b 1204 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1205
60ce0fbd
SE		 1206 if (has_branch_stack(event))
1207 data.br_stack = &cpuc->lbr_stack;
1208
a8b0ca17 1209 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1210 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1211 }
1212
f22f54f4
PZ		 1213 /*
1214 * Repeat if there is more work to be done:
1215 */
1216 status = intel_pmu_get_status();
1217 if (status)
1218 goto again;
1219
3fb2b8dd 1220done:
11164cd4 1221 intel_pmu_enable_all(0);
de725dec 1222 return handled;
f22f54f4
PZ		 1223}
1224
f22f54f4 1225static struct event_constraint *
ca037701 1226intel_bts_constraints(struct perf_event *event)
f22f54f4 1227{
ca037701
PZ		 1228 struct hw_perf_event *hwc = &event->hw;
1229 unsigned int hw_event, bts_event;
f22f54f4 1230
18a073a3
PZ		 1231 if (event->attr.freq)
1232 return NULL;
1233
ca037701
PZ		 1234 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1235 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1236
ca037701 1237 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1238 return &bts_constraint;
ca037701 1239
f22f54f4
PZ		 1240 return NULL;
1241}
1242
5a425294 1243static int intel_alt_er(int idx)
b79e8941
PZ		 1244{
1245 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1246 return idx;
b79e8941 1247
5a425294
PZ		 1248 if (idx == EXTRA_REG_RSP_0)
1249 return EXTRA_REG_RSP_1;
1250
1251 if (idx == EXTRA_REG_RSP_1)
1252 return EXTRA_REG_RSP_0;
1253
1254 return idx;
1255}
1256
1257static void intel_fixup_er(struct perf_event *event, int idx)
1258{
1259 event->hw.extra_reg.idx = idx;
1260
1261 if (idx == EXTRA_REG_RSP_0) {
b79e8941
PZ		 1262 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1263 event->hw.config |= 0x01b7;
b79e8941 1264 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1265 } else if (idx == EXTRA_REG_RSP_1) {
1266 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1267 event->hw.config |= 0x01bb;
1268 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1269 }
b79e8941
PZ		 1270}
1271
efc9f05d
SE		 1272/*
1273 * manage allocation of shared extra msr for certain events
1274 *
1275 * sharing can be:
1276 * per-cpu: to be shared between the various events on a single PMU
1277 * per-core: per-cpu + shared by HT threads
1278 */
a7e3ed1e 1279static struct event_constraint *
efc9f05d 1280__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1281 struct perf_event *event,
1282 struct hw_perf_event_extra *reg)
a7e3ed1e 1283{
efc9f05d 1284 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1285 struct er_account *era;
cd8a38d3 1286 unsigned long flags;
5a425294 1287 int idx = reg->idx;
a7e3ed1e 1288
5a425294
PZ		 1289 /*
1290 * reg->alloc can be set due to existing state, so for fake cpuc we
1291 * need to ignore this, otherwise we might fail to allocate proper fake
1292 * state for this extra reg constraint. Also see the comment below.
1293 */
1294 if (reg->alloc && !cpuc->is_fake)
b36817e8 1295 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1296
b79e8941 1297again:
5a425294 1298 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1299 /*
1300 * we use spin_lock_irqsave() to avoid lockdep issues when
1301 * passing a fake cpuc
1302 */
1303 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1304
1305 if (!atomic_read(&era->ref) || era->config == reg->config) {
1306
5a425294
PZ		 1307 /*
1308 * If its a fake cpuc -- as per validate_{group,event}() we
1309 * shouldn't touch event state and we can avoid doing so
1310 * since both will only call get_event_constraints() once
1311 * on each event, this avoids the need for reg->alloc.
1312 *
1313 * Not doing the ER fixup will only result in era->reg being
1314 * wrong, but since we won't actually try and program hardware
1315 * this isn't a problem either.
1316 */
1317 if (!cpuc->is_fake) {
1318 if (idx != reg->idx)
1319 intel_fixup_er(event, idx);
1320
1321 /*
1322 * x86_schedule_events() can call get_event_constraints()
1323 * multiple times on events in the case of incremental
1324 * scheduling(). reg->alloc ensures we only do the ER
1325 * allocation once.
1326 */
1327 reg->alloc = 1;
1328 }
1329
efc9f05d
SE		 1330 /* lock in msr value */
1331 era->config = reg->config;
1332 era->reg = reg->reg;
1333
1334 /* one more user */
1335 atomic_inc(&era->ref);
1336
a7e3ed1e 1337 /*
b36817e8
SE		 1338 * need to call x86_get_event_constraint()
1339 * to check if associated event has constraints
a7e3ed1e 1340 */
b36817e8 1341 c = NULL;
5a425294
PZ		 1342 } else {
1343 idx = intel_alt_er(idx);
1344 if (idx != reg->idx) {
1345 raw_spin_unlock_irqrestore(&era->lock, flags);
1346 goto again;
1347 }
a7e3ed1e 1348 }
cd8a38d3 1349 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1350
efc9f05d
SE		 1351 return c;
1352}
1353
1354static void
1355__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1356 struct hw_perf_event_extra *reg)
1357{
1358 struct er_account *era;
1359
1360 /*
5a425294
PZ		 1361 * Only put constraint if extra reg was actually allocated. Also takes
1362 * care of event which do not use an extra shared reg.
1363 *
1364 * Also, if this is a fake cpuc we shouldn't touch any event state
1365 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1366 * either since it'll be thrown out.
efc9f05d 1367 */
5a425294 1368 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1369 return;
1370
1371 era = &cpuc->shared_regs->regs[reg->idx];
1372
1373 /* one fewer user */
1374 atomic_dec(&era->ref);
1375
1376 /* allocate again next time */
1377 reg->alloc = 0;
1378}
1379
1380static struct event_constraint *
1381intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1382 struct perf_event *event)
1383{
b36817e8
SE		 1384 struct event_constraint *c = NULL, *d;
1385 struct hw_perf_event_extra *xreg, *breg;
1386
1387 xreg = &event->hw.extra_reg;
1388 if (xreg->idx != EXTRA_REG_NONE) {
1389 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1390 if (c == &emptyconstraint)
1391 return c;
1392 }
1393 breg = &event->hw.branch_reg;
1394 if (breg->idx != EXTRA_REG_NONE) {
1395 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1396 if (d == &emptyconstraint) {
1397 __intel_shared_reg_put_constraints(cpuc, xreg);
1398 c = d;
1399 }
1400 }
efc9f05d 1401 return c;
a7e3ed1e
AK		 1402}
1403
de0428a7
KW		 1404struct event_constraint *
1405x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1406{
1407 struct event_constraint *c;
1408
1409 if (x86_pmu.event_constraints) {
1410 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3
SE		 1411 if ((event->hw.config & c->cmask) == c->code) {
1412 /* hw.flags zeroed at initialization */
1413 event->hw.flags |= c->flags;
de0428a7 1414 return c;
9fac2cf3 1415 }
de0428a7
KW		 1416 }
1417 }
1418
1419 return &unconstrained;
1420}
1421
f22f54f4
PZ		 1422static struct event_constraint *
1423intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1424{
1425 struct event_constraint *c;
1426
ca037701
PZ		 1427 c = intel_bts_constraints(event);
1428 if (c)
1429 return c;
1430
1431 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1432 if (c)
1433 return c;
1434
efc9f05d 1435 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1436 if (c)
1437 return c;
1438
f22f54f4
PZ		 1439 return x86_get_event_constraints(cpuc, event);
1440}
1441
efc9f05d
SE		 1442static void
1443intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1444 struct perf_event *event)
1445{
efc9f05d 1446 struct hw_perf_event_extra *reg;
a7e3ed1e 1447
efc9f05d
SE		 1448 reg = &event->hw.extra_reg;
1449 if (reg->idx != EXTRA_REG_NONE)
1450 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1451
1452 reg = &event->hw.branch_reg;
1453 if (reg->idx != EXTRA_REG_NONE)
1454 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1455}
a7e3ed1e 1456
efc9f05d
SE		 1457static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1458 struct perf_event *event)
1459{
9fac2cf3 1460 event->hw.flags = 0;
efc9f05d 1461 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1462}
1463
0780c927 1464static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1465{
0780c927 1466 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1467 /*
1468 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1469 * (0x003c) so that we can use it with PEBS.
1470 *
1471 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1472 * PEBS capable. However we can use INST_RETIRED.ANY_P
1473 * (0x00c0), which is a PEBS capable event, to get the same
1474 * count.
1475 *
1476 * INST_RETIRED.ANY_P counts the number of cycles that retires
1477 * CNTMASK instructions. By setting CNTMASK to a value (16)
1478 * larger than the maximum number of instructions that can be
1479 * retired per cycle (4) and then inverting the condition, we
1480 * count all cycles that retire 16 or less instructions, which
1481 * is every cycle.
1482 *
1483 * Thereby we gain a PEBS capable cycle counter.
1484 */
f9b4eeb8
PZ		 1485 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1486
0780c927
PZ		 1487 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1488 event->hw.config = alt_config;
1489 }
1490}
1491
1492static void intel_pebs_aliases_snb(struct perf_event *event)
1493{
1494 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1495 /*
1496 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1497 * (0x003c) so that we can use it with PEBS.
1498 *
1499 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1500 * PEBS capable. However we can use UOPS_RETIRED.ALL
1501 * (0x01c2), which is a PEBS capable event, to get the same
1502 * count.
1503 *
1504 * UOPS_RETIRED.ALL counts the number of cycles that retires
1505 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1506 * larger than the maximum number of micro-ops that can be
1507 * retired per cycle (4) and then inverting the condition, we
1508 * count all cycles that retire 16 or less micro-ops, which
1509 * is every cycle.
1510 *
1511 * Thereby we gain a PEBS capable cycle counter.
1512 */
1513 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1514
1515 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1516 event->hw.config = alt_config;
1517 }
0780c927
PZ		 1518}
1519
1520static int intel_pmu_hw_config(struct perf_event *event)
1521{
1522 int ret = x86_pmu_hw_config(event);
1523
1524 if (ret)
1525 return ret;
1526
1527 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1528 x86_pmu.pebs_aliases(event);
7639dae0 1529
60ce0fbd
SE		 1530 if (intel_pmu_needs_lbr_smpl(event)) {
1531 ret = intel_pmu_setup_lbr_filter(event);
1532 if (ret)
1533 return ret;
1534 }
1535
b4cdc5c2
PZ		 1536 if (event->attr.type != PERF_TYPE_RAW)
1537 return 0;
1538
1539 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1540 return 0;
1541
1542 if (x86_pmu.version < 3)
1543 return -EINVAL;
1544
1545 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1546 return -EACCES;
1547
1548 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1549
1550 return 0;
1551}
1552
144d31e6
GN		 1553struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1554{
1555 if (x86_pmu.guest_get_msrs)
1556 return x86_pmu.guest_get_msrs(nr);
1557 *nr = 0;
1558 return NULL;
1559}
1560EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1561
1562static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1563{
1564 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1565 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1566
1567 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1568 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1569 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1570 /*
1571 * If PMU counter has PEBS enabled it is not enough to disable counter
1572 * on a guest entry since PEBS memory write can overshoot guest entry
1573 * and corrupt guest memory. Disabling PEBS solves the problem.
1574 */
1575 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1576 arr[1].host = cpuc->pebs_enabled;
1577 arr[1].guest = 0;
144d31e6 1578
26a4f3c0 1579 *nr = 2;
144d31e6
GN		 1580 return arr;
1581}
1582
1583static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1584{
1585 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1586 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1587 int idx;
1588
1589 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1590 struct perf_event *event = cpuc->events[idx];
1591
1592 arr[idx].msr = x86_pmu_config_addr(idx);
1593 arr[idx].host = arr[idx].guest = 0;
1594
1595 if (!test_bit(idx, cpuc->active_mask))
1596 continue;
1597
1598 arr[idx].host = arr[idx].guest =
1599 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1600
1601 if (event->attr.exclude_host)
1602 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1603 else if (event->attr.exclude_guest)
1604 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1605 }
1606
1607 *nr = x86_pmu.num_counters;
1608 return arr;
1609}
1610
1611static void core_pmu_enable_event(struct perf_event *event)
1612{
1613 if (!event->attr.exclude_host)
1614 x86_pmu_enable_event(event);
1615}
1616
1617static void core_pmu_enable_all(int added)
1618{
1619 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1620 int idx;
1621
1622 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1623 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1624
1625 if (!test_bit(idx, cpuc->active_mask) ||
1626 cpuc->events[idx]->attr.exclude_host)
1627 continue;
1628
1629 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1630 }
1631}
1632
641cc938
JO		 1633PMU_FORMAT_ATTR(event, "config:0-7" );
1634PMU_FORMAT_ATTR(umask, "config:8-15" );
1635PMU_FORMAT_ATTR(edge, "config:18" );
1636PMU_FORMAT_ATTR(pc, "config:19" );
1637PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1638PMU_FORMAT_ATTR(inv, "config:23" );
1639PMU_FORMAT_ATTR(cmask, "config:24-31" );
1640
1641static struct attribute *intel_arch_formats_attr[] = {
1642 &format_attr_event.attr,
1643 &format_attr_umask.attr,
1644 &format_attr_edge.attr,
1645 &format_attr_pc.attr,
1646 &format_attr_inv.attr,
1647 &format_attr_cmask.attr,
1648 NULL,
1649};
1650
0bf79d44
JO		 1651ssize_t intel_event_sysfs_show(char *page, u64 config)
1652{
1653 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1654
1655 return x86_event_sysfs_show(page, config, event);
1656}
1657
caaa8be3 1658static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1659 .name = "core",
1660 .handle_irq = x86_pmu_handle_irq,
1661 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1662 .enable_all = core_pmu_enable_all,
1663 .enable = core_pmu_enable_event,
f22f54f4 1664 .disable = x86_pmu_disable_event,
b4cdc5c2 1665 .hw_config = x86_pmu_hw_config,
a072738e 1666 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1667 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1668 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1669 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1670 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1671 .apic = 1,
1672 /*
1673 * Intel PMCs cannot be accessed sanely above 32 bit width,
1674 * so we install an artificial 1<<31 period regardless of
1675 * the generic event period:
1676 */
1677 .max_period = (1ULL << 31) - 1,
1678 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1679 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1680 .event_constraints = intel_core_event_constraints,
144d31e6 1681 .guest_get_msrs = core_guest_get_msrs,
641cc938 1682 .format_attrs = intel_arch_formats_attr,
0bf79d44 1683 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1684};
1685
de0428a7 1686struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1687{
1688 struct intel_shared_regs *regs;
1689 int i;
1690
1691 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1692 GFP_KERNEL, cpu_to_node(cpu));
1693 if (regs) {
1694 /*
1695 * initialize the locks to keep lockdep happy
1696 */
1697 for (i = 0; i < EXTRA_REG_MAX; i++)
1698 raw_spin_lock_init(&regs->regs[i].lock);
1699
1700 regs->core_id = -1;
1701 }
1702 return regs;
1703}
1704
a7e3ed1e
AK		 1705static int intel_pmu_cpu_prepare(int cpu)
1706{
1707 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1708
b36817e8 1709 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1710 return NOTIFY_OK;
1711
efc9f05d
SE		 1712 cpuc->shared_regs = allocate_shared_regs(cpu);
1713 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1714 return NOTIFY_BAD;
1715
a7e3ed1e
AK		 1716 return NOTIFY_OK;
1717}
1718
74846d35
PZ		 1719static void intel_pmu_cpu_starting(int cpu)
1720{
a7e3ed1e
AK		 1721 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1722 int core_id = topology_core_id(cpu);
1723 int i;
1724
69092624
LM		 1725 init_debug_store_on_cpu(cpu);
1726 /*
1727 * Deal with CPUs that don't clear their LBRs on power-up.
1728 */
1729 intel_pmu_lbr_reset();
1730
b36817e8
SE		 1731 cpuc->lbr_sel = NULL;
1732
1733 if (!cpuc->shared_regs)
69092624
LM		 1734 return;
1735
b36817e8
SE		 1736 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1737 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1738 struct intel_shared_regs *pc;
a7e3ed1e 1739
b36817e8
SE		 1740 pc = per_cpu(cpu_hw_events, i).shared_regs;
1741 if (pc && pc->core_id == core_id) {
1742 cpuc->kfree_on_online = cpuc->shared_regs;
1743 cpuc->shared_regs = pc;
1744 break;
1745 }
a7e3ed1e 1746 }
b36817e8
SE		 1747 cpuc->shared_regs->core_id = core_id;
1748 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1749 }
1750
b36817e8
SE		 1751 if (x86_pmu.lbr_sel_map)
1752 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1753}
1754
1755static void intel_pmu_cpu_dying(int cpu)
1756{
a7e3ed1e 1757 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1758 struct intel_shared_regs *pc;
a7e3ed1e 1759
efc9f05d 1760 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1761 if (pc) {
1762 if (pc->core_id == -1 || --pc->refcnt == 0)
1763 kfree(pc);
efc9f05d 1764 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1765 }
1766
74846d35
PZ		 1767 fini_debug_store_on_cpu(cpu);
1768}
1769
d010b332
SE		 1770static void intel_pmu_flush_branch_stack(void)
1771{
1772 /*
1773 * Intel LBR does not tag entries with the
1774 * PID of the current task, then we need to
1775 * flush it on ctxsw
1776 * For now, we simply reset it
1777 */
1778 if (x86_pmu.lbr_nr)
1779 intel_pmu_lbr_reset();
1780}
1781
641cc938
JO		 1782PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1783
1784static struct attribute *intel_arch3_formats_attr[] = {
1785 &format_attr_event.attr,
1786 &format_attr_umask.attr,
1787 &format_attr_edge.attr,
1788 &format_attr_pc.attr,
1789 &format_attr_any.attr,
1790 &format_attr_inv.attr,
1791 &format_attr_cmask.attr,
1792
1793 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1794 NULL,
1795};
1796
caaa8be3 1797static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1798 .name = "Intel",
1799 .handle_irq = intel_pmu_handle_irq,
1800 .disable_all = intel_pmu_disable_all,
1801 .enable_all = intel_pmu_enable_all,
1802 .enable = intel_pmu_enable_event,
1803 .disable = intel_pmu_disable_event,
b4cdc5c2 1804 .hw_config = intel_pmu_hw_config,
a072738e 1805 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1806 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1807 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1808 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1809 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1810 .apic = 1,
1811 /*
1812 * Intel PMCs cannot be accessed sanely above 32 bit width,
1813 * so we install an artificial 1<<31 period regardless of
1814 * the generic event period:
1815 */
1816 .max_period = (1ULL << 31) - 1,
3f6da390 1817 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1818 .put_event_constraints = intel_put_event_constraints,
0780c927 1819 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1820
641cc938 1821 .format_attrs = intel_arch3_formats_attr,
0bf79d44 1822 .events_sysfs_show = intel_event_sysfs_show,
641cc938 1823
a7e3ed1e 1824 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1825 .cpu_starting = intel_pmu_cpu_starting,
1826 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1827 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1828 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1829};
1830
c1d6f42f 1831static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1832{
1833 /*
1834 * PEBS is unreliable due to:
1835 *
1836 * AJ67 - PEBS may experience CPL leaks
1837 * AJ68 - PEBS PMI may be delayed by one event
1838 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1839 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1840 *
1841 * AJ67 could be worked around by restricting the OS/USR flags.
1842 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1843 *
1844 * AJ106 could possibly be worked around by not allowing LBR
1845 * usage from PEBS, including the fixup.
1846 * AJ68 could possibly be worked around by always programming
ec75a716 1847 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1848 *
1849 * But taken together it might just make sense to not enable PEBS on
1850 * these chips.
1851 */
c767a54b 1852 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1853 x86_pmu.pebs = 0;
1854 x86_pmu.pebs_constraints = NULL;
1855}
1856
c93dc84c
PZ		 1857static int intel_snb_pebs_broken(int cpu)
1858{
1859 u32 rev = UINT_MAX; /* default to broken for unknown models */
1860
1861 switch (cpu_data(cpu).x86_model) {
1862 case 42: /* SNB */
1863 rev = 0x28;
1864 break;
1865
1866 case 45: /* SNB-EP */
1867 switch (cpu_data(cpu).x86_mask) {
1868 case 6: rev = 0x618; break;
1869 case 7: rev = 0x70c; break;
1870 }
1871 }
1872
1873 return (cpu_data(cpu).microcode < rev);
1874}
1875
1876static void intel_snb_check_microcode(void)
1877{
1878 int pebs_broken = 0;
1879 int cpu;
1880
1881 get_online_cpus();
1882 for_each_online_cpu(cpu) {
1883 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1884 break;
1885 }
1886 put_online_cpus();
1887
1888 if (pebs_broken == x86_pmu.pebs_broken)
1889 return;
1890
1891 /*
1892 * Serialized by the microcode lock..
1893 */
1894 if (x86_pmu.pebs_broken) {
1895 pr_info("PEBS enabled due to microcode update\n");
1896 x86_pmu.pebs_broken = 0;
1897 } else {
1898 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1899 x86_pmu.pebs_broken = 1;
1900 }
1901}
1902
c1d6f42f 1903static __init void intel_sandybridge_quirk(void)
6a600a8b 1904{
c93dc84c
PZ		 1905 x86_pmu.check_microcode = intel_snb_check_microcode;
1906 intel_snb_check_microcode();
6a600a8b
PZ		 1907}
1908
c1d6f42f
PZ		 1909static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1910 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1911 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1912 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1913 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1914 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1915 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1916 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 1917};
1918
c1d6f42f
PZ		 1919static __init void intel_arch_events_quirk(void)
1920{
1921 int bit;
1922
1923 /* disable event that reported as not presend by cpuid */
1924 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1925 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 1926 pr_warn("CPUID marked event: \'%s\' unavailable\n",
1927 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 1928 }
1929}
1930
1931static __init void intel_nehalem_quirk(void)
1932{
1933 union cpuid10_ebx ebx;
1934
1935 ebx.full = x86_pmu.events_maskl;
1936 if (ebx.split.no_branch_misses_retired) {
1937 /*
1938 * Erratum AAJ80 detected, we work it around by using
1939 * the BR_MISP_EXEC.ANY event. This will over-count
1940 * branch-misses, but it's still much better than the
1941 * architectural event which is often completely bogus:
1942 */
1943 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1944 ebx.split.no_branch_misses_retired = 0;
1945 x86_pmu.events_maskl = ebx.full;
c767a54b 1946 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 1947 }
1948}
1949
de0428a7 1950__init int intel_pmu_init(void)
f22f54f4
PZ		 1951{
1952 union cpuid10_edx edx;
1953 union cpuid10_eax eax;
ffb871bc 1954 union cpuid10_ebx ebx;
a1eac7ac 1955 struct event_constraint *c;
f22f54f4 1956 unsigned int unused;
f22f54f4
PZ		 1957 int version;
1958
1959 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 1960 switch (boot_cpu_data.x86) {
1961 case 0x6:
1962 return p6_pmu_init();
e717bf4e
VW		 1963 case 0xb:
1964 return knc_pmu_init();
a072738e
CG		 1965 case 0xf:
1966 return p4_pmu_init();
1967 }
f22f54f4 1968 return -ENODEV;
f22f54f4
PZ		 1969 }
1970
1971 /*
1972 * Check whether the Architectural PerfMon supports
1973 * Branch Misses Retired hw_event or not.
1974 */
ffb871bc
GN		 1975 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1976 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 1977 return -ENODEV;
1978
1979 version = eax.split.version_id;
1980 if (version < 2)
1981 x86_pmu = core_pmu;
1982 else
1983 x86_pmu = intel_pmu;
1984
1985 x86_pmu.version = version;
948b1bb8
RR		 1986 x86_pmu.num_counters = eax.split.num_counters;
1987 x86_pmu.cntval_bits = eax.split.bit_width;
1988 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 1989
c1d6f42f
PZ		 1990 x86_pmu.events_maskl = ebx.full;
1991 x86_pmu.events_mask_len = eax.split.mask_length;
1992
70ab7003
AK		 1993 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
1994
f22f54f4
PZ		 1995 /*
1996 * Quirk: v2 perfmon does not report fixed-purpose events, so
1997 * assume at least 3 events:
1998 */
1999 if (version > 1)
948b1bb8 2000 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2001
8db909a7
PZ		 2002 /*
2003 * v2 and above have a perf capabilities MSR
2004 */
2005 if (version > 1) {
2006 u64 capabilities;
2007
2008 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2009 x86_pmu.intel_cap.capabilities = capabilities;
2010 }
2011
ca037701
PZ		 2012 intel_ds_init();
2013
c1d6f42f
PZ		 2014 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2015
f22f54f4
PZ		 2016 /*
2017 * Install the hw-cache-events table:
2018 */
2019 switch (boot_cpu_data.x86_model) {
2020 case 14: /* 65 nm core solo/duo, "Yonah" */
2021 pr_cont("Core events, ");
2022 break;
2023
2024 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2025 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2026 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2027 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2028 case 29: /* six-core 45 nm xeon "Dunnington" */
2029 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2030 sizeof(hw_cache_event_ids));
2031
caff2bef
PZ		 2032 intel_pmu_lbr_init_core();
2033
f22f54f4 2034 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2035 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2036 pr_cont("Core2 events, ");
2037 break;
2038
2039 case 26: /* 45 nm nehalem, "Bloomfield" */
2040 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2041 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2042 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2043 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2044 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2045 sizeof(hw_cache_extra_regs));
f22f54f4 2046
caff2bef
PZ		 2047 intel_pmu_lbr_init_nhm();
2048
f22f54f4 2049 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2050 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2051 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2052 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2053
f20093ee
SE		 2054 x86_pmu.cpu_events = nhm_events_attrs;
2055
91fc4cc0 2056 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2057 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2058 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2059 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2060 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2061 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2062
c1d6f42f 2063 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2064
11164cd4 2065 pr_cont("Nehalem events, ");
f22f54f4 2066 break;
caff2bef 2067
b622d644 2068 case 28: /* Atom */
0927b482
SL		 2069 case 38: /* Lincroft */
2070 case 39: /* Penwell */
2071 case 53: /* Cloverview */
2072 case 54: /* Cedarview */
f22f54f4
PZ		 2073 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2074 sizeof(hw_cache_event_ids));
2075
caff2bef
PZ		 2076 intel_pmu_lbr_init_atom();
2077
f22f54f4 2078 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2079 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2080 pr_cont("Atom events, ");
2081 break;
2082
2083 case 37: /* 32 nm nehalem, "Clarkdale" */
2084 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2085 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2086 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2087 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2088 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2089 sizeof(hw_cache_extra_regs));
f22f54f4 2090
caff2bef
PZ		 2091 intel_pmu_lbr_init_nhm();
2092
f22f54f4 2093 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2094 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2095 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2096 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2097 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2098
f20093ee
SE		 2099 x86_pmu.cpu_events = nhm_events_attrs;
2100
30112039 2101 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2102 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2103 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2104 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2105 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2106 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2107
f22f54f4
PZ		 2108 pr_cont("Westmere events, ");
2109 break;
b622d644 2110
b06b3d49 2111 case 42: /* SandyBridge */
a34668f6 2112 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2113 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2114 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2115 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2116 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2117 sizeof(hw_cache_extra_regs));
b06b3d49 2118
c5cc2cd9 2119 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2120
2121 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2122 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2123 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
ee89cbc2
SE		 2124 x86_pmu.extra_regs = intel_snb_extra_regs;
2125 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2126 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2127 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2128
f20093ee
SE		 2129 x86_pmu.cpu_events = snb_events_attrs;
2130
e04d1b23 2131 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2132 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2133 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2134 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2135 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2136 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2137
b06b3d49
LM		 2138 pr_cont("SandyBridge events, ");
2139 break;
20a36e39 2140 case 58: /* IvyBridge */
923d8697 2141 case 62: /* IvyBridge EP */
20a36e39
SE		 2142 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2143 sizeof(hw_cache_event_ids));
2144 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2145 sizeof(hw_cache_extra_regs));
2146
2147 intel_pmu_lbr_init_snb();
2148
69943182 2149 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2150 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2151 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2152 x86_pmu.extra_regs = intel_snb_extra_regs;
2153 /* all extra regs are per-cpu when HT is on */
2154 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2155 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2156
f20093ee
SE		 2157 x86_pmu.cpu_events = snb_events_attrs;
2158
20a36e39
SE		 2159 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2160 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2161 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2162
2163 pr_cont("IvyBridge events, ");
2164 break;
2165
b06b3d49 2166
f22f54f4 2167 default:
0af3ac1f
AK		 2168 switch (x86_pmu.version) {
2169 case 1:
2170 x86_pmu.event_constraints = intel_v1_event_constraints;
2171 pr_cont("generic architected perfmon v1, ");
2172 break;
2173 default:
2174 /*
2175 * default constraints for v2 and up
2176 */
2177 x86_pmu.event_constraints = intel_gen_event_constraints;
2178 pr_cont("generic architected perfmon, ");
2179 break;
2180 }
f22f54f4 2181 }
ffb871bc 2182
a1eac7ac
RR		 2183 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2184 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2185 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2186 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2187 }
2188 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2189
2190 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2191 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2192 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2193 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2194 }
2195
2196 x86_pmu.intel_ctrl |=
2197 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2198
2199 if (x86_pmu.event_constraints) {
2200 /*
2201 * event on fixed counter2 (REF_CYCLES) only works on this
2202 * counter, so do not extend mask to generic counters
2203 */
2204 for_each_event_constraint(c, x86_pmu.event_constraints) {
2205 if (c->cmask != X86_RAW_EVENT_MASK
2206 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2207 continue;
2208 }
2209
2210 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2211 c->weight += x86_pmu.num_counters;
2212 }
2213 }
2214
f22f54f4
PZ		 2215 return 0;
2216}
Linux kernel - Deliverables
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