[deliverable/linux.git] / arch / x86 / kernel / cpu / scattered.c

/*
 *	Routines to identify additional cpu features that are scattered in
 *	cpuid space.
 */
#include <linux/cpu.h>

#include <asm/pat.h>
#include <asm/processor.h>

#include <asm/apic.h>

struct cpuid_bit {
	u16 feature;
	u8 reg;
	u8 bit;
	u32 level;
	u32 sub_leaf;
};

enum cpuid_regs {
	CR_EAX = 0,
	CR_ECX,
	CR_EDX,
	CR_EBX
};

void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{
	u32 max_level;
	u32 regs[4];
	const struct cpuid_bit *cb;

	static const struct cpuid_bit cpuid_bits[] = {
		{ X86_FEATURE_INTEL_PT,		CR_EBX,25, 0x00000007, 0 },
		{ X86_FEATURE_APERFMPERF,	CR_ECX, 0, 0x00000006, 0 },
		{ X86_FEATURE_EPB,		CR_ECX, 3, 0x00000006, 0 },
		{ X86_FEATURE_HW_PSTATE,	CR_EDX, 7, 0x80000007, 0 },
		{ X86_FEATURE_CPB,		CR_EDX, 9, 0x80000007, 0 },
		{ X86_FEATURE_PROC_FEEDBACK,	CR_EDX,11, 0x80000007, 0 },
		{ 0, 0, 0, 0, 0 }
	};

	for (cb = cpuid_bits; cb->feature; cb++) {

		/* Verify that the level is valid */
		max_level = cpuid_eax(cb->level & 0xffff0000);
		if (max_level < cb->level ||
		    max_level > (cb->level | 0xffff))
			continue;

		cpuid_count(cb->level, cb->sub_leaf, &regs[CR_EAX],
			    &regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);

		if (regs[cb->reg] & (1 << cb->bit))
			set_cpu_cap(c, cb->feature);
	}
}
Commit	Line	Data
2decb194	1	/*
3f79410c	2	* Routines to identify additional cpu features that are scattered in
2decb194 PA	3	* cpuid space.
	4	*/
	5	#include <linux/cpu.h>
	6
	7	#include <asm/pat.h>
	8	#include <asm/processor.h>
	9
	10	#include <asm/apic.h>
	11
	12	struct cpuid_bit {
	13	u16 feature;
	14	u8 reg;
	15	u8 bit;
	16	u32 level;
	17	u32 sub_leaf;
	18	};
	19
	20	enum cpuid_regs {
	21	CR_EAX = 0,
	22	CR_ECX,
	23	CR_EDX,
	24	CR_EBX
	25	};
	26
148f9bb8	27	void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
2decb194 PA	28	{
	29	u32 max_level;
	30	u32 regs[4];
	31	const struct cpuid_bit *cb;
	32
148f9bb8	33	static const struct cpuid_bit cpuid_bits[] = {
ed69628b	34	{ X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
2decb194 PA	35	{ X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
2decb194 PA	36	{ X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
2f1e097e	37	{ X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
9c5320c8 JS	38	{ X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
9c5320c8 JS	39	{ X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
2decb194 PA	40	{ 0, 0, 0, 0, 0 }
	41	};
	42
	43	for (cb = cpuid_bits; cb->feature; cb++) {
	44
	45	/* Verify that the level is valid */
	46	max_level = cpuid_eax(cb->level & 0xffff0000);
	47	if (max_level < cb->level \|\|
	48	max_level > (cb->level \| 0xffff))
	49	continue;
	50
	51	cpuid_count(cb->level, cb->sub_leaf, &regs[CR_EAX],
	52	&regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);
	53
	54	if (regs[cb->reg] & (1 << cb->bit))
	55	set_cpu_cap(c, cb->feature);
	56	}
	57	}