Commit | Line | Data |
---|---|---|
da6b737b SAS |
1 | /* |
2 | * Architecture specific OF callbacks. | |
3 | */ | |
4 | #include <linux/bootmem.h> | |
69c60c88 | 5 | #include <linux/export.h> |
da6b737b | 6 | #include <linux/io.h> |
b4e51854 | 7 | #include <linux/irqdomain.h> |
19c4f5f7 | 8 | #include <linux/interrupt.h> |
da6b737b SAS |
9 | #include <linux/list.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/of_fdt.h> | |
3879a6f3 | 12 | #include <linux/of_address.h> |
da6b737b | 13 | #include <linux/of_platform.h> |
96e0a079 | 14 | #include <linux/of_irq.h> |
da6b737b | 15 | #include <linux/slab.h> |
96e0a079 SAS |
16 | #include <linux/pci.h> |
17 | #include <linux/of_pci.h> | |
977cb76d | 18 | #include <linux/initrd.h> |
da6b737b | 19 | |
ffb9fc68 | 20 | #include <asm/hpet.h> |
3879a6f3 | 21 | #include <asm/apic.h> |
96e0a079 | 22 | #include <asm/pci_x86.h> |
ba904f06 | 23 | #include <asm/setup.h> |
95d76acc | 24 | #include <asm/i8259.h> |
19c4f5f7 | 25 | |
3879a6f3 | 26 | __initdata u64 initial_dtb; |
da6b737b | 27 | char __initdata cmd_line[COMMAND_LINE_SIZE]; |
19c4f5f7 | 28 | |
3879a6f3 SAS |
29 | int __initdata of_ioapic; |
30 | ||
da6b737b SAS |
31 | void __init early_init_dt_scan_chosen_arch(unsigned long node) |
32 | { | |
33 | BUG(); | |
34 | } | |
35 | ||
36 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
37 | { | |
38 | BUG(); | |
39 | } | |
40 | ||
41 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
42 | { | |
43 | return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); | |
44 | } | |
45 | ||
46 | void __init add_dtb(u64 data) | |
47 | { | |
3879a6f3 SAS |
48 | initial_dtb = data + offsetof(struct setup_data, data); |
49 | } | |
50 | ||
9079b353 SAS |
51 | /* |
52 | * CE4100 ids. Will be moved to machine_device_initcall() once we have it. | |
53 | */ | |
54 | static struct of_device_id __initdata ce4100_ids[] = { | |
55 | { .compatible = "intel,ce4100-cp", }, | |
56 | { .compatible = "isa", }, | |
57 | { .compatible = "pci", }, | |
58 | {}, | |
59 | }; | |
60 | ||
61 | static int __init add_bus_probe(void) | |
62 | { | |
4a66b1d9 | 63 | if (!of_have_populated_dt()) |
9079b353 SAS |
64 | return 0; |
65 | ||
66 | return of_platform_bus_probe(NULL, ce4100_ids, NULL); | |
67 | } | |
68 | module_init(add_bus_probe); | |
69 | ||
96e0a079 | 70 | #ifdef CONFIG_PCI |
3d5fe5a6 BH |
71 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
72 | { | |
73 | struct device_node *np; | |
74 | ||
75 | for_each_node_by_type(np, "pci") { | |
76 | const void *prop; | |
77 | unsigned int bus_min; | |
78 | ||
79 | prop = of_get_property(np, "bus-range", NULL); | |
80 | if (!prop) | |
81 | continue; | |
82 | bus_min = be32_to_cpup(prop); | |
83 | if (bus->number == bus_min) | |
84 | return np; | |
85 | } | |
86 | return NULL; | |
87 | } | |
88 | ||
96e0a079 SAS |
89 | static int x86_of_pci_irq_enable(struct pci_dev *dev) |
90 | { | |
96e0a079 SAS |
91 | u32 virq; |
92 | int ret; | |
93 | u8 pin; | |
94 | ||
95 | ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
96 | if (ret) | |
97 | return ret; | |
98 | if (!pin) | |
99 | return 0; | |
100 | ||
16b84e5a | 101 | virq = of_irq_parse_and_map_pci(dev, 0, 0); |
96e0a079 SAS |
102 | if (virq == 0) |
103 | return -EINVAL; | |
104 | dev->irq = virq; | |
105 | return 0; | |
106 | } | |
107 | ||
108 | static void x86_of_pci_irq_disable(struct pci_dev *dev) | |
109 | { | |
110 | } | |
111 | ||
148f9bb8 | 112 | void x86_of_pci_init(void) |
96e0a079 | 113 | { |
96e0a079 SAS |
114 | pcibios_enable_irq = x86_of_pci_irq_enable; |
115 | pcibios_disable_irq = x86_of_pci_irq_disable; | |
96e0a079 SAS |
116 | } |
117 | #endif | |
118 | ||
ffb9fc68 SAS |
119 | static void __init dtb_setup_hpet(void) |
120 | { | |
4a66b1d9 | 121 | #ifdef CONFIG_HPET_TIMER |
ffb9fc68 SAS |
122 | struct device_node *dn; |
123 | struct resource r; | |
124 | int ret; | |
125 | ||
126 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); | |
127 | if (!dn) | |
128 | return; | |
129 | ret = of_address_to_resource(dn, 0, &r); | |
130 | if (ret) { | |
131 | WARN_ON(1); | |
132 | return; | |
133 | } | |
134 | hpet_address = r.start; | |
4a66b1d9 | 135 | #endif |
ffb9fc68 SAS |
136 | } |
137 | ||
3879a6f3 SAS |
138 | static void __init dtb_lapic_setup(void) |
139 | { | |
140 | #ifdef CONFIG_X86_LOCAL_APIC | |
a906fdaa TG |
141 | struct device_node *dn; |
142 | struct resource r; | |
143 | int ret; | |
144 | ||
145 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); | |
146 | if (!dn) | |
3879a6f3 SAS |
147 | return; |
148 | ||
a906fdaa TG |
149 | ret = of_address_to_resource(dn, 0, &r); |
150 | if (WARN_ON(ret)) | |
151 | return; | |
152 | ||
153 | /* Did the boot loader setup the local APIC ? */ | |
154 | if (!cpu_has_apic) { | |
155 | if (apic_force_enable(r.start)) | |
156 | return; | |
157 | } | |
3879a6f3 SAS |
158 | smp_found_config = 1; |
159 | pic_mode = 1; | |
a906fdaa | 160 | register_lapic_address(r.start); |
3879a6f3 | 161 | generic_processor_info(boot_cpu_physical_apicid, |
a906fdaa | 162 | GET_APIC_VERSION(apic_read(APIC_LVR))); |
3879a6f3 SAS |
163 | #endif |
164 | } | |
165 | ||
166 | #ifdef CONFIG_X86_IO_APIC | |
167 | static unsigned int ioapic_id; | |
168 | ||
169 | static void __init dtb_add_ioapic(struct device_node *dn) | |
170 | { | |
171 | struct resource r; | |
172 | int ret; | |
173 | ||
174 | ret = of_address_to_resource(dn, 0, &r); | |
175 | if (ret) { | |
176 | printk(KERN_ERR "Can't obtain address from node %s.\n", | |
177 | dn->full_name); | |
178 | return; | |
179 | } | |
180 | mp_register_ioapic(++ioapic_id, r.start, gsi_top); | |
181 | } | |
182 | ||
183 | static void __init dtb_ioapic_setup(void) | |
184 | { | |
185 | struct device_node *dn; | |
186 | ||
3879a6f3 SAS |
187 | for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") |
188 | dtb_add_ioapic(dn); | |
189 | ||
190 | if (nr_ioapics) { | |
191 | of_ioapic = 1; | |
192 | return; | |
193 | } | |
194 | printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); | |
3879a6f3 SAS |
195 | } |
196 | #else | |
197 | static void __init dtb_ioapic_setup(void) {} | |
198 | #endif | |
199 | ||
200 | static void __init dtb_apic_setup(void) | |
201 | { | |
202 | dtb_lapic_setup(); | |
203 | dtb_ioapic_setup(); | |
204 | } | |
205 | ||
4a66b1d9 SAS |
206 | #ifdef CONFIG_OF_FLATTREE |
207 | static void __init x86_flattree_get_config(void) | |
3879a6f3 SAS |
208 | { |
209 | u32 size, map_len; | |
1bac1869 | 210 | void *dt; |
3879a6f3 SAS |
211 | |
212 | if (!initial_dtb) | |
213 | return; | |
214 | ||
1bac1869 | 215 | map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128); |
3879a6f3 | 216 | |
1bac1869 RH |
217 | initial_boot_params = dt = early_memremap(initial_dtb, map_len); |
218 | size = of_get_flat_dt_size(); | |
3879a6f3 | 219 | if (map_len < size) { |
21c561bd | 220 | early_iounmap(dt, map_len); |
1bac1869 | 221 | initial_boot_params = dt = early_memremap(initial_dtb, size); |
3879a6f3 SAS |
222 | map_len = size; |
223 | } | |
224 | ||
21c561bd RH |
225 | unflatten_and_copy_device_tree(); |
226 | early_iounmap(dt, map_len); | |
4a66b1d9 SAS |
227 | } |
228 | #else | |
229 | static inline void x86_flattree_get_config(void) { } | |
230 | #endif | |
231 | ||
a906fdaa | 232 | void __init x86_dtb_init(void) |
4a66b1d9 SAS |
233 | { |
234 | x86_flattree_get_config(); | |
235 | ||
236 | if (!of_have_populated_dt()) | |
237 | return; | |
238 | ||
ffb9fc68 | 239 | dtb_setup_hpet(); |
3879a6f3 | 240 | dtb_apic_setup(); |
da6b737b | 241 | } |
bcc7c124 SAS |
242 | |
243 | #ifdef CONFIG_X86_IO_APIC | |
244 | ||
245 | struct of_ioapic_type { | |
246 | u32 out_type; | |
247 | u32 trigger; | |
248 | u32 polarity; | |
249 | }; | |
250 | ||
251 | static struct of_ioapic_type of_ioapic_type[] = | |
252 | { | |
253 | { | |
254 | .out_type = IRQ_TYPE_EDGE_RISING, | |
255 | .trigger = IOAPIC_EDGE, | |
256 | .polarity = 1, | |
257 | }, | |
258 | { | |
259 | .out_type = IRQ_TYPE_LEVEL_LOW, | |
260 | .trigger = IOAPIC_LEVEL, | |
261 | .polarity = 0, | |
262 | }, | |
263 | { | |
264 | .out_type = IRQ_TYPE_LEVEL_HIGH, | |
265 | .trigger = IOAPIC_LEVEL, | |
266 | .polarity = 1, | |
267 | }, | |
268 | { | |
269 | .out_type = IRQ_TYPE_EDGE_FALLING, | |
270 | .trigger = IOAPIC_EDGE, | |
271 | .polarity = 0, | |
272 | }, | |
273 | }; | |
274 | ||
b4e51854 GL |
275 | static int ioapic_xlate(struct irq_domain *domain, |
276 | struct device_node *controller, | |
277 | const u32 *intspec, u32 intsize, | |
278 | irq_hw_number_t *out_hwirq, u32 *out_type) | |
bcc7c124 SAS |
279 | { |
280 | struct io_apic_irq_attr attr; | |
281 | struct of_ioapic_type *it; | |
b4e51854 GL |
282 | u32 line, idx; |
283 | int rc; | |
bcc7c124 | 284 | |
b4e51854 | 285 | if (WARN_ON(intsize < 2)) |
bcc7c124 SAS |
286 | return -EINVAL; |
287 | ||
b4e51854 | 288 | line = intspec[0]; |
bcc7c124 | 289 | |
b4e51854 | 290 | if (intspec[1] >= ARRAY_SIZE(of_ioapic_type)) |
bcc7c124 SAS |
291 | return -EINVAL; |
292 | ||
b4e51854 | 293 | it = &of_ioapic_type[intspec[1]]; |
bcc7c124 | 294 | |
b4e51854 | 295 | idx = (u32) domain->host_data; |
bcc7c124 SAS |
296 | set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); |
297 | ||
b4e51854 GL |
298 | rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line), |
299 | cpu_to_node(0), &attr); | |
300 | if (rc) | |
301 | return rc; | |
302 | ||
303 | *out_hwirq = line; | |
304 | *out_type = it->out_type; | |
305 | return 0; | |
bcc7c124 SAS |
306 | } |
307 | ||
b4e51854 GL |
308 | const struct irq_domain_ops ioapic_irq_domain_ops = { |
309 | .xlate = ioapic_xlate, | |
310 | }; | |
311 | ||
ece3234a SAS |
312 | static void dt_add_ioapic_domain(unsigned int ioapic_num, |
313 | struct device_node *np) | |
314 | { | |
315 | struct irq_domain *id; | |
316 | struct mp_ioapic_gsi *gsi_cfg; | |
317 | int ret; | |
95d76acc | 318 | int num, legacy_irqs = nr_legacy_irqs(); |
ece3234a SAS |
319 | |
320 | gsi_cfg = mp_ioapic_gsi_routing(ioapic_num); | |
321 | num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
322 | ||
323 | id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops, | |
324 | (void *)ioapic_num); | |
325 | BUG_ON(!id); | |
326 | if (gsi_cfg->gsi_base == 0) { | |
327 | /* | |
95d76acc | 328 | * The first nr_legacy_irqs() irq descs are allocated in |
ece3234a SAS |
329 | * early_irq_init() and need just a mapping. The |
330 | * remaining irqs need both. All of them are preallocated | |
331 | * and assigned so we can keep the 1:1 mapping which the ioapic | |
332 | * is having. | |
333 | */ | |
95d76acc | 334 | irq_domain_associate_many(id, 0, 0, legacy_irqs); |
ece3234a | 335 | |
95d76acc JL |
336 | if (num > legacy_irqs) { |
337 | ret = irq_create_strict_mappings(id, legacy_irqs, | |
338 | legacy_irqs, num - legacy_irqs); | |
ece3234a SAS |
339 | if (ret) |
340 | pr_err("Error creating mapping for the " | |
341 | "remaining IRQs: %d\n", ret); | |
342 | } | |
343 | irq_set_default_host(id); | |
344 | } else { | |
345 | ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num); | |
346 | if (ret) | |
347 | pr_err("Error creating IRQ mapping: %d\n", ret); | |
348 | } | |
349 | } | |
350 | ||
bcc7c124 SAS |
351 | static void __init ioapic_add_ofnode(struct device_node *np) |
352 | { | |
353 | struct resource r; | |
354 | int i, ret; | |
355 | ||
356 | ret = of_address_to_resource(np, 0, &r); | |
357 | if (ret) { | |
358 | printk(KERN_ERR "Failed to obtain address for %s\n", | |
359 | np->full_name); | |
360 | return; | |
361 | } | |
362 | ||
363 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 364 | if (r.start == mpc_ioapic_addr(i)) { |
ece3234a | 365 | dt_add_ioapic_domain(i, np); |
bcc7c124 SAS |
366 | return; |
367 | } | |
368 | } | |
369 | printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name); | |
370 | } | |
371 | ||
372 | void __init x86_add_irq_domains(void) | |
373 | { | |
374 | struct device_node *dp; | |
375 | ||
4a66b1d9 | 376 | if (!of_have_populated_dt()) |
bcc7c124 SAS |
377 | return; |
378 | ||
379 | for_each_node_with_property(dp, "interrupt-controller") { | |
380 | if (of_device_is_compatible(dp, "intel,ce4100-ioapic")) | |
381 | ioapic_add_ofnode(dp); | |
382 | } | |
383 | } | |
384 | #else | |
385 | void __init x86_add_irq_domains(void) { } | |
386 | #endif |