Commit | Line | Data |
---|---|---|
dfa4698c AK |
1 | /* Various workarounds for chipset bugs. |
2 | This code runs very early and can't use the regular PCI subsystem | |
3 | The entries are keyed to PCI bridges which usually identify chipsets | |
4 | uniquely. | |
5 | This is only for whole classes of chipsets with specific problems which | |
6 | need early invasive action (e.g. before the timers are initialized). | |
7 | Most PCI device specific workarounds can be done later and should be | |
8 | in standard PCI quirks | |
9 | Mainboard specific bugs should be handled by DMI entries. | |
10 | CPU specific bugs in setup.c */ | |
11 | ||
12 | #include <linux/pci.h> | |
13 | #include <linux/acpi.h> | |
abb2bafd LW |
14 | #include <linux/delay.h> |
15 | #include <linux/dmi.h> | |
dfa4698c | 16 | #include <linux/pci_ids.h> |
abb2bafd LW |
17 | #include <linux/bcma/bcma.h> |
18 | #include <linux/bcma/bcma_regs.h> | |
814c5f1f | 19 | #include <drm/i915_drm.h> |
dfa4698c | 20 | #include <asm/pci-direct.h> |
dfa4698c | 21 | #include <asm/dma.h> |
54ef3400 AK |
22 | #include <asm/io_apic.h> |
23 | #include <asm/apic.h> | |
62187910 | 24 | #include <asm/hpet.h> |
46a7fa27 | 25 | #include <asm/iommu.h> |
1d9b16d1 | 26 | #include <asm/gart.h> |
03bbcb2e | 27 | #include <asm/irq_remapping.h> |
abb2bafd LW |
28 | #include <asm/early_ioremap.h> |
29 | ||
30 | #define dev_err(msg) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg) | |
dfa4698c | 31 | |
c6b48324 NH |
32 | static void __init fix_hypertransport_config(int num, int slot, int func) |
33 | { | |
34 | u32 htcfg; | |
35 | /* | |
36 | * we found a hypertransport bus | |
37 | * make sure that we are broadcasting | |
38 | * interrupts to all cpus on the ht bus | |
39 | * if we're using extended apic ids | |
40 | */ | |
41 | htcfg = read_pci_config(num, slot, func, 0x68); | |
42 | if (htcfg & (1 << 18)) { | |
7bcbc78d NH |
43 | printk(KERN_INFO "Detected use of extended apic ids " |
44 | "on hypertransport bus\n"); | |
c6b48324 | 45 | if ((htcfg & (1 << 17)) == 0) { |
7bcbc78d NH |
46 | printk(KERN_INFO "Enabling hypertransport extended " |
47 | "apic interrupt broadcast\n"); | |
48 | printk(KERN_INFO "Note this is a bios bug, " | |
49 | "please contact your hw vendor\n"); | |
c6b48324 NH |
50 | htcfg |= (1 << 17); |
51 | write_pci_config(num, slot, func, 0x68, htcfg); | |
52 | } | |
53 | } | |
54 | ||
55 | ||
56 | } | |
57 | ||
58 | static void __init via_bugs(int num, int slot, int func) | |
dfa4698c | 59 | { |
966396d3 | 60 | #ifdef CONFIG_GART_IOMMU |
c987d12f | 61 | if ((max_pfn > MAX_DMA32_PFN || force_iommu) && |
0440d4c0 | 62 | !gart_iommu_aperture_allowed) { |
dfa4698c | 63 | printk(KERN_INFO |
54ef3400 AK |
64 | "Looks like a VIA chipset. Disabling IOMMU." |
65 | " Override with iommu=allowed\n"); | |
0440d4c0 | 66 | gart_iommu_aperture_disabled = 1; |
dfa4698c AK |
67 | } |
68 | #endif | |
69 | } | |
70 | ||
71 | #ifdef CONFIG_ACPI | |
03d0d20e | 72 | #ifdef CONFIG_X86_IO_APIC |
dfa4698c | 73 | |
15a58ed1 | 74 | static int __init nvidia_hpet_check(struct acpi_table_header *header) |
dfa4698c | 75 | { |
dfa4698c AK |
76 | return 0; |
77 | } | |
03d0d20e JG |
78 | #endif /* CONFIG_X86_IO_APIC */ |
79 | #endif /* CONFIG_ACPI */ | |
dfa4698c | 80 | |
c6b48324 | 81 | static void __init nvidia_bugs(int num, int slot, int func) |
dfa4698c AK |
82 | { |
83 | #ifdef CONFIG_ACPI | |
54ef3400 | 84 | #ifdef CONFIG_X86_IO_APIC |
447d29d1 LW |
85 | /* |
86 | * Only applies to Nvidia root ports (bus 0) and not to | |
87 | * Nvidia graphics cards with PCI ports on secondary buses. | |
88 | */ | |
89 | if (num) | |
90 | return; | |
91 | ||
dfa4698c AK |
92 | /* |
93 | * All timer overrides on Nvidia are | |
94 | * wrong unless HPET is enabled. | |
fa18f477 AK |
95 | * Unfortunately that's not true on many Asus boards. |
96 | * We don't know yet how to detect this automatically, but | |
97 | * at least allow a command line override. | |
dfa4698c | 98 | */ |
fa18f477 AK |
99 | if (acpi_use_timer_override) |
100 | return; | |
101 | ||
fe699336 | 102 | if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) { |
dfa4698c AK |
103 | acpi_skip_timer_override = 1; |
104 | printk(KERN_INFO "Nvidia board " | |
105 | "detected. Ignoring ACPI " | |
106 | "timer override.\n"); | |
fa18f477 AK |
107 | printk(KERN_INFO "If you got timer trouble " |
108 | "try acpi_use_timer_override\n"); | |
dfa4698c | 109 | } |
54ef3400 | 110 | #endif |
dfa4698c AK |
111 | #endif |
112 | /* RED-PEN skip them on mptables too? */ | |
113 | ||
114 | } | |
115 | ||
26adcfbf AH |
116 | #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC) |
117 | static u32 __init ati_ixp4x0_rev(int num, int slot, int func) | |
33fb0e4e AH |
118 | { |
119 | u32 d; | |
120 | u8 b; | |
121 | ||
122 | b = read_pci_config_byte(num, slot, func, 0xac); | |
123 | b &= ~(1<<5); | |
124 | write_pci_config_byte(num, slot, func, 0xac, b); | |
125 | ||
126 | d = read_pci_config(num, slot, func, 0x70); | |
127 | d |= 1<<8; | |
128 | write_pci_config(num, slot, func, 0x70, d); | |
129 | ||
130 | d = read_pci_config(num, slot, func, 0x8); | |
131 | d &= 0xff; | |
132 | return d; | |
133 | } | |
134 | ||
135 | static void __init ati_bugs(int num, int slot, int func) | |
136 | { | |
33fb0e4e AH |
137 | u32 d; |
138 | u8 b; | |
139 | ||
140 | if (acpi_use_timer_override) | |
141 | return; | |
142 | ||
143 | d = ati_ixp4x0_rev(num, slot, func); | |
144 | if (d < 0x82) | |
145 | acpi_skip_timer_override = 1; | |
146 | else { | |
147 | /* check for IRQ0 interrupt swap */ | |
148 | outb(0x72, 0xcd6); b = inb(0xcd7); | |
149 | if (!(b & 0x2)) | |
150 | acpi_skip_timer_override = 1; | |
151 | } | |
152 | ||
153 | if (acpi_skip_timer_override) { | |
154 | printk(KERN_INFO "SB4X0 revision 0x%x\n", d); | |
155 | printk(KERN_INFO "Ignoring ACPI timer override.\n"); | |
156 | printk(KERN_INFO "If you got timer trouble " | |
157 | "try acpi_use_timer_override\n"); | |
158 | } | |
33fb0e4e AH |
159 | } |
160 | ||
26adcfbf AH |
161 | static u32 __init ati_sbx00_rev(int num, int slot, int func) |
162 | { | |
7f74f8f2 | 163 | u32 d; |
26adcfbf | 164 | |
26adcfbf AH |
165 | d = read_pci_config(num, slot, func, 0x8); |
166 | d &= 0xff; | |
26adcfbf AH |
167 | |
168 | return d; | |
169 | } | |
170 | ||
171 | static void __init ati_bugs_contd(int num, int slot, int func) | |
172 | { | |
173 | u32 d, rev; | |
174 | ||
26adcfbf | 175 | rev = ati_sbx00_rev(num, slot, func); |
7f74f8f2 AH |
176 | if (rev >= 0x40) |
177 | acpi_fix_pin2_polarity = 1; | |
178 | ||
1d3e09a3 AH |
179 | /* |
180 | * SB600: revisions 0x11, 0x12, 0x13, 0x14, ... | |
181 | * SB700: revisions 0x39, 0x3a, ... | |
182 | * SB800: revisions 0x40, 0x41, ... | |
183 | */ | |
184 | if (rev >= 0x39) | |
26adcfbf AH |
185 | return; |
186 | ||
7f74f8f2 AH |
187 | if (acpi_use_timer_override) |
188 | return; | |
189 | ||
26adcfbf AH |
190 | /* check for IRQ0 interrupt swap */ |
191 | d = read_pci_config(num, slot, func, 0x64); | |
192 | if (!(d & (1<<14))) | |
193 | acpi_skip_timer_override = 1; | |
194 | ||
195 | if (acpi_skip_timer_override) { | |
196 | printk(KERN_INFO "SB600 revision 0x%x\n", rev); | |
197 | printk(KERN_INFO "Ignoring ACPI timer override.\n"); | |
198 | printk(KERN_INFO "If you got timer trouble " | |
199 | "try acpi_use_timer_override\n"); | |
200 | } | |
201 | } | |
202 | #else | |
203 | static void __init ati_bugs(int num, int slot, int func) | |
204 | { | |
205 | } | |
206 | ||
207 | static void __init ati_bugs_contd(int num, int slot, int func) | |
208 | { | |
209 | } | |
210 | #endif | |
211 | ||
03bbcb2e NH |
212 | static void __init intel_remapping_check(int num, int slot, int func) |
213 | { | |
214 | u8 revision; | |
803075db | 215 | u16 device; |
03bbcb2e | 216 | |
803075db | 217 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); |
03bbcb2e NH |
218 | revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID); |
219 | ||
220 | /* | |
6f8a1b33 NH |
221 | * Revision <= 13 of all triggering devices id in this quirk |
222 | * have a problem draining interrupts when irq remapping is | |
223 | * enabled, and should be flagged as broken. Additionally | |
224 | * revision 0x22 of device id 0x3405 has this problem. | |
03bbcb2e | 225 | */ |
6f8a1b33 | 226 | if (revision <= 0x13) |
03bbcb2e | 227 | set_irq_remapping_broken(); |
6f8a1b33 | 228 | else if (device == 0x3405 && revision == 0x22) |
803075db | 229 | set_irq_remapping_broken(); |
03bbcb2e NH |
230 | } |
231 | ||
814c5f1f JB |
232 | /* |
233 | * Systems with Intel graphics controllers set aside memory exclusively | |
234 | * for gfx driver use. This memory is not marked in the E820 as reserved | |
235 | * or as RAM, and so is subject to overlap from E820 manipulation later | |
236 | * in the boot process. On some systems, MMIO space is allocated on top, | |
237 | * despite the efforts of the "RAM buffer" approach, which simply rounds | |
238 | * memory boundaries up to 64M to try to catch space that may decode | |
239 | * as RAM and so is not suitable for MMIO. | |
814c5f1f | 240 | */ |
814c5f1f | 241 | |
86e58762 | 242 | #define KB(x) ((x) * 1024UL) |
814c5f1f | 243 | #define MB(x) (KB (KB (x))) |
814c5f1f | 244 | |
a4dff769 VS |
245 | static size_t __init i830_tseg_size(void) |
246 | { | |
c0dd3460 | 247 | u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC); |
a4dff769 | 248 | |
c0dd3460 | 249 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
250 | return 0; |
251 | ||
c0dd3460 | 252 | if (esmramc & I830_TSEG_SIZE_1M) |
a4dff769 VS |
253 | return MB(1); |
254 | else | |
255 | return KB(512); | |
256 | } | |
257 | ||
258 | static size_t __init i845_tseg_size(void) | |
259 | { | |
c0dd3460 JL |
260 | u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC); |
261 | u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK; | |
a4dff769 | 262 | |
c0dd3460 | 263 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
264 | return 0; |
265 | ||
c0dd3460 JL |
266 | switch (tseg_size) { |
267 | case I845_TSEG_SIZE_512K: return KB(512); | |
268 | case I845_TSEG_SIZE_1M: return MB(1); | |
a4dff769 | 269 | default: |
c0dd3460 | 270 | WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc); |
a4dff769 | 271 | } |
c0dd3460 | 272 | return 0; |
a4dff769 VS |
273 | } |
274 | ||
275 | static size_t __init i85x_tseg_size(void) | |
276 | { | |
c0dd3460 | 277 | u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC); |
a4dff769 | 278 | |
c0dd3460 | 279 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
280 | return 0; |
281 | ||
282 | return MB(1); | |
283 | } | |
284 | ||
285 | static size_t __init i830_mem_size(void) | |
286 | { | |
287 | return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); | |
288 | } | |
289 | ||
290 | static size_t __init i85x_mem_size(void) | |
291 | { | |
292 | return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); | |
293 | } | |
294 | ||
295 | /* | |
296 | * On 830/845/85x the stolen memory base isn't available in any | |
297 | * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size. | |
298 | */ | |
c0dd3460 JL |
299 | static phys_addr_t __init i830_stolen_base(int num, int slot, int func, |
300 | size_t stolen_size) | |
a4dff769 | 301 | { |
c0dd3460 | 302 | return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size; |
a4dff769 VS |
303 | } |
304 | ||
c0dd3460 JL |
305 | static phys_addr_t __init i845_stolen_base(int num, int slot, int func, |
306 | size_t stolen_size) | |
a4dff769 | 307 | { |
c0dd3460 | 308 | return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size; |
a4dff769 VS |
309 | } |
310 | ||
c0dd3460 JL |
311 | static phys_addr_t __init i85x_stolen_base(int num, int slot, int func, |
312 | size_t stolen_size) | |
a4dff769 | 313 | { |
c0dd3460 | 314 | return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size; |
a4dff769 VS |
315 | } |
316 | ||
c0dd3460 JL |
317 | static phys_addr_t __init i865_stolen_base(int num, int slot, int func, |
318 | size_t stolen_size) | |
a4dff769 | 319 | { |
c0dd3460 JL |
320 | u16 toud; |
321 | ||
a4dff769 VS |
322 | /* |
323 | * FIXME is the graphics stolen memory region | |
324 | * always at TOUD? Ie. is it always the last | |
325 | * one to be allocated by the BIOS? | |
326 | */ | |
c0dd3460 JL |
327 | toud = read_pci_config_16(0, 0, 0, I865_TOUD); |
328 | ||
329 | return (phys_addr_t)toud << 16; | |
330 | } | |
331 | ||
332 | static phys_addr_t __init gen3_stolen_base(int num, int slot, int func, | |
333 | size_t stolen_size) | |
334 | { | |
335 | u32 bsm; | |
336 | ||
337 | /* Almost universally we can find the Graphics Base of Stolen Memory | |
338 | * at register BSM (0x5c) in the igfx configuration space. On a few | |
339 | * (desktop) machines this is also mirrored in the bridge device at | |
340 | * different locations, or in the MCHBAR. | |
341 | */ | |
342 | bsm = read_pci_config(num, slot, func, INTEL_BSM); | |
343 | ||
344 | return (phys_addr_t)bsm & INTEL_BSM_MASK; | |
a4dff769 VS |
345 | } |
346 | ||
347 | static size_t __init i830_stolen_size(int num, int slot, int func) | |
348 | { | |
a4dff769 | 349 | u16 gmch_ctrl; |
c0dd3460 | 350 | u16 gms; |
a4dff769 VS |
351 | |
352 | gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); | |
c0dd3460 JL |
353 | gms = gmch_ctrl & I830_GMCH_GMS_MASK; |
354 | ||
355 | switch (gms) { | |
356 | case I830_GMCH_GMS_STOLEN_512: return KB(512); | |
357 | case I830_GMCH_GMS_STOLEN_1024: return MB(1); | |
358 | case I830_GMCH_GMS_STOLEN_8192: return MB(8); | |
359 | /* local memory isn't part of the normal address space */ | |
360 | case I830_GMCH_GMS_LOCAL: return 0; | |
a4dff769 | 361 | default: |
c0dd3460 | 362 | WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); |
a4dff769 VS |
363 | } |
364 | ||
c0dd3460 | 365 | return 0; |
a4dff769 VS |
366 | } |
367 | ||
814c5f1f JB |
368 | static size_t __init gen3_stolen_size(int num, int slot, int func) |
369 | { | |
814c5f1f | 370 | u16 gmch_ctrl; |
c0dd3460 | 371 | u16 gms; |
814c5f1f JB |
372 | |
373 | gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); | |
c0dd3460 JL |
374 | gms = gmch_ctrl & I855_GMCH_GMS_MASK; |
375 | ||
376 | switch (gms) { | |
377 | case I855_GMCH_GMS_STOLEN_1M: return MB(1); | |
378 | case I855_GMCH_GMS_STOLEN_4M: return MB(4); | |
379 | case I855_GMCH_GMS_STOLEN_8M: return MB(8); | |
380 | case I855_GMCH_GMS_STOLEN_16M: return MB(16); | |
381 | case I855_GMCH_GMS_STOLEN_32M: return MB(32); | |
382 | case I915_GMCH_GMS_STOLEN_48M: return MB(48); | |
383 | case I915_GMCH_GMS_STOLEN_64M: return MB(64); | |
384 | case G33_GMCH_GMS_STOLEN_128M: return MB(128); | |
385 | case G33_GMCH_GMS_STOLEN_256M: return MB(256); | |
386 | case INTEL_GMCH_GMS_STOLEN_96M: return MB(96); | |
387 | case INTEL_GMCH_GMS_STOLEN_160M:return MB(160); | |
388 | case INTEL_GMCH_GMS_STOLEN_224M:return MB(224); | |
389 | case INTEL_GMCH_GMS_STOLEN_352M:return MB(352); | |
814c5f1f | 390 | default: |
c0dd3460 | 391 | WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); |
814c5f1f JB |
392 | } |
393 | ||
c0dd3460 | 394 | return 0; |
814c5f1f JB |
395 | } |
396 | ||
397 | static size_t __init gen6_stolen_size(int num, int slot, int func) | |
398 | { | |
399 | u16 gmch_ctrl; | |
c0dd3460 | 400 | u16 gms; |
814c5f1f JB |
401 | |
402 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 403 | gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; |
814c5f1f | 404 | |
c0dd3460 | 405 | return (size_t)gms * MB(32); |
814c5f1f JB |
406 | } |
407 | ||
36dfcea4 | 408 | static size_t __init gen8_stolen_size(int num, int slot, int func) |
9459d252 BW |
409 | { |
410 | u16 gmch_ctrl; | |
c0dd3460 | 411 | u16 gms; |
9459d252 BW |
412 | |
413 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 JL |
414 | gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; |
415 | ||
416 | return (size_t)gms * MB(32); | |
9459d252 BW |
417 | } |
418 | ||
3e3b2c39 DL |
419 | static size_t __init chv_stolen_size(int num, int slot, int func) |
420 | { | |
421 | u16 gmch_ctrl; | |
c0dd3460 | 422 | u16 gms; |
3e3b2c39 DL |
423 | |
424 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 425 | gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; |
3e3b2c39 DL |
426 | |
427 | /* | |
428 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
429 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
430 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
431 | */ | |
c0dd3460 JL |
432 | if (gms < 0x11) |
433 | return (size_t)gms * MB(32); | |
434 | else if (gms < 0x17) | |
435 | return (size_t)(gms - 0x11 + 2) * MB(4); | |
3e3b2c39 | 436 | else |
c0dd3460 | 437 | return (size_t)(gms - 0x17 + 9) * MB(4); |
3e3b2c39 | 438 | } |
52ca7045 | 439 | |
66375014 DL |
440 | static size_t __init gen9_stolen_size(int num, int slot, int func) |
441 | { | |
442 | u16 gmch_ctrl; | |
c0dd3460 | 443 | u16 gms; |
66375014 DL |
444 | |
445 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 446 | gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; |
66375014 | 447 | |
c0dd3460 JL |
448 | /* 0x0 to 0xef: 32MB increments starting at 0MB */ |
449 | /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ | |
450 | if (gms < 0xf0) | |
451 | return (size_t)gms * MB(32); | |
66375014 | 452 | else |
c0dd3460 | 453 | return (size_t)(gms - 0xf0 + 1) * MB(4); |
66375014 DL |
454 | } |
455 | ||
ee0629cf JL |
456 | struct intel_early_ops { |
457 | size_t (*stolen_size)(int num, int slot, int func); | |
458 | phys_addr_t (*stolen_base)(int num, int slot, int func, size_t size); | |
459 | }; | |
66375014 | 460 | |
ee0629cf JL |
461 | static const struct intel_early_ops i830_early_ops __initconst = { |
462 | .stolen_base = i830_stolen_base, | |
463 | .stolen_size = i830_stolen_size, | |
a4dff769 VS |
464 | }; |
465 | ||
ee0629cf JL |
466 | static const struct intel_early_ops i845_early_ops __initconst = { |
467 | .stolen_base = i845_stolen_base, | |
468 | .stolen_size = i830_stolen_size, | |
a4dff769 VS |
469 | }; |
470 | ||
ee0629cf JL |
471 | static const struct intel_early_ops i85x_early_ops __initconst = { |
472 | .stolen_base = i85x_stolen_base, | |
473 | .stolen_size = gen3_stolen_size, | |
a4dff769 VS |
474 | }; |
475 | ||
ee0629cf JL |
476 | static const struct intel_early_ops i865_early_ops __initconst = { |
477 | .stolen_base = i865_stolen_base, | |
478 | .stolen_size = gen3_stolen_size, | |
a4dff769 VS |
479 | }; |
480 | ||
ee0629cf JL |
481 | static const struct intel_early_ops gen3_early_ops __initconst = { |
482 | .stolen_base = gen3_stolen_base, | |
483 | .stolen_size = gen3_stolen_size, | |
52ca7045 VS |
484 | }; |
485 | ||
ee0629cf JL |
486 | static const struct intel_early_ops gen6_early_ops __initconst = { |
487 | .stolen_base = gen3_stolen_base, | |
488 | .stolen_size = gen6_stolen_size, | |
52ca7045 VS |
489 | }; |
490 | ||
ee0629cf JL |
491 | static const struct intel_early_ops gen8_early_ops __initconst = { |
492 | .stolen_base = gen3_stolen_base, | |
493 | .stolen_size = gen8_stolen_size, | |
52ca7045 | 494 | }; |
814c5f1f | 495 | |
ee0629cf JL |
496 | static const struct intel_early_ops gen9_early_ops __initconst = { |
497 | .stolen_base = gen3_stolen_base, | |
498 | .stolen_size = gen9_stolen_size, | |
66375014 DL |
499 | }; |
500 | ||
ee0629cf JL |
501 | static const struct intel_early_ops chv_early_ops __initconst = { |
502 | .stolen_base = gen3_stolen_base, | |
503 | .stolen_size = chv_stolen_size, | |
3e3b2c39 DL |
504 | }; |
505 | ||
ee0629cf JL |
506 | static const struct pci_device_id intel_early_ids[] __initconst = { |
507 | INTEL_I830_IDS(&i830_early_ops), | |
508 | INTEL_I845G_IDS(&i845_early_ops), | |
509 | INTEL_I85X_IDS(&i85x_early_ops), | |
510 | INTEL_I865G_IDS(&i865_early_ops), | |
511 | INTEL_I915G_IDS(&gen3_early_ops), | |
512 | INTEL_I915GM_IDS(&gen3_early_ops), | |
513 | INTEL_I945G_IDS(&gen3_early_ops), | |
514 | INTEL_I945GM_IDS(&gen3_early_ops), | |
515 | INTEL_VLV_M_IDS(&gen6_early_ops), | |
516 | INTEL_VLV_D_IDS(&gen6_early_ops), | |
517 | INTEL_PINEVIEW_IDS(&gen3_early_ops), | |
518 | INTEL_I965G_IDS(&gen3_early_ops), | |
519 | INTEL_G33_IDS(&gen3_early_ops), | |
520 | INTEL_I965GM_IDS(&gen3_early_ops), | |
521 | INTEL_GM45_IDS(&gen3_early_ops), | |
522 | INTEL_G45_IDS(&gen3_early_ops), | |
523 | INTEL_IRONLAKE_D_IDS(&gen3_early_ops), | |
524 | INTEL_IRONLAKE_M_IDS(&gen3_early_ops), | |
525 | INTEL_SNB_D_IDS(&gen6_early_ops), | |
526 | INTEL_SNB_M_IDS(&gen6_early_ops), | |
527 | INTEL_IVB_M_IDS(&gen6_early_ops), | |
528 | INTEL_IVB_D_IDS(&gen6_early_ops), | |
529 | INTEL_HSW_D_IDS(&gen6_early_ops), | |
530 | INTEL_HSW_M_IDS(&gen6_early_ops), | |
531 | INTEL_BDW_M_IDS(&gen8_early_ops), | |
532 | INTEL_BDW_D_IDS(&gen8_early_ops), | |
533 | INTEL_CHV_IDS(&chv_early_ops), | |
534 | INTEL_SKL_IDS(&gen9_early_ops), | |
535 | INTEL_BXT_IDS(&gen9_early_ops), | |
536 | INTEL_KBL_IDS(&gen9_early_ops), | |
814c5f1f JB |
537 | }; |
538 | ||
ee0629cf JL |
539 | static void __init |
540 | intel_graphics_stolen(int num, int slot, int func, | |
541 | const struct intel_early_ops *early_ops) | |
814c5f1f | 542 | { |
01e5d3b4 | 543 | phys_addr_t base, end; |
814c5f1f | 544 | size_t size; |
ee0629cf JL |
545 | |
546 | size = early_ops->stolen_size(num, slot, func); | |
547 | base = early_ops->stolen_base(num, slot, func, size); | |
548 | ||
549 | if (!size || !base) | |
550 | return; | |
551 | ||
01e5d3b4 CW |
552 | end = base + size - 1; |
553 | printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n", | |
554 | &base, &end); | |
ee0629cf JL |
555 | |
556 | /* Mark this space as reserved */ | |
557 | e820_add_region(base, size, E820_RESERVED); | |
558 | sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map); | |
559 | } | |
560 | ||
561 | static void __init intel_graphics_quirks(int num, int slot, int func) | |
562 | { | |
563 | const struct intel_early_ops *early_ops; | |
564 | u16 device; | |
814c5f1f | 565 | int i; |
814c5f1f JB |
566 | |
567 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); | |
ee0629cf JL |
568 | |
569 | for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) { | |
570 | kernel_ulong_t driver_data = intel_early_ids[i].driver_data; | |
571 | ||
572 | if (intel_early_ids[i].device != device) | |
573 | continue; | |
574 | ||
575 | early_ops = (typeof(early_ops))driver_data; | |
576 | ||
577 | intel_graphics_stolen(num, slot, func, early_ops); | |
578 | ||
579 | return; | |
814c5f1f JB |
580 | } |
581 | } | |
582 | ||
62187910 FT |
583 | static void __init force_disable_hpet(int num, int slot, int func) |
584 | { | |
585 | #ifdef CONFIG_HPET_TIMER | |
3d45ac4b | 586 | boot_hpet_disable = true; |
62187910 FT |
587 | pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n"); |
588 | #endif | |
589 | } | |
590 | ||
abb2bafd LW |
591 | #define BCM4331_MMIO_SIZE 16384 |
592 | #define BCM4331_PM_CAP 0x40 | |
593 | #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg) | |
594 | #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg) | |
595 | ||
596 | static void __init apple_airport_reset(int bus, int slot, int func) | |
597 | { | |
598 | void __iomem *mmio; | |
599 | u16 pmcsr; | |
600 | u64 addr; | |
601 | int i; | |
602 | ||
603 | if (!dmi_match(DMI_SYS_VENDOR, "Apple Inc.")) | |
604 | return; | |
605 | ||
606 | /* Card may have been put into PCI_D3hot by grub quirk */ | |
607 | pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); | |
608 | ||
609 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { | |
610 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
611 | write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr); | |
612 | mdelay(10); | |
613 | ||
614 | pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); | |
615 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { | |
616 | dev_err("Cannot power up Apple AirPort card\n"); | |
617 | return; | |
618 | } | |
619 | } | |
620 | ||
621 | addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0); | |
622 | addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32; | |
623 | addr &= PCI_BASE_ADDRESS_MEM_MASK; | |
624 | ||
625 | mmio = early_ioremap(addr, BCM4331_MMIO_SIZE); | |
626 | if (!mmio) { | |
627 | dev_err("Cannot iomap Apple AirPort card\n"); | |
628 | return; | |
629 | } | |
630 | ||
631 | pr_info("Resetting Apple AirPort card (left enabled by EFI)\n"); | |
632 | ||
633 | for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++) | |
634 | udelay(10); | |
635 | ||
636 | bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); | |
637 | bcma_aread32(BCMA_RESET_CTL); | |
638 | udelay(1); | |
639 | ||
640 | bcma_awrite32(BCMA_RESET_CTL, 0); | |
641 | bcma_aread32(BCMA_RESET_CTL); | |
642 | udelay(10); | |
643 | ||
644 | early_iounmap(mmio, BCM4331_MMIO_SIZE); | |
645 | } | |
62187910 | 646 | |
c6b48324 NH |
647 | #define QFLAG_APPLY_ONCE 0x1 |
648 | #define QFLAG_APPLIED 0x2 | |
649 | #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) | |
dfa4698c | 650 | struct chipset { |
c6b48324 NH |
651 | u32 vendor; |
652 | u32 device; | |
653 | u32 class; | |
654 | u32 class_mask; | |
655 | u32 flags; | |
656 | void (*f)(int num, int slot, int func); | |
dfa4698c AK |
657 | }; |
658 | ||
c993c735 | 659 | static struct chipset early_qrk[] __initdata = { |
c6b48324 NH |
660 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
661 | PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs }, | |
662 | { PCI_VENDOR_ID_VIA, PCI_ANY_ID, | |
663 | PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs }, | |
c6b48324 NH |
664 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, |
665 | PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config }, | |
33fb0e4e AH |
666 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, |
667 | PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, | |
26adcfbf AH |
668 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
669 | PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, | |
03bbcb2e NH |
670 | { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST, |
671 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
803075db NH |
672 | { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST, |
673 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
03bbcb2e NH |
674 | { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST, |
675 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
814c5f1f | 676 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID, |
ee0629cf | 677 | QFLAG_APPLY_ONCE, intel_graphics_quirks }, |
62187910 | 678 | /* |
b58d9307 FT |
679 | * HPET on the current version of the Baytrail platform has accuracy |
680 | * problems: it will halt in deep idle state - so we disable it. | |
681 | * | |
682 | * More details can be found in section 18.10.1.3 of the datasheet: | |
683 | * | |
684 | * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf | |
62187910 FT |
685 | */ |
686 | { PCI_VENDOR_ID_INTEL, 0x0f00, | |
687 | PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, | |
abb2bafd LW |
688 | { PCI_VENDOR_ID_BROADCOM, 0x4331, |
689 | PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, | |
dfa4698c AK |
690 | {} |
691 | }; | |
692 | ||
850c3210 LW |
693 | static void __init early_pci_scan_bus(int bus); |
694 | ||
15650a2f JB |
695 | /** |
696 | * check_dev_quirk - apply early quirks to a given PCI device | |
697 | * @num: bus number | |
698 | * @slot: slot number | |
699 | * @func: PCI function | |
700 | * | |
701 | * Check the vendor & device ID against the early quirks table. | |
702 | * | |
850c3210 | 703 | * If the device is single function, let early_pci_scan_bus() know so we don't |
15650a2f JB |
704 | * poke at this device again. |
705 | */ | |
706 | static int __init check_dev_quirk(int num, int slot, int func) | |
7bcbc78d NH |
707 | { |
708 | u16 class; | |
709 | u16 vendor; | |
710 | u16 device; | |
711 | u8 type; | |
850c3210 | 712 | u8 sec; |
7bcbc78d NH |
713 | int i; |
714 | ||
715 | class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE); | |
716 | ||
717 | if (class == 0xffff) | |
15650a2f | 718 | return -1; /* no class, treat as single function */ |
7bcbc78d NH |
719 | |
720 | vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID); | |
721 | ||
722 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); | |
723 | ||
724 | for (i = 0; early_qrk[i].f != NULL; i++) { | |
725 | if (((early_qrk[i].vendor == PCI_ANY_ID) || | |
726 | (early_qrk[i].vendor == vendor)) && | |
727 | ((early_qrk[i].device == PCI_ANY_ID) || | |
728 | (early_qrk[i].device == device)) && | |
729 | (!((early_qrk[i].class ^ class) & | |
730 | early_qrk[i].class_mask))) { | |
731 | if ((early_qrk[i].flags & | |
732 | QFLAG_DONE) != QFLAG_DONE) | |
733 | early_qrk[i].f(num, slot, func); | |
734 | early_qrk[i].flags |= QFLAG_APPLIED; | |
735 | } | |
736 | } | |
737 | ||
738 | type = read_pci_config_byte(num, slot, func, | |
739 | PCI_HEADER_TYPE); | |
850c3210 LW |
740 | |
741 | if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { | |
742 | sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS); | |
743 | if (sec > num) | |
744 | early_pci_scan_bus(sec); | |
745 | } | |
746 | ||
7bcbc78d | 747 | if (!(type & 0x80)) |
15650a2f JB |
748 | return -1; |
749 | ||
750 | return 0; | |
7bcbc78d NH |
751 | } |
752 | ||
850c3210 | 753 | static void __init early_pci_scan_bus(int bus) |
dfa4698c | 754 | { |
8659c406 | 755 | int slot, func; |
0637a70a | 756 | |
dfa4698c | 757 | /* Poor man's PCI discovery */ |
8659c406 AK |
758 | for (slot = 0; slot < 32; slot++) |
759 | for (func = 0; func < 8; func++) { | |
760 | /* Only probe function 0 on single fn devices */ | |
850c3210 | 761 | if (check_dev_quirk(bus, slot, func)) |
8659c406 AK |
762 | break; |
763 | } | |
dfa4698c | 764 | } |
850c3210 LW |
765 | |
766 | void __init early_quirks(void) | |
767 | { | |
768 | if (!early_pci_allowed()) | |
769 | return; | |
770 | ||
771 | early_pci_scan_bus(0); | |
772 | } |