Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
78f7f1e5 | 8 | #include <asm/fpu/internal.h> |
1da177e4 | 9 | |
085cc281 IM |
10 | /* |
11 | * Track whether the kernel is using the FPU state | |
12 | * currently. | |
13 | * | |
14 | * This flag is used: | |
15 | * | |
16 | * - by IRQ context code to potentially use the FPU | |
17 | * if it's unused. | |
18 | * | |
19 | * - to debug kernel_fpu_begin()/end() correctness | |
20 | */ | |
14e153ef ON |
21 | static DEFINE_PER_CPU(bool, in_kernel_fpu); |
22 | ||
b0c050c5 | 23 | /* |
36b544dc | 24 | * Track which context is using the FPU on the CPU: |
b0c050c5 | 25 | */ |
36b544dc | 26 | DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
b0c050c5 | 27 | |
416d49ac | 28 | static void kernel_fpu_disable(void) |
7575637a ON |
29 | { |
30 | WARN_ON(this_cpu_read(in_kernel_fpu)); | |
31 | this_cpu_write(in_kernel_fpu, true); | |
32 | } | |
33 | ||
416d49ac | 34 | static void kernel_fpu_enable(void) |
7575637a | 35 | { |
3103ae3a | 36 | WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu)); |
7575637a ON |
37 | this_cpu_write(in_kernel_fpu, false); |
38 | } | |
39 | ||
085cc281 IM |
40 | static bool kernel_fpu_disabled(void) |
41 | { | |
42 | return this_cpu_read(in_kernel_fpu); | |
43 | } | |
44 | ||
8546c008 LT |
45 | /* |
46 | * Were we in an interrupt that interrupted kernel mode? | |
47 | * | |
304bceda | 48 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
49 | * pair does nothing at all: the thread must not have fpu (so |
50 | * that we don't try to save the FPU state), and TS must | |
51 | * be set (so that the clts/stts pair does nothing that is | |
52 | * visible in the interrupted kernel thread). | |
5187b28f | 53 | * |
4b2e762e ON |
54 | * Except for the eagerfpu case when we return true; in the likely case |
55 | * the thread has FPU but we are not going to set/clear TS. | |
8546c008 | 56 | */ |
416d49ac | 57 | static bool interrupted_kernel_fpu_idle(void) |
8546c008 | 58 | { |
085cc281 | 59 | if (kernel_fpu_disabled()) |
14e153ef ON |
60 | return false; |
61 | ||
5d2bd700 | 62 | if (use_eager_fpu()) |
4b2e762e | 63 | return true; |
304bceda | 64 | |
d5cea9b0 | 65 | return !current->thread.fpu.fpregs_active && (read_cr0() & X86_CR0_TS); |
8546c008 LT |
66 | } |
67 | ||
68 | /* | |
69 | * Were we in user mode (or vm86 mode) when we were | |
70 | * interrupted? | |
71 | * | |
72 | * Doing kernel_fpu_begin/end() is ok if we are running | |
73 | * in an interrupt context from user mode - we'll just | |
74 | * save the FPU state as required. | |
75 | */ | |
416d49ac | 76 | static bool interrupted_user_mode(void) |
8546c008 LT |
77 | { |
78 | struct pt_regs *regs = get_irq_regs(); | |
f39b6f0e | 79 | return regs && user_mode(regs); |
8546c008 LT |
80 | } |
81 | ||
82 | /* | |
83 | * Can we use the FPU in kernel mode with the | |
84 | * whole "kernel_fpu_begin/end()" sequence? | |
85 | * | |
86 | * It's always ok in process context (ie "not interrupt") | |
87 | * but it is sometimes ok even from an irq. | |
88 | */ | |
89 | bool irq_fpu_usable(void) | |
90 | { | |
91 | return !in_interrupt() || | |
92 | interrupted_user_mode() || | |
93 | interrupted_kernel_fpu_idle(); | |
94 | } | |
95 | EXPORT_SYMBOL(irq_fpu_usable); | |
96 | ||
b1a74bf8 | 97 | void __kernel_fpu_begin(void) |
8546c008 | 98 | { |
36b544dc | 99 | struct fpu *fpu = ¤t->thread.fpu; |
8546c008 | 100 | |
3103ae3a | 101 | kernel_fpu_disable(); |
14e153ef | 102 | |
d5cea9b0 | 103 | if (fpu->fpregs_active) { |
276983f8 | 104 | fpu_save_init(fpu); |
7aeccb83 | 105 | } else { |
36b544dc | 106 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
7aeccb83 ON |
107 | if (!use_eager_fpu()) |
108 | clts(); | |
8546c008 LT |
109 | } |
110 | } | |
b1a74bf8 | 111 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 112 | |
b1a74bf8 | 113 | void __kernel_fpu_end(void) |
8546c008 | 114 | { |
af2d94fd | 115 | struct fpu *fpu = ¤t->thread.fpu; |
33a3ebdc | 116 | |
d5cea9b0 | 117 | if (fpu->fpregs_active) { |
11f2d50b | 118 | if (WARN_ON(restore_fpu_checking(fpu))) |
af2d94fd | 119 | fpu_reset_state(fpu); |
33a3ebdc | 120 | } else if (!use_eager_fpu()) { |
304bceda | 121 | stts(); |
731bd6a9 | 122 | } |
14e153ef | 123 | |
3103ae3a | 124 | kernel_fpu_enable(); |
8546c008 | 125 | } |
b1a74bf8 | 126 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 | 127 | |
a4d8fc2e | 128 | static void __save_fpu(struct fpu *fpu) |
2d75bcf3 IM |
129 | { |
130 | if (use_xsave()) { | |
131 | if (unlikely(system_state == SYSTEM_BOOTING)) | |
a4d8fc2e | 132 | xsave_state_booting(&fpu->state->xsave); |
2d75bcf3 | 133 | else |
a4d8fc2e | 134 | xsave_state(&fpu->state->xsave); |
2d75bcf3 | 135 | } else { |
a4d8fc2e | 136 | fpu_fxsave(fpu); |
2d75bcf3 IM |
137 | } |
138 | } | |
139 | ||
4af08f2f IM |
140 | /* |
141 | * Save the FPU state (initialize it if necessary): | |
87cdb98a IM |
142 | * |
143 | * This only ever gets called for the current task. | |
4af08f2f | 144 | */ |
0c070595 | 145 | void fpu__save(struct fpu *fpu) |
8546c008 | 146 | { |
0c070595 | 147 | WARN_ON(fpu != ¤t->thread.fpu); |
87cdb98a | 148 | |
8546c008 | 149 | preempt_disable(); |
d5cea9b0 | 150 | if (fpu->fpregs_active) { |
1a2a7f4e | 151 | if (use_eager_fpu()) { |
a4d8fc2e | 152 | __save_fpu(fpu); |
1a2a7f4e | 153 | } else { |
276983f8 | 154 | fpu_save_init(fpu); |
35191e3f | 155 | __thread_fpu_end(fpu); |
1a2a7f4e | 156 | } |
a9241ea5 | 157 | } |
8546c008 LT |
158 | preempt_enable(); |
159 | } | |
4af08f2f | 160 | EXPORT_SYMBOL_GPL(fpu__save); |
8546c008 | 161 | |
c0ee2cf6 | 162 | void fpstate_init(struct fpu *fpu) |
1da177e4 | 163 | { |
60e019eb | 164 | if (!cpu_has_fpu) { |
86603283 AK |
165 | finit_soft_fpu(&fpu->state->soft); |
166 | return; | |
e8a496ac | 167 | } |
e8a496ac | 168 | |
1d23c451 ON |
169 | memset(fpu->state, 0, xstate_size); |
170 | ||
1da177e4 | 171 | if (cpu_has_fxsr) { |
5d2bd700 | 172 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 173 | } else { |
86603283 | 174 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
175 | fp->cwd = 0xffff037fu; |
176 | fp->swd = 0xffff0000u; | |
177 | fp->twd = 0xffffffffu; | |
178 | fp->fos = 0xffff0000u; | |
1da177e4 | 179 | } |
86603283 | 180 | } |
c0ee2cf6 | 181 | EXPORT_SYMBOL_GPL(fpstate_init); |
86603283 | 182 | |
8ffb53ab IM |
183 | /* |
184 | * FPU state allocation: | |
185 | */ | |
f55f88e2 | 186 | static struct kmem_cache *task_xstate_cachep; |
8ffb53ab IM |
187 | |
188 | void fpstate_cache_init(void) | |
189 | { | |
190 | task_xstate_cachep = | |
191 | kmem_cache_create("task_xstate", xstate_size, | |
192 | __alignof__(union thread_xstate), | |
193 | SLAB_PANIC | SLAB_NOTRACK, NULL); | |
194 | setup_xstate_comp(); | |
195 | } | |
196 | ||
ed97b085 | 197 | int fpstate_alloc(struct fpu *fpu) |
6fbe6712 IM |
198 | { |
199 | if (fpu->state) | |
200 | return 0; | |
ed97b085 | 201 | |
6fbe6712 IM |
202 | fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL); |
203 | if (!fpu->state) | |
204 | return -ENOMEM; | |
ed97b085 IM |
205 | |
206 | /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */ | |
6fbe6712 | 207 | WARN_ON((unsigned long)fpu->state & 15); |
ed97b085 | 208 | |
6fbe6712 IM |
209 | return 0; |
210 | } | |
ed97b085 | 211 | EXPORT_SYMBOL_GPL(fpstate_alloc); |
6fbe6712 | 212 | |
5a12bf63 IM |
213 | void fpstate_free(struct fpu *fpu) |
214 | { | |
215 | if (fpu->state) { | |
216 | kmem_cache_free(task_xstate_cachep, fpu->state); | |
217 | fpu->state = NULL; | |
218 | } | |
219 | } | |
220 | EXPORT_SYMBOL_GPL(fpstate_free); | |
221 | ||
bfd6fc05 IM |
222 | /* |
223 | * Copy the current task's FPU state to a new task's FPU context. | |
224 | * | |
225 | * In the 'eager' case we just save to the destination context. | |
226 | * | |
227 | * In the 'lazy' case we save to the source context, mark the FPU lazy | |
228 | * via stts() and copy the source context into the destination context. | |
229 | */ | |
f9bc977f | 230 | static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu) |
e102f30f | 231 | { |
f9bc977f | 232 | WARN_ON(src_fpu != ¤t->thread.fpu); |
bfd6fc05 | 233 | |
e102f30f | 234 | if (use_eager_fpu()) { |
f9bc977f | 235 | memset(&dst_fpu->state->xsave, 0, xstate_size); |
a4d8fc2e | 236 | __save_fpu(dst_fpu); |
e102f30f | 237 | } else { |
0c070595 | 238 | fpu__save(src_fpu); |
a4d8fc2e | 239 | memcpy(dst_fpu->state, src_fpu->state, xstate_size); |
e102f30f IM |
240 | } |
241 | } | |
242 | ||
c69e098b | 243 | int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu) |
a752b53d | 244 | { |
c69e098b | 245 | dst_fpu->counter = 0; |
d5cea9b0 | 246 | dst_fpu->fpregs_active = 0; |
c69e098b IM |
247 | dst_fpu->state = NULL; |
248 | dst_fpu->last_cpu = -1; | |
a752b53d | 249 | |
c5bedc68 IM |
250 | if (src_fpu->fpstate_active) { |
251 | int err = fpstate_alloc(dst_fpu); | |
a752b53d IM |
252 | |
253 | if (err) | |
254 | return err; | |
f9bc977f | 255 | fpu_copy(dst_fpu, src_fpu); |
a752b53d IM |
256 | } |
257 | return 0; | |
258 | } | |
259 | ||
97185c95 IM |
260 | /* |
261 | * Allocate the backing store for the current task's FPU registers | |
262 | * and initialize the registers themselves as well. | |
263 | * | |
264 | * Can fail. | |
265 | */ | |
db2b1d3a | 266 | int fpstate_alloc_init(struct fpu *fpu) |
97185c95 IM |
267 | { |
268 | int ret; | |
269 | ||
db2b1d3a | 270 | if (WARN_ON_ONCE(fpu != ¤t->thread.fpu)) |
97185c95 | 271 | return -EINVAL; |
c5bedc68 | 272 | if (WARN_ON_ONCE(fpu->fpstate_active)) |
97185c95 IM |
273 | return -EINVAL; |
274 | ||
275 | /* | |
276 | * Memory allocation at the first usage of the FPU and other state. | |
277 | */ | |
db2b1d3a | 278 | ret = fpstate_alloc(fpu); |
97185c95 IM |
279 | if (ret) |
280 | return ret; | |
281 | ||
db2b1d3a | 282 | fpstate_init(fpu); |
97185c95 IM |
283 | |
284 | /* Safe to do for the current task: */ | |
c5bedc68 | 285 | fpu->fpstate_active = 1; |
97185c95 IM |
286 | |
287 | return 0; | |
288 | } | |
289 | EXPORT_SYMBOL_GPL(fpstate_alloc_init); | |
290 | ||
86603283 | 291 | /* |
af7f8721 IM |
292 | * This function is called before we modify a stopped child's |
293 | * FPU state context. | |
294 | * | |
295 | * If the child has not used the FPU before then initialize its | |
296 | * FPU context. | |
297 | * | |
298 | * If the child has used the FPU before then unlazy it. | |
299 | * | |
300 | * [ After this function call, after the context is modified and | |
301 | * the child task is woken up, the child task will restore | |
302 | * the modified FPU state from the modified context. If we | |
303 | * didn't clear its lazy status here then the lazy in-registers | |
304 | * state pending on its former CPU could be restored, losing | |
305 | * the modifications. ] | |
306 | * | |
307 | * This function is also called before we read a stopped child's | |
308 | * FPU state - to make sure it's modified. | |
309 | * | |
310 | * TODO: A future optimization would be to skip the unlazying in | |
311 | * the read-only case, it's not strictly necessary for | |
312 | * read-only access to the context. | |
86603283 | 313 | */ |
cc08d545 | 314 | static int fpu__unlazy_stopped(struct fpu *child_fpu) |
86603283 AK |
315 | { |
316 | int ret; | |
317 | ||
cc08d545 | 318 | if (WARN_ON_ONCE(child_fpu == ¤t->thread.fpu)) |
67e97fc2 IM |
319 | return -EINVAL; |
320 | ||
c5bedc68 | 321 | if (child_fpu->fpstate_active) { |
cc08d545 | 322 | child_fpu->last_cpu = -1; |
86603283 AK |
323 | return 0; |
324 | } | |
325 | ||
44210111 | 326 | /* |
86603283 | 327 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 328 | */ |
cc08d545 | 329 | ret = fpstate_alloc(child_fpu); |
86603283 AK |
330 | if (ret) |
331 | return ret; | |
332 | ||
cc08d545 | 333 | fpstate_init(child_fpu); |
86603283 | 334 | |
071ae621 | 335 | /* Safe to do for stopped child tasks: */ |
c5bedc68 | 336 | child_fpu->fpstate_active = 1; |
071ae621 | 337 | |
aa283f49 | 338 | return 0; |
1da177e4 LT |
339 | } |
340 | ||
93b90712 | 341 | /* |
3a0aee48 | 342 | * 'fpu__restore()' saves the current math information in the |
93b90712 IM |
343 | * old math state array, and gets the new ones from the current task |
344 | * | |
345 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
346 | * Don't touch unless you *really* know how it works. | |
347 | * | |
348 | * Must be called with kernel preemption disabled (eg with local | |
349 | * local interrupts as in the case of do_device_not_available). | |
350 | */ | |
3a0aee48 | 351 | void fpu__restore(void) |
93b90712 IM |
352 | { |
353 | struct task_struct *tsk = current; | |
4540d3fa | 354 | struct fpu *fpu = &tsk->thread.fpu; |
93b90712 | 355 | |
c5bedc68 | 356 | if (!fpu->fpstate_active) { |
93b90712 IM |
357 | local_irq_enable(); |
358 | /* | |
359 | * does a slab alloc which can sleep | |
360 | */ | |
db2b1d3a | 361 | if (fpstate_alloc_init(fpu)) { |
93b90712 IM |
362 | /* |
363 | * ran out of memory! | |
364 | */ | |
365 | do_group_exit(SIGKILL); | |
366 | return; | |
367 | } | |
368 | local_irq_disable(); | |
369 | } | |
370 | ||
371 | /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */ | |
372 | kernel_fpu_disable(); | |
4540d3fa | 373 | __thread_fpu_begin(fpu); |
11f2d50b | 374 | if (unlikely(restore_fpu_checking(fpu))) { |
af2d94fd | 375 | fpu_reset_state(fpu); |
93b90712 IM |
376 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
377 | } else { | |
378 | tsk->thread.fpu.counter++; | |
379 | } | |
380 | kernel_fpu_enable(); | |
381 | } | |
3a0aee48 | 382 | EXPORT_SYMBOL_GPL(fpu__restore); |
93b90712 | 383 | |
2e8a3102 | 384 | void fpu__clear(struct task_struct *tsk) |
81683cc8 | 385 | { |
c5bedc68 IM |
386 | struct fpu *fpu = &tsk->thread.fpu; |
387 | ||
2e8a3102 | 388 | WARN_ON_ONCE(tsk != current); /* Almost certainly an anomaly */ |
4c138410 | 389 | |
81683cc8 IM |
390 | if (!use_eager_fpu()) { |
391 | /* FPU state will be reallocated lazily at the first use. */ | |
ca6787ba | 392 | drop_fpu(fpu); |
e11267c1 | 393 | fpstate_free(fpu); |
81683cc8 | 394 | } else { |
c5bedc68 | 395 | if (!fpu->fpstate_active) { |
81683cc8 | 396 | /* kthread execs. TODO: cleanup this horror. */ |
e11267c1 | 397 | if (WARN_ON(fpstate_alloc_init(fpu))) |
81683cc8 IM |
398 | force_sig(SIGKILL, tsk); |
399 | user_fpu_begin(); | |
400 | } | |
401 | restore_init_xstate(); | |
402 | } | |
403 | } | |
404 | ||
5b3efd50 | 405 | /* |
678eaf60 | 406 | * The xstateregs_active() routine is the same as the regset_fpregs_active() routine, |
5b3efd50 SS |
407 | * as the "regset->n" for the xstate regset will be updated based on the feature |
408 | * capabilites supported by the xsave. | |
409 | */ | |
678eaf60 | 410 | int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
44210111 | 411 | { |
c5bedc68 IM |
412 | struct fpu *target_fpu = &target->thread.fpu; |
413 | ||
414 | return target_fpu->fpstate_active ? regset->n : 0; | |
44210111 | 415 | } |
1da177e4 | 416 | |
678eaf60 | 417 | int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 418 | { |
c5bedc68 IM |
419 | struct fpu *target_fpu = &target->thread.fpu; |
420 | ||
421 | return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0; | |
44210111 | 422 | } |
1da177e4 | 423 | |
44210111 RM |
424 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
425 | unsigned int pos, unsigned int count, | |
426 | void *kbuf, void __user *ubuf) | |
427 | { | |
cc08d545 | 428 | struct fpu *fpu = &target->thread.fpu; |
aa283f49 SS |
429 | int ret; |
430 | ||
44210111 RM |
431 | if (!cpu_has_fxsr) |
432 | return -ENODEV; | |
433 | ||
cc08d545 | 434 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
435 | if (ret) |
436 | return ret; | |
44210111 | 437 | |
29104e10 SS |
438 | sanitize_i387_state(target); |
439 | ||
44210111 | 440 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 441 | &fpu->state->fxsave, 0, -1); |
1da177e4 | 442 | } |
44210111 RM |
443 | |
444 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
445 | unsigned int pos, unsigned int count, | |
446 | const void *kbuf, const void __user *ubuf) | |
447 | { | |
cc08d545 | 448 | struct fpu *fpu = &target->thread.fpu; |
44210111 RM |
449 | int ret; |
450 | ||
451 | if (!cpu_has_fxsr) | |
452 | return -ENODEV; | |
453 | ||
cc08d545 | 454 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
455 | if (ret) |
456 | return ret; | |
457 | ||
29104e10 SS |
458 | sanitize_i387_state(target); |
459 | ||
44210111 | 460 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 461 | &fpu->state->fxsave, 0, -1); |
44210111 RM |
462 | |
463 | /* | |
464 | * mxcsr reserved bits must be masked to zero for security reasons. | |
465 | */ | |
8dcea8db | 466 | fpu->state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 467 | |
42deec6f SS |
468 | /* |
469 | * update the header bits in the xsave header, indicating the | |
470 | * presence of FP and SSE state. | |
471 | */ | |
472 | if (cpu_has_xsave) | |
400e4b20 | 473 | fpu->state->xsave.header.xfeatures |= XSTATE_FPSSE; |
42deec6f | 474 | |
44210111 RM |
475 | return ret; |
476 | } | |
477 | ||
5b3efd50 SS |
478 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
479 | unsigned int pos, unsigned int count, | |
480 | void *kbuf, void __user *ubuf) | |
481 | { | |
cc08d545 | 482 | struct fpu *fpu = &target->thread.fpu; |
18ecb3bf | 483 | struct xsave_struct *xsave; |
5b3efd50 SS |
484 | int ret; |
485 | ||
486 | if (!cpu_has_xsave) | |
487 | return -ENODEV; | |
488 | ||
cc08d545 | 489 | ret = fpu__unlazy_stopped(fpu); |
5b3efd50 SS |
490 | if (ret) |
491 | return ret; | |
492 | ||
8dcea8db | 493 | xsave = &fpu->state->xsave; |
18ecb3bf | 494 | |
5b3efd50 | 495 | /* |
ff7fbc72 SS |
496 | * Copy the 48bytes defined by the software first into the xstate |
497 | * memory layout in the thread struct, so that we can copy the entire | |
498 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 499 | */ |
e7f180dc ON |
500 | memcpy(&xsave->i387.sw_reserved, |
501 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 | 502 | /* |
ff7fbc72 | 503 | * Copy the xstate memory layout. |
5b3efd50 | 504 | */ |
e7f180dc | 505 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
506 | return ret; |
507 | } | |
508 | ||
509 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
510 | unsigned int pos, unsigned int count, | |
511 | const void *kbuf, const void __user *ubuf) | |
512 | { | |
cc08d545 | 513 | struct fpu *fpu = &target->thread.fpu; |
18ecb3bf | 514 | struct xsave_struct *xsave; |
5b3efd50 | 515 | int ret; |
5b3efd50 SS |
516 | |
517 | if (!cpu_has_xsave) | |
518 | return -ENODEV; | |
519 | ||
cc08d545 | 520 | ret = fpu__unlazy_stopped(fpu); |
5b3efd50 SS |
521 | if (ret) |
522 | return ret; | |
523 | ||
8dcea8db | 524 | xsave = &fpu->state->xsave; |
18ecb3bf | 525 | |
e7f180dc | 526 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
527 | /* |
528 | * mxcsr reserved bits must be masked to zero for security reasons. | |
529 | */ | |
e7f180dc | 530 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
400e4b20 | 531 | xsave->header.xfeatures &= xfeatures_mask; |
5b3efd50 SS |
532 | /* |
533 | * These bits must be zero. | |
534 | */ | |
3a54450b | 535 | memset(&xsave->header.reserved, 0, 48); |
8dcea8db | 536 | |
5b3efd50 SS |
537 | return ret; |
538 | } | |
539 | ||
44210111 | 540 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 541 | |
1da177e4 LT |
542 | /* |
543 | * FPU tag word conversions. | |
544 | */ | |
545 | ||
3b095a04 | 546 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
547 | { |
548 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 549 | |
1da177e4 | 550 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 551 | tmp = ~twd; |
44210111 | 552 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
553 | /* and move the valid bits to the lower byte. */ |
554 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
555 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
556 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 557 | |
3b095a04 | 558 | return tmp; |
1da177e4 LT |
559 | } |
560 | ||
497888cf | 561 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
562 | #define FP_EXP_TAG_VALID 0 |
563 | #define FP_EXP_TAG_ZERO 1 | |
564 | #define FP_EXP_TAG_SPECIAL 2 | |
565 | #define FP_EXP_TAG_EMPTY 3 | |
566 | ||
567 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
568 | { | |
569 | struct _fpxreg *st; | |
570 | u32 tos = (fxsave->swd >> 11) & 7; | |
571 | u32 twd = (unsigned long) fxsave->twd; | |
572 | u32 tag; | |
573 | u32 ret = 0xffff0000u; | |
574 | int i; | |
1da177e4 | 575 | |
44210111 | 576 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
577 | if (twd & 0x1) { |
578 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 579 | |
3b095a04 | 580 | switch (st->exponent & 0x7fff) { |
1da177e4 | 581 | case 0x7fff: |
44210111 | 582 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
583 | break; |
584 | case 0x0000: | |
3b095a04 CG |
585 | if (!st->significand[0] && |
586 | !st->significand[1] && | |
587 | !st->significand[2] && | |
44210111 RM |
588 | !st->significand[3]) |
589 | tag = FP_EXP_TAG_ZERO; | |
590 | else | |
591 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
592 | break; |
593 | default: | |
44210111 RM |
594 | if (st->significand[3] & 0x8000) |
595 | tag = FP_EXP_TAG_VALID; | |
596 | else | |
597 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
598 | break; |
599 | } | |
600 | } else { | |
44210111 | 601 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 602 | } |
44210111 | 603 | ret |= tag << (2 * i); |
1da177e4 LT |
604 | } |
605 | return ret; | |
606 | } | |
607 | ||
608 | /* | |
44210111 | 609 | * FXSR floating point environment conversions. |
1da177e4 LT |
610 | */ |
611 | ||
72a671ce | 612 | void |
f668964e | 613 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 614 | { |
86603283 | 615 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
616 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
617 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
618 | int i; | |
1da177e4 | 619 | |
44210111 RM |
620 | env->cwd = fxsave->cwd | 0xffff0000u; |
621 | env->swd = fxsave->swd | 0xffff0000u; | |
622 | env->twd = twd_fxsr_to_i387(fxsave); | |
623 | ||
624 | #ifdef CONFIG_X86_64 | |
625 | env->fip = fxsave->rip; | |
626 | env->foo = fxsave->rdp; | |
10c11f30 BG |
627 | /* |
628 | * should be actually ds/cs at fpu exception time, but | |
629 | * that information is not available in 64bit mode. | |
630 | */ | |
631 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 632 | if (tsk == current) { |
10c11f30 | 633 | savesegment(ds, env->fos); |
1da177e4 | 634 | } else { |
10c11f30 | 635 | env->fos = tsk->thread.ds; |
1da177e4 | 636 | } |
10c11f30 | 637 | env->fos |= 0xffff0000; |
44210111 RM |
638 | #else |
639 | env->fip = fxsave->fip; | |
609b5297 | 640 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
641 | env->foo = fxsave->foo; |
642 | env->fos = fxsave->fos; | |
643 | #endif | |
1da177e4 | 644 | |
44210111 RM |
645 | for (i = 0; i < 8; ++i) |
646 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
647 | } |
648 | ||
72a671ce SS |
649 | void convert_to_fxsr(struct task_struct *tsk, |
650 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 651 | |
1da177e4 | 652 | { |
86603283 | 653 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
654 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
655 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
656 | int i; | |
1da177e4 | 657 | |
44210111 RM |
658 | fxsave->cwd = env->cwd; |
659 | fxsave->swd = env->swd; | |
660 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
661 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
662 | #ifdef CONFIG_X86_64 | |
663 | fxsave->rip = env->fip; | |
664 | fxsave->rdp = env->foo; | |
665 | /* cs and ds ignored */ | |
666 | #else | |
667 | fxsave->fip = env->fip; | |
668 | fxsave->fcs = (env->fcs & 0xffff); | |
669 | fxsave->foo = env->foo; | |
670 | fxsave->fos = env->fos; | |
671 | #endif | |
1da177e4 | 672 | |
44210111 RM |
673 | for (i = 0; i < 8; ++i) |
674 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
675 | } |
676 | ||
44210111 RM |
677 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
678 | unsigned int pos, unsigned int count, | |
679 | void *kbuf, void __user *ubuf) | |
1da177e4 | 680 | { |
cc08d545 | 681 | struct fpu *fpu = &target->thread.fpu; |
44210111 | 682 | struct user_i387_ia32_struct env; |
aa283f49 | 683 | int ret; |
1da177e4 | 684 | |
cc08d545 | 685 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
686 | if (ret) |
687 | return ret; | |
1da177e4 | 688 | |
60e019eb | 689 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
690 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
691 | ||
60e019eb | 692 | if (!cpu_has_fxsr) |
44210111 | 693 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 694 | &fpu->state->fsave, 0, |
61c4628b | 695 | -1); |
1da177e4 | 696 | |
29104e10 SS |
697 | sanitize_i387_state(target); |
698 | ||
44210111 RM |
699 | if (kbuf && pos == 0 && count == sizeof(env)) { |
700 | convert_from_fxsr(kbuf, target); | |
701 | return 0; | |
1da177e4 | 702 | } |
44210111 RM |
703 | |
704 | convert_from_fxsr(&env, target); | |
f668964e | 705 | |
44210111 | 706 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
707 | } |
708 | ||
44210111 RM |
709 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
710 | unsigned int pos, unsigned int count, | |
711 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 712 | { |
cc08d545 | 713 | struct fpu *fpu = &target->thread.fpu; |
44210111 RM |
714 | struct user_i387_ia32_struct env; |
715 | int ret; | |
1da177e4 | 716 | |
cc08d545 | 717 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
718 | if (ret) |
719 | return ret; | |
720 | ||
29104e10 SS |
721 | sanitize_i387_state(target); |
722 | ||
60e019eb | 723 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
724 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
725 | ||
60e019eb | 726 | if (!cpu_has_fxsr) |
44210111 | 727 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 728 | &fpu->state->fsave, 0, |
60e019eb | 729 | -1); |
44210111 RM |
730 | |
731 | if (pos > 0 || count < sizeof(env)) | |
732 | convert_from_fxsr(&env, target); | |
733 | ||
734 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
735 | if (!ret) | |
736 | convert_to_fxsr(target, &env); | |
737 | ||
42deec6f SS |
738 | /* |
739 | * update the header bit in the xsave header, indicating the | |
740 | * presence of FP. | |
741 | */ | |
742 | if (cpu_has_xsave) | |
400e4b20 | 743 | fpu->state->xsave.header.xfeatures |= XSTATE_FP; |
44210111 | 744 | return ret; |
1da177e4 LT |
745 | } |
746 | ||
1da177e4 LT |
747 | /* |
748 | * FPU state for core dumps. | |
60b3b9af RM |
749 | * This is only used for a.out dumps now. |
750 | * It is declared generically using elf_fpregset_t (which is | |
751 | * struct user_i387_struct) but is in fact only used for 32-bit | |
752 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 753 | */ |
c5bedc68 | 754 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu) |
1da177e4 | 755 | { |
1da177e4 | 756 | struct task_struct *tsk = current; |
c5bedc68 | 757 | struct fpu *fpu = &tsk->thread.fpu; |
f668964e | 758 | int fpvalid; |
1da177e4 | 759 | |
c5bedc68 | 760 | fpvalid = fpu->fpstate_active; |
60b3b9af RM |
761 | if (fpvalid) |
762 | fpvalid = !fpregs_get(tsk, NULL, | |
763 | 0, sizeof(struct user_i387_ia32_struct), | |
c5bedc68 | 764 | ufpu, NULL); |
1da177e4 LT |
765 | |
766 | return fpvalid; | |
767 | } | |
129f6946 | 768 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 769 | |
60b3b9af | 770 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |