x86/fpu: Remove 'struct task_struct' usage from __thread_set_has_fpu()
[deliverable/linux.git] / arch / x86 / kernel / fpu / core.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
1361b83a 8#include <asm/fpu-internal.h>
1da177e4 9
085cc281
IM
10/*
11 * Track whether the kernel is using the FPU state
12 * currently.
13 *
14 * This flag is used:
15 *
16 * - by IRQ context code to potentially use the FPU
17 * if it's unused.
18 *
19 * - to debug kernel_fpu_begin()/end() correctness
20 */
14e153ef
ON
21static DEFINE_PER_CPU(bool, in_kernel_fpu);
22
b0c050c5 23/*
36b544dc 24 * Track which context is using the FPU on the CPU:
b0c050c5 25 */
36b544dc 26DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
b0c050c5 27
416d49ac 28static void kernel_fpu_disable(void)
7575637a
ON
29{
30 WARN_ON(this_cpu_read(in_kernel_fpu));
31 this_cpu_write(in_kernel_fpu, true);
32}
33
416d49ac 34static void kernel_fpu_enable(void)
7575637a 35{
3103ae3a 36 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
7575637a
ON
37 this_cpu_write(in_kernel_fpu, false);
38}
39
085cc281
IM
40static bool kernel_fpu_disabled(void)
41{
42 return this_cpu_read(in_kernel_fpu);
43}
44
8546c008
LT
45/*
46 * Were we in an interrupt that interrupted kernel mode?
47 *
304bceda 48 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
8546c008
LT
49 * pair does nothing at all: the thread must not have fpu (so
50 * that we don't try to save the FPU state), and TS must
51 * be set (so that the clts/stts pair does nothing that is
52 * visible in the interrupted kernel thread).
5187b28f 53 *
4b2e762e
ON
54 * Except for the eagerfpu case when we return true; in the likely case
55 * the thread has FPU but we are not going to set/clear TS.
8546c008 56 */
416d49ac 57static bool interrupted_kernel_fpu_idle(void)
8546c008 58{
085cc281 59 if (kernel_fpu_disabled())
14e153ef
ON
60 return false;
61
5d2bd700 62 if (use_eager_fpu())
4b2e762e 63 return true;
304bceda 64
276983f8 65 return !current->thread.fpu.has_fpu && (read_cr0() & X86_CR0_TS);
8546c008
LT
66}
67
68/*
69 * Were we in user mode (or vm86 mode) when we were
70 * interrupted?
71 *
72 * Doing kernel_fpu_begin/end() is ok if we are running
73 * in an interrupt context from user mode - we'll just
74 * save the FPU state as required.
75 */
416d49ac 76static bool interrupted_user_mode(void)
8546c008
LT
77{
78 struct pt_regs *regs = get_irq_regs();
f39b6f0e 79 return regs && user_mode(regs);
8546c008
LT
80}
81
82/*
83 * Can we use the FPU in kernel mode with the
84 * whole "kernel_fpu_begin/end()" sequence?
85 *
86 * It's always ok in process context (ie "not interrupt")
87 * but it is sometimes ok even from an irq.
88 */
89bool irq_fpu_usable(void)
90{
91 return !in_interrupt() ||
92 interrupted_user_mode() ||
93 interrupted_kernel_fpu_idle();
94}
95EXPORT_SYMBOL(irq_fpu_usable);
96
b1a74bf8 97void __kernel_fpu_begin(void)
8546c008 98{
36b544dc 99 struct fpu *fpu = &current->thread.fpu;
8546c008 100
3103ae3a 101 kernel_fpu_disable();
14e153ef 102
276983f8
IM
103 if (fpu->has_fpu) {
104 fpu_save_init(fpu);
7aeccb83 105 } else {
36b544dc 106 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
7aeccb83
ON
107 if (!use_eager_fpu())
108 clts();
8546c008
LT
109 }
110}
b1a74bf8 111EXPORT_SYMBOL(__kernel_fpu_begin);
8546c008 112
b1a74bf8 113void __kernel_fpu_end(void)
8546c008 114{
33a3ebdc 115 struct task_struct *me = current;
276983f8 116 struct fpu *fpu = &me->thread.fpu;
33a3ebdc 117
276983f8 118 if (fpu->has_fpu) {
33a3ebdc 119 if (WARN_ON(restore_fpu_checking(me)))
b85e67d1 120 fpu_reset_state(me);
33a3ebdc 121 } else if (!use_eager_fpu()) {
304bceda 122 stts();
731bd6a9 123 }
14e153ef 124
3103ae3a 125 kernel_fpu_enable();
8546c008 126}
b1a74bf8 127EXPORT_SYMBOL(__kernel_fpu_end);
8546c008 128
4af08f2f
IM
129/*
130 * Save the FPU state (initialize it if necessary):
87cdb98a
IM
131 *
132 * This only ever gets called for the current task.
4af08f2f 133 */
0a781551 134void fpu__save(struct task_struct *tsk)
8546c008 135{
276983f8
IM
136 struct fpu *fpu = &tsk->thread.fpu;
137
87cdb98a
IM
138 WARN_ON(tsk != current);
139
8546c008 140 preempt_disable();
276983f8 141 if (fpu->has_fpu) {
1a2a7f4e
ON
142 if (use_eager_fpu()) {
143 __save_fpu(tsk);
144 } else {
276983f8 145 fpu_save_init(fpu);
1a2a7f4e
ON
146 __thread_fpu_end(tsk);
147 }
a9241ea5 148 }
8546c008
LT
149 preempt_enable();
150}
4af08f2f 151EXPORT_SYMBOL_GPL(fpu__save);
8546c008 152
c0ee2cf6 153void fpstate_init(struct fpu *fpu)
1da177e4 154{
60e019eb 155 if (!cpu_has_fpu) {
86603283
AK
156 finit_soft_fpu(&fpu->state->soft);
157 return;
e8a496ac 158 }
e8a496ac 159
1d23c451
ON
160 memset(fpu->state, 0, xstate_size);
161
1da177e4 162 if (cpu_has_fxsr) {
5d2bd700 163 fx_finit(&fpu->state->fxsave);
1da177e4 164 } else {
86603283 165 struct i387_fsave_struct *fp = &fpu->state->fsave;
61c4628b
SS
166 fp->cwd = 0xffff037fu;
167 fp->swd = 0xffff0000u;
168 fp->twd = 0xffffffffu;
169 fp->fos = 0xffff0000u;
1da177e4 170 }
86603283 171}
c0ee2cf6 172EXPORT_SYMBOL_GPL(fpstate_init);
86603283 173
8ffb53ab
IM
174/*
175 * FPU state allocation:
176 */
f55f88e2 177static struct kmem_cache *task_xstate_cachep;
8ffb53ab
IM
178
179void fpstate_cache_init(void)
180{
181 task_xstate_cachep =
182 kmem_cache_create("task_xstate", xstate_size,
183 __alignof__(union thread_xstate),
184 SLAB_PANIC | SLAB_NOTRACK, NULL);
185 setup_xstate_comp();
186}
187
ed97b085 188int fpstate_alloc(struct fpu *fpu)
6fbe6712
IM
189{
190 if (fpu->state)
191 return 0;
ed97b085 192
6fbe6712
IM
193 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
194 if (!fpu->state)
195 return -ENOMEM;
ed97b085
IM
196
197 /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */
6fbe6712 198 WARN_ON((unsigned long)fpu->state & 15);
ed97b085 199
6fbe6712
IM
200 return 0;
201}
ed97b085 202EXPORT_SYMBOL_GPL(fpstate_alloc);
6fbe6712 203
5a12bf63
IM
204void fpstate_free(struct fpu *fpu)
205{
206 if (fpu->state) {
207 kmem_cache_free(task_xstate_cachep, fpu->state);
208 fpu->state = NULL;
209 }
210}
211EXPORT_SYMBOL_GPL(fpstate_free);
212
bfd6fc05
IM
213/*
214 * Copy the current task's FPU state to a new task's FPU context.
215 *
216 * In the 'eager' case we just save to the destination context.
217 *
218 * In the 'lazy' case we save to the source context, mark the FPU lazy
219 * via stts() and copy the source context into the destination context.
220 */
e102f30f
IM
221static void fpu_copy(struct task_struct *dst, struct task_struct *src)
222{
bfd6fc05
IM
223 WARN_ON(src != current);
224
e102f30f
IM
225 if (use_eager_fpu()) {
226 memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
227 __save_fpu(dst);
228 } else {
229 struct fpu *dfpu = &dst->thread.fpu;
230 struct fpu *sfpu = &src->thread.fpu;
231
232 fpu__save(src);
233 memcpy(dfpu->state, sfpu->state, xstate_size);
234 }
235}
236
a752b53d
IM
237int fpu__copy(struct task_struct *dst, struct task_struct *src)
238{
239 dst->thread.fpu.counter = 0;
240 dst->thread.fpu.has_fpu = 0;
241 dst->thread.fpu.state = NULL;
242
243 task_disable_lazy_fpu_restore(dst);
244
245 if (tsk_used_math(src)) {
246 int err = fpstate_alloc(&dst->thread.fpu);
247
248 if (err)
249 return err;
250 fpu_copy(dst, src);
251 }
252 return 0;
253}
254
97185c95
IM
255/*
256 * Allocate the backing store for the current task's FPU registers
257 * and initialize the registers themselves as well.
258 *
259 * Can fail.
260 */
261int fpstate_alloc_init(struct task_struct *curr)
262{
263 int ret;
264
265 if (WARN_ON_ONCE(curr != current))
266 return -EINVAL;
267 if (WARN_ON_ONCE(curr->flags & PF_USED_MATH))
268 return -EINVAL;
269
270 /*
271 * Memory allocation at the first usage of the FPU and other state.
272 */
ed97b085 273 ret = fpstate_alloc(&curr->thread.fpu);
97185c95
IM
274 if (ret)
275 return ret;
276
c0ee2cf6 277 fpstate_init(&curr->thread.fpu);
97185c95
IM
278
279 /* Safe to do for the current task: */
280 curr->flags |= PF_USED_MATH;
281
282 return 0;
283}
284EXPORT_SYMBOL_GPL(fpstate_alloc_init);
285
86603283
AK
286/*
287 * The _current_ task is using the FPU for the first time
288 * so initialize it and set the mxcsr to its default
289 * value at reset if we support XMM instructions and then
0d2eb44f 290 * remember the current task has used the FPU.
86603283 291 */
67e97fc2 292static int fpu__unlazy_stopped(struct task_struct *child)
86603283
AK
293{
294 int ret;
295
67e97fc2
IM
296 if (WARN_ON_ONCE(child == current))
297 return -EINVAL;
298
071ae621 299 if (child->flags & PF_USED_MATH) {
67e97fc2 300 task_disable_lazy_fpu_restore(child);
86603283
AK
301 return 0;
302 }
303
44210111 304 /*
86603283 305 * Memory allocation at the first usage of the FPU and other state.
44210111 306 */
ed97b085 307 ret = fpstate_alloc(&child->thread.fpu);
86603283
AK
308 if (ret)
309 return ret;
310
c0ee2cf6 311 fpstate_init(&child->thread.fpu);
86603283 312
071ae621
IM
313 /* Safe to do for stopped child tasks: */
314 child->flags |= PF_USED_MATH;
315
aa283f49 316 return 0;
1da177e4
LT
317}
318
93b90712 319/*
3a0aee48 320 * 'fpu__restore()' saves the current math information in the
93b90712
IM
321 * old math state array, and gets the new ones from the current task
322 *
323 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
324 * Don't touch unless you *really* know how it works.
325 *
326 * Must be called with kernel preemption disabled (eg with local
327 * local interrupts as in the case of do_device_not_available).
328 */
3a0aee48 329void fpu__restore(void)
93b90712
IM
330{
331 struct task_struct *tsk = current;
332
333 if (!tsk_used_math(tsk)) {
334 local_irq_enable();
335 /*
336 * does a slab alloc which can sleep
337 */
338 if (fpstate_alloc_init(tsk)) {
339 /*
340 * ran out of memory!
341 */
342 do_group_exit(SIGKILL);
343 return;
344 }
345 local_irq_disable();
346 }
347
348 /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */
349 kernel_fpu_disable();
350 __thread_fpu_begin(tsk);
351 if (unlikely(restore_fpu_checking(tsk))) {
352 fpu_reset_state(tsk);
353 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
354 } else {
355 tsk->thread.fpu.counter++;
356 }
357 kernel_fpu_enable();
358}
3a0aee48 359EXPORT_SYMBOL_GPL(fpu__restore);
93b90712 360
81683cc8
IM
361void fpu__flush_thread(struct task_struct *tsk)
362{
363 if (!use_eager_fpu()) {
364 /* FPU state will be reallocated lazily at the first use. */
365 drop_fpu(tsk);
366 fpstate_free(&tsk->thread.fpu);
367 } else {
368 if (!tsk_used_math(tsk)) {
369 /* kthread execs. TODO: cleanup this horror. */
370 if (WARN_ON(fpstate_alloc_init(tsk)))
371 force_sig(SIGKILL, tsk);
372 user_fpu_begin();
373 }
374 restore_init_xstate();
375 }
376}
377
5b3efd50
SS
378/*
379 * The xstateregs_active() routine is the same as the fpregs_active() routine,
380 * as the "regset->n" for the xstate regset will be updated based on the feature
381 * capabilites supported by the xsave.
382 */
44210111
RM
383int fpregs_active(struct task_struct *target, const struct user_regset *regset)
384{
385 return tsk_used_math(target) ? regset->n : 0;
386}
1da177e4 387
44210111 388int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
1da177e4 389{
44210111
RM
390 return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
391}
1da177e4 392
44210111
RM
393int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
394 unsigned int pos, unsigned int count,
395 void *kbuf, void __user *ubuf)
396{
aa283f49
SS
397 int ret;
398
44210111
RM
399 if (!cpu_has_fxsr)
400 return -ENODEV;
401
67e97fc2 402 ret = fpu__unlazy_stopped(target);
aa283f49
SS
403 if (ret)
404 return ret;
44210111 405
29104e10
SS
406 sanitize_i387_state(target);
407
44210111 408 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 409 &target->thread.fpu.state->fxsave, 0, -1);
1da177e4 410}
44210111
RM
411
412int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
413 unsigned int pos, unsigned int count,
414 const void *kbuf, const void __user *ubuf)
415{
416 int ret;
417
418 if (!cpu_has_fxsr)
419 return -ENODEV;
420
67e97fc2 421 ret = fpu__unlazy_stopped(target);
aa283f49
SS
422 if (ret)
423 return ret;
424
29104e10
SS
425 sanitize_i387_state(target);
426
44210111 427 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
86603283 428 &target->thread.fpu.state->fxsave, 0, -1);
44210111
RM
429
430 /*
431 * mxcsr reserved bits must be masked to zero for security reasons.
432 */
86603283 433 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
44210111 434
42deec6f
SS
435 /*
436 * update the header bits in the xsave header, indicating the
437 * presence of FP and SSE state.
438 */
439 if (cpu_has_xsave)
86603283 440 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
42deec6f 441
44210111
RM
442 return ret;
443}
444
5b3efd50
SS
445int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
446 unsigned int pos, unsigned int count,
447 void *kbuf, void __user *ubuf)
448{
18ecb3bf 449 struct xsave_struct *xsave;
5b3efd50
SS
450 int ret;
451
452 if (!cpu_has_xsave)
453 return -ENODEV;
454
67e97fc2 455 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
456 if (ret)
457 return ret;
458
18ecb3bf
BP
459 xsave = &target->thread.fpu.state->xsave;
460
5b3efd50 461 /*
ff7fbc72
SS
462 * Copy the 48bytes defined by the software first into the xstate
463 * memory layout in the thread struct, so that we can copy the entire
464 * xstateregs to the user using one user_regset_copyout().
5b3efd50 465 */
e7f180dc
ON
466 memcpy(&xsave->i387.sw_reserved,
467 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
5b3efd50 468 /*
ff7fbc72 469 * Copy the xstate memory layout.
5b3efd50 470 */
e7f180dc 471 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
472 return ret;
473}
474
475int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
476 unsigned int pos, unsigned int count,
477 const void *kbuf, const void __user *ubuf)
478{
18ecb3bf 479 struct xsave_struct *xsave;
5b3efd50 480 int ret;
5b3efd50
SS
481
482 if (!cpu_has_xsave)
483 return -ENODEV;
484
67e97fc2 485 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
486 if (ret)
487 return ret;
488
18ecb3bf
BP
489 xsave = &target->thread.fpu.state->xsave;
490
e7f180dc 491 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
492 /*
493 * mxcsr reserved bits must be masked to zero for security reasons.
494 */
e7f180dc
ON
495 xsave->i387.mxcsr &= mxcsr_feature_mask;
496 xsave->xsave_hdr.xstate_bv &= pcntxt_mask;
5b3efd50
SS
497 /*
498 * These bits must be zero.
499 */
e7f180dc 500 memset(&xsave->xsave_hdr.reserved, 0, 48);
5b3efd50
SS
501 return ret;
502}
503
44210111 504#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
1da177e4 505
1da177e4
LT
506/*
507 * FPU tag word conversions.
508 */
509
3b095a04 510static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
1da177e4
LT
511{
512 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
3b095a04 513
1da177e4 514 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
3b095a04 515 tmp = ~twd;
44210111 516 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
3b095a04
CG
517 /* and move the valid bits to the lower byte. */
518 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
519 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
520 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
f668964e 521
3b095a04 522 return tmp;
1da177e4
LT
523}
524
497888cf 525#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
44210111
RM
526#define FP_EXP_TAG_VALID 0
527#define FP_EXP_TAG_ZERO 1
528#define FP_EXP_TAG_SPECIAL 2
529#define FP_EXP_TAG_EMPTY 3
530
531static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
532{
533 struct _fpxreg *st;
534 u32 tos = (fxsave->swd >> 11) & 7;
535 u32 twd = (unsigned long) fxsave->twd;
536 u32 tag;
537 u32 ret = 0xffff0000u;
538 int i;
1da177e4 539
44210111 540 for (i = 0; i < 8; i++, twd >>= 1) {
3b095a04
CG
541 if (twd & 0x1) {
542 st = FPREG_ADDR(fxsave, (i - tos) & 7);
1da177e4 543
3b095a04 544 switch (st->exponent & 0x7fff) {
1da177e4 545 case 0x7fff:
44210111 546 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
547 break;
548 case 0x0000:
3b095a04
CG
549 if (!st->significand[0] &&
550 !st->significand[1] &&
551 !st->significand[2] &&
44210111
RM
552 !st->significand[3])
553 tag = FP_EXP_TAG_ZERO;
554 else
555 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
556 break;
557 default:
44210111
RM
558 if (st->significand[3] & 0x8000)
559 tag = FP_EXP_TAG_VALID;
560 else
561 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
562 break;
563 }
564 } else {
44210111 565 tag = FP_EXP_TAG_EMPTY;
1da177e4 566 }
44210111 567 ret |= tag << (2 * i);
1da177e4
LT
568 }
569 return ret;
570}
571
572/*
44210111 573 * FXSR floating point environment conversions.
1da177e4
LT
574 */
575
72a671ce 576void
f668964e 577convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
1da177e4 578{
86603283 579 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
580 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
581 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
582 int i;
1da177e4 583
44210111
RM
584 env->cwd = fxsave->cwd | 0xffff0000u;
585 env->swd = fxsave->swd | 0xffff0000u;
586 env->twd = twd_fxsr_to_i387(fxsave);
587
588#ifdef CONFIG_X86_64
589 env->fip = fxsave->rip;
590 env->foo = fxsave->rdp;
10c11f30
BG
591 /*
592 * should be actually ds/cs at fpu exception time, but
593 * that information is not available in 64bit mode.
594 */
595 env->fcs = task_pt_regs(tsk)->cs;
44210111 596 if (tsk == current) {
10c11f30 597 savesegment(ds, env->fos);
1da177e4 598 } else {
10c11f30 599 env->fos = tsk->thread.ds;
1da177e4 600 }
10c11f30 601 env->fos |= 0xffff0000;
44210111
RM
602#else
603 env->fip = fxsave->fip;
609b5297 604 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
44210111
RM
605 env->foo = fxsave->foo;
606 env->fos = fxsave->fos;
607#endif
1da177e4 608
44210111
RM
609 for (i = 0; i < 8; ++i)
610 memcpy(&to[i], &from[i], sizeof(to[0]));
1da177e4
LT
611}
612
72a671ce
SS
613void convert_to_fxsr(struct task_struct *tsk,
614 const struct user_i387_ia32_struct *env)
1da177e4 615
1da177e4 616{
86603283 617 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
618 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
619 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
620 int i;
1da177e4 621
44210111
RM
622 fxsave->cwd = env->cwd;
623 fxsave->swd = env->swd;
624 fxsave->twd = twd_i387_to_fxsr(env->twd);
625 fxsave->fop = (u16) ((u32) env->fcs >> 16);
626#ifdef CONFIG_X86_64
627 fxsave->rip = env->fip;
628 fxsave->rdp = env->foo;
629 /* cs and ds ignored */
630#else
631 fxsave->fip = env->fip;
632 fxsave->fcs = (env->fcs & 0xffff);
633 fxsave->foo = env->foo;
634 fxsave->fos = env->fos;
635#endif
1da177e4 636
44210111
RM
637 for (i = 0; i < 8; ++i)
638 memcpy(&to[i], &from[i], sizeof(from[0]));
1da177e4
LT
639}
640
44210111
RM
641int fpregs_get(struct task_struct *target, const struct user_regset *regset,
642 unsigned int pos, unsigned int count,
643 void *kbuf, void __user *ubuf)
1da177e4 644{
44210111 645 struct user_i387_ia32_struct env;
aa283f49 646 int ret;
1da177e4 647
67e97fc2 648 ret = fpu__unlazy_stopped(target);
aa283f49
SS
649 if (ret)
650 return ret;
1da177e4 651
60e019eb 652 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
653 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
654
60e019eb 655 if (!cpu_has_fxsr)
44210111 656 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 657 &target->thread.fpu.state->fsave, 0,
61c4628b 658 -1);
1da177e4 659
29104e10
SS
660 sanitize_i387_state(target);
661
44210111
RM
662 if (kbuf && pos == 0 && count == sizeof(env)) {
663 convert_from_fxsr(kbuf, target);
664 return 0;
1da177e4 665 }
44210111
RM
666
667 convert_from_fxsr(&env, target);
f668964e 668
44210111 669 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
1da177e4
LT
670}
671
44210111
RM
672int fpregs_set(struct task_struct *target, const struct user_regset *regset,
673 unsigned int pos, unsigned int count,
674 const void *kbuf, const void __user *ubuf)
1da177e4 675{
44210111
RM
676 struct user_i387_ia32_struct env;
677 int ret;
1da177e4 678
67e97fc2 679 ret = fpu__unlazy_stopped(target);
aa283f49
SS
680 if (ret)
681 return ret;
682
29104e10
SS
683 sanitize_i387_state(target);
684
60e019eb 685 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
686 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
687
60e019eb 688 if (!cpu_has_fxsr)
44210111 689 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
60e019eb
PA
690 &target->thread.fpu.state->fsave, 0,
691 -1);
44210111
RM
692
693 if (pos > 0 || count < sizeof(env))
694 convert_from_fxsr(&env, target);
695
696 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
697 if (!ret)
698 convert_to_fxsr(target, &env);
699
42deec6f
SS
700 /*
701 * update the header bit in the xsave header, indicating the
702 * presence of FP.
703 */
704 if (cpu_has_xsave)
86603283 705 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
44210111 706 return ret;
1da177e4
LT
707}
708
1da177e4
LT
709/*
710 * FPU state for core dumps.
60b3b9af
RM
711 * This is only used for a.out dumps now.
712 * It is declared generically using elf_fpregset_t (which is
713 * struct user_i387_struct) but is in fact only used for 32-bit
714 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
1da177e4 715 */
3b095a04 716int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
1da177e4 717{
1da177e4 718 struct task_struct *tsk = current;
f668964e 719 int fpvalid;
1da177e4
LT
720
721 fpvalid = !!used_math();
60b3b9af
RM
722 if (fpvalid)
723 fpvalid = !fpregs_get(tsk, NULL,
724 0, sizeof(struct user_i387_ia32_struct),
725 fpu, NULL);
1da177e4
LT
726
727 return fpvalid;
728}
129f6946 729EXPORT_SYMBOL(dump_fpu);
1da177e4 730
60b3b9af 731#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
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