Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
df6b35f4 | 8 | #include <asm/fpu/api.h> |
78f7f1e5 | 9 | #include <asm/fpu/internal.h> |
fcbc99c4 | 10 | #include <asm/fpu/signal.h> |
72a671ce | 11 | #include <asm/sigframe.h> |
375074cc | 12 | #include <asm/tlbflush.h> |
dc1e35c6 | 13 | |
5b073430 IM |
14 | static const char *xfeature_names[] = |
15 | { | |
16 | "x87 floating point registers" , | |
17 | "SSE registers" , | |
18 | "AVX registers" , | |
19 | "MPX bounds registers" , | |
20 | "MPX CSR" , | |
21 | "AVX-512 opmask" , | |
22 | "AVX-512 Hi256" , | |
23 | "AVX-512 ZMM_Hi256" , | |
24 | "unknown xstate feature" , | |
25 | }; | |
26 | ||
dc1e35c6 | 27 | /* |
614df7fb | 28 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 29 | */ |
5b073430 | 30 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 31 | |
45c2d7f4 RR |
32 | /* |
33 | * Represents init state for the supported extended state. | |
34 | */ | |
3e5e1267 | 35 | struct xsave_struct init_xstate_ctx; |
45c2d7f4 | 36 | |
72a671ce | 37 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
966ece61 | 38 | static unsigned int xstate_offsets[XFEATURES_NR_MAX], xstate_sizes[XFEATURES_NR_MAX]; |
614df7fb | 39 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
40 | |
41 | /* The number of supported xfeatures in xfeatures_mask: */ | |
42 | static unsigned int xfeatures_nr; | |
a1488f8b | 43 | |
5b073430 IM |
44 | /* |
45 | * Return whether the system supports a given xfeature. | |
46 | * | |
47 | * Also return the name of the (most advanced) feature that the caller requested: | |
48 | */ | |
49 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
50 | { | |
51 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
52 | ||
53 | if (unlikely(feature_name)) { | |
54 | long xfeature_idx, max_idx; | |
55 | u64 xfeatures_print; | |
56 | /* | |
57 | * So we use FLS here to be able to print the most advanced | |
58 | * feature that was requested but is missing. So if a driver | |
59 | * asks about "XSTATE_SSE | XSTATE_YMM" we'll print the | |
60 | * missing AVX feature - this is the most informative message | |
61 | * to users: | |
62 | */ | |
63 | if (xfeatures_missing) | |
64 | xfeatures_print = xfeatures_missing; | |
65 | else | |
66 | xfeatures_print = xfeatures_needed; | |
67 | ||
68 | xfeature_idx = fls64(xfeatures_print)-1; | |
69 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
70 | xfeature_idx = min(xfeature_idx, max_idx); | |
71 | ||
72 | *feature_name = xfeature_names[xfeature_idx]; | |
73 | } | |
74 | ||
75 | if (xfeatures_missing) | |
76 | return 0; | |
77 | ||
78 | return 1; | |
79 | } | |
80 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
81 | ||
29104e10 | 82 | /* |
73a3aeb3 IM |
83 | * When executing XSAVEOPT (optimized XSAVE), if a processor implementation |
84 | * detects that an FPU state component is still (or is again) in its | |
85 | * initialized state, it may clear the corresponding bit in the header.xfeatures | |
86 | * field, and can skip the writeout of registers to the corresponding memory layout. | |
87 | * | |
88 | * This means that when the bit is zero, the state component might still contain | |
89 | * some previous - non-initialized register state. | |
90 | * | |
91 | * Before writing xstate information to user-space we sanitize those components, | |
92 | * to always ensure that the memory layout of a feature will be in the init state | |
93 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
94 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 95 | */ |
36e49e7f | 96 | void fpstate_sanitize_xstate(struct fpu *fpu) |
29104e10 | 97 | { |
36e49e7f | 98 | struct i387_fxsave_struct *fx = &fpu->state.fxsave; |
73a3aeb3 | 99 | int feature_bit; |
400e4b20 | 100 | u64 xfeatures; |
29104e10 | 101 | |
1ac91a76 | 102 | if (!use_xsaveopt()) |
29104e10 SS |
103 | return; |
104 | ||
36e49e7f | 105 | xfeatures = fpu->state.xsave.header.xfeatures; |
29104e10 SS |
106 | |
107 | /* | |
108 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 109 | * to do for us, as the memory layout is up to date. |
29104e10 | 110 | */ |
400e4b20 | 111 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
112 | return; |
113 | ||
114 | /* | |
115 | * FP is in init state | |
116 | */ | |
400e4b20 | 117 | if (!(xfeatures & XSTATE_FP)) { |
29104e10 SS |
118 | fx->cwd = 0x37f; |
119 | fx->swd = 0; | |
120 | fx->twd = 0; | |
121 | fx->fop = 0; | |
122 | fx->rip = 0; | |
123 | fx->rdp = 0; | |
124 | memset(&fx->st_space[0], 0, 128); | |
125 | } | |
126 | ||
127 | /* | |
128 | * SSE is in init state | |
129 | */ | |
400e4b20 | 130 | if (!(xfeatures & XSTATE_SSE)) |
29104e10 SS |
131 | memset(&fx->xmm_space[0], 0, 256); |
132 | ||
73a3aeb3 IM |
133 | /* |
134 | * First two features are FPU and SSE, which above we handled | |
135 | * in a special way already: | |
136 | */ | |
137 | feature_bit = 0x2; | |
400e4b20 | 138 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
139 | |
140 | /* | |
73a3aeb3 IM |
141 | * Update all the remaining memory layouts according to their |
142 | * standard xstate layout, if their header bit is in the init | |
143 | * state: | |
29104e10 | 144 | */ |
400e4b20 IM |
145 | while (xfeatures) { |
146 | if (xfeatures & 0x1) { | |
29104e10 SS |
147 | int offset = xstate_offsets[feature_bit]; |
148 | int size = xstate_sizes[feature_bit]; | |
149 | ||
73a3aeb3 | 150 | memcpy((void *)fx + offset, |
3e5e1267 | 151 | (void *)&init_xstate_ctx + offset, |
29104e10 SS |
152 | size); |
153 | } | |
154 | ||
400e4b20 | 155 | xfeatures >>= 1; |
29104e10 SS |
156 | feature_bit++; |
157 | } | |
158 | } | |
159 | ||
c37b5efe SS |
160 | /* |
161 | * Check for the presence of extended state information in the | |
162 | * user fpstate pointer in the sigcontext. | |
163 | */ | |
72a671ce SS |
164 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
165 | void __user *fpstate, | |
166 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
167 | { |
168 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
3a54450b | 169 | sizeof(struct xstate_header); |
c37b5efe | 170 | unsigned int magic2; |
c37b5efe | 171 | |
72a671ce SS |
172 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
173 | return -1; | |
c37b5efe | 174 | |
72a671ce SS |
175 | /* Check for the first magic field and other error scenarios. */ |
176 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
177 | fx_sw->xstate_size < min_xstate_size || | |
178 | fx_sw->xstate_size > xstate_size || | |
179 | fx_sw->xstate_size > fx_sw->extended_size) | |
180 | return -1; | |
c37b5efe | 181 | |
c37b5efe SS |
182 | /* |
183 | * Check for the presence of second magic word at the end of memory | |
184 | * layout. This detects the case where the user just copied the legacy | |
185 | * fpstate layout with out copying the extended state information | |
186 | * in the memory layout. | |
187 | */ | |
72a671ce SS |
188 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
189 | || magic2 != FP_XSTATE_MAGIC2) | |
190 | return -1; | |
c37b5efe SS |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
ab513701 SS |
195 | /* |
196 | * Signal frame handlers. | |
197 | */ | |
72a671ce SS |
198 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
199 | { | |
200 | if (use_fxsr()) { | |
7366ed77 | 201 | struct xsave_struct *xsave = &tsk->thread.fpu.state.xsave; |
72a671ce SS |
202 | struct user_i387_ia32_struct env; |
203 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 204 | |
72a671ce SS |
205 | convert_from_fxsr(&env, tsk); |
206 | ||
207 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
208 | __put_user(xsave->i387.swd, &fp->status) || | |
209 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
210 | return -1; | |
211 | } else { | |
212 | struct i387_fsave_struct __user *fp = buf; | |
213 | u32 swd; | |
214 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
215 | return -1; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 222 | { |
72a671ce SS |
223 | struct xsave_struct __user *x = buf; |
224 | struct _fpx_sw_bytes *sw_bytes; | |
400e4b20 | 225 | u32 xfeatures; |
72a671ce | 226 | int err; |
ab513701 | 227 | |
72a671ce SS |
228 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
229 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
230 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 231 | |
72a671ce SS |
232 | if (!use_xsave()) |
233 | return err; | |
ab513701 | 234 | |
72a671ce | 235 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 236 | |
72a671ce | 237 | /* |
400e4b20 | 238 | * Read the xfeatures which we copied (directly from the cpu or |
72a671ce SS |
239 | * from the state in task struct) to the user buffers. |
240 | */ | |
400e4b20 | 241 | err |= __get_user(xfeatures, (__u32 *)&x->header.xfeatures); |
06c38d5e | 242 | |
72a671ce SS |
243 | /* |
244 | * For legacy compatible, we always set FP/SSE bits in the bit | |
245 | * vector while saving the state to the user context. This will | |
246 | * enable us capturing any changes(during sigreturn) to | |
247 | * the FP/SSE bits by the legacy applications which don't touch | |
400e4b20 | 248 | * xfeatures in the xsave header. |
72a671ce | 249 | * |
400e4b20 | 250 | * xsave aware apps can change the xfeatures in the xsave |
72a671ce SS |
251 | * header as well as change any contents in the memory layout. |
252 | * xrestore as part of sigreturn will capture all the changes. | |
253 | */ | |
400e4b20 | 254 | xfeatures |= XSTATE_FPSSE; |
c37b5efe | 255 | |
400e4b20 | 256 | err |= __put_user(xfeatures, (__u32 *)&x->header.xfeatures); |
72a671ce SS |
257 | |
258 | return err; | |
259 | } | |
260 | ||
2a52af8b | 261 | static inline int copy_fpregs_to_sigframe(struct xsave_struct __user *buf) |
72a671ce SS |
262 | { |
263 | int err; | |
264 | ||
265 | if (use_xsave()) | |
266 | err = xsave_user(buf); | |
267 | else if (use_fxsr()) | |
268 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
269 | else | |
270 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
271 | ||
272 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
273 | err = -EFAULT; | |
274 | return err; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Save the fpu, extended register state to the user signal frame. | |
279 | * | |
280 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
281 | * state is copied. | |
282 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
283 | * | |
284 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
285 | * buf != buf_fx for 32-bit frames with fxstate. | |
286 | * | |
287 | * If the fpu, extended register state is live, save the state directly | |
288 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
289 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
290 | * | |
291 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
292 | * the aligned state at 'buf_fx'. | |
293 | * | |
294 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
295 | * indicating the absence/presence of the extended state to the user. | |
296 | */ | |
c8e14041 | 297 | int copy_fpstate_to_sigframe(void __user *buf, void __user *buf_fx, int size) |
72a671ce | 298 | { |
7366ed77 | 299 | struct xsave_struct *xsave = ¤t->thread.fpu.state.xsave; |
72a671ce SS |
300 | struct task_struct *tsk = current; |
301 | int ia32_fxstate = (buf != buf_fx); | |
302 | ||
303 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
304 | config_enabled(CONFIG_IA32_EMULATION)); | |
305 | ||
306 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
307 | return -EACCES; | |
308 | ||
60e019eb | 309 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
310 | return fpregs_soft_get(current, NULL, 0, |
311 | sizeof(struct user_i387_ia32_struct), NULL, | |
312 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
313 | ||
3c6dffa9 | 314 | if (fpregs_active()) { |
72a671ce | 315 | /* Save the live register state to the user directly. */ |
2a52af8b | 316 | if (copy_fpregs_to_sigframe(buf_fx)) |
72a671ce SS |
317 | return -1; |
318 | /* Update the thread's fxstate to save the fsave header. */ | |
319 | if (ia32_fxstate) | |
320 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 321 | } else { |
36e49e7f | 322 | fpstate_sanitize_xstate(&tsk->thread.fpu); |
72a671ce | 323 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
324 | return -1; |
325 | } | |
c37b5efe | 326 | |
72a671ce SS |
327 | /* Save the fsave header for the 32-bit frames. */ |
328 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
329 | return -1; | |
06c38d5e | 330 | |
72a671ce SS |
331 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
332 | return -1; | |
333 | ||
72a671ce SS |
334 | return 0; |
335 | } | |
c37b5efe | 336 | |
72a671ce SS |
337 | static inline void |
338 | sanitize_restored_xstate(struct task_struct *tsk, | |
339 | struct user_i387_ia32_struct *ia32_env, | |
400e4b20 | 340 | u64 xfeatures, int fx_only) |
72a671ce | 341 | { |
7366ed77 | 342 | struct xsave_struct *xsave = &tsk->thread.fpu.state.xsave; |
3a54450b | 343 | struct xstate_header *header = &xsave->header; |
c37b5efe | 344 | |
72a671ce SS |
345 | if (use_xsave()) { |
346 | /* These bits must be zero. */ | |
3a54450b | 347 | memset(header->reserved, 0, 48); |
04944b79 SS |
348 | |
349 | /* | |
72a671ce SS |
350 | * Init the state that is not present in the memory |
351 | * layout and not enabled by the OS. | |
04944b79 | 352 | */ |
72a671ce | 353 | if (fx_only) |
400e4b20 | 354 | header->xfeatures = XSTATE_FPSSE; |
72a671ce | 355 | else |
400e4b20 | 356 | header->xfeatures &= (xfeatures_mask & xfeatures); |
72a671ce | 357 | } |
04944b79 | 358 | |
72a671ce | 359 | if (use_fxsr()) { |
04944b79 | 360 | /* |
72a671ce SS |
361 | * mscsr reserved bits must be masked to zero for security |
362 | * reasons. | |
04944b79 | 363 | */ |
72a671ce | 364 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 365 | |
72a671ce | 366 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 367 | } |
ab513701 SS |
368 | } |
369 | ||
c37b5efe | 370 | /* |
72a671ce | 371 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 372 | */ |
72a671ce | 373 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 374 | { |
72a671ce SS |
375 | if (use_xsave()) { |
376 | if ((unsigned long)buf % 64 || fx_only) { | |
614df7fb | 377 | u64 init_bv = xfeatures_mask & ~XSTATE_FPSSE; |
3e5e1267 | 378 | xrstor_state(&init_xstate_ctx, init_bv); |
e139e955 | 379 | return fxrstor_user(buf); |
72a671ce | 380 | } else { |
614df7fb | 381 | u64 init_bv = xfeatures_mask & ~xbv; |
72a671ce | 382 | if (unlikely(init_bv)) |
3e5e1267 | 383 | xrstor_state(&init_xstate_ctx, init_bv); |
72a671ce SS |
384 | return xrestore_user(buf, xbv); |
385 | } | |
386 | } else if (use_fxsr()) { | |
e139e955 | 387 | return fxrstor_user(buf); |
72a671ce | 388 | } else |
e139e955 | 389 | return frstor_user(buf); |
c37b5efe SS |
390 | } |
391 | ||
82c0e45e | 392 | static int __fpu__restore_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 393 | { |
72a671ce | 394 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 395 | struct task_struct *tsk = current; |
c5bedc68 | 396 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 397 | int state_size = xstate_size; |
400e4b20 | 398 | u64 xfeatures = 0; |
72a671ce SS |
399 | int fx_only = 0; |
400 | ||
401 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
402 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
403 | |
404 | if (!buf) { | |
fbce7782 | 405 | fpu__clear(fpu); |
ab513701 | 406 | return 0; |
72a671ce SS |
407 | } |
408 | ||
409 | if (!access_ok(VERIFY_READ, buf, size)) | |
410 | return -EACCES; | |
411 | ||
c4d72e2d | 412 | fpu__activate_curr(fpu); |
ab513701 | 413 | |
60e019eb | 414 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
415 | return fpregs_soft_set(current, NULL, |
416 | 0, sizeof(struct user_i387_ia32_struct), | |
417 | NULL, buf) != 0; | |
ab513701 | 418 | |
72a671ce SS |
419 | if (use_xsave()) { |
420 | struct _fpx_sw_bytes fx_sw_user; | |
421 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
422 | /* | |
423 | * Couldn't find the extended state information in the | |
424 | * memory layout. Restore just the FP/SSE and init all | |
425 | * the other extended state. | |
426 | */ | |
427 | state_size = sizeof(struct i387_fxsave_struct); | |
428 | fx_only = 1; | |
429 | } else { | |
430 | state_size = fx_sw_user.xstate_size; | |
400e4b20 | 431 | xfeatures = fx_sw_user.xfeatures; |
72a671ce SS |
432 | } |
433 | } | |
434 | ||
435 | if (ia32_fxstate) { | |
436 | /* | |
437 | * For 32-bit frames with fxstate, copy the user state to the | |
438 | * thread's fpu state, reconstruct fxstate from the fsave | |
439 | * header. Sanitize the copied state etc. | |
440 | */ | |
a7c80ebc | 441 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 442 | struct user_i387_ia32_struct env; |
304bceda | 443 | int err = 0; |
72a671ce | 444 | |
304bceda | 445 | /* |
c5bedc68 | 446 | * Drop the current fpu which clears fpu->fpstate_active. This ensures |
304bceda SS |
447 | * that any context-switch during the copy of the new state, |
448 | * avoids the intermediate state from getting restored/saved. | |
449 | * Thus avoiding the new restored state from getting corrupted. | |
450 | * We will be ready to restore/save the state only after | |
c5bedc68 | 451 | * fpu->fpstate_active is again set. |
304bceda | 452 | */ |
50338615 | 453 | fpu__drop(fpu); |
72a671ce | 454 | |
7366ed77 | 455 | if (__copy_from_user(&fpu->state.xsave, buf_fx, state_size) || |
304bceda | 456 | __copy_from_user(&env, buf, sizeof(env))) { |
c0ee2cf6 | 457 | fpstate_init(fpu); |
304bceda SS |
458 | err = -1; |
459 | } else { | |
400e4b20 | 460 | sanitize_restored_xstate(tsk, &env, xfeatures, fx_only); |
304bceda | 461 | } |
72a671ce | 462 | |
c5bedc68 | 463 | fpu->fpstate_active = 1; |
df24fb85 ON |
464 | if (use_eager_fpu()) { |
465 | preempt_disable(); | |
3a0aee48 | 466 | fpu__restore(); |
df24fb85 ON |
467 | preempt_enable(); |
468 | } | |
304bceda SS |
469 | |
470 | return err; | |
72a671ce | 471 | } else { |
ab513701 | 472 | /* |
72a671ce SS |
473 | * For 64-bit frames and 32-bit fsave frames, restore the user |
474 | * state to the registers directly (with exceptions handled). | |
ab513701 | 475 | */ |
72a671ce | 476 | user_fpu_begin(); |
400e4b20 | 477 | if (restore_user_xstate(buf_fx, xfeatures, fx_only)) { |
fbce7782 | 478 | fpu__clear(fpu); |
72a671ce SS |
479 | return -1; |
480 | } | |
ab513701 | 481 | } |
72a671ce SS |
482 | |
483 | return 0; | |
ab513701 | 484 | } |
ab513701 | 485 | |
82c0e45e IM |
486 | static inline int xstate_sigframe_size(void) |
487 | { | |
488 | return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size; | |
489 | } | |
490 | ||
491 | /* | |
492 | * Restore FPU state from a sigframe: | |
493 | */ | |
494 | int fpu__restore_sig(void __user *buf, int ia32_frame) | |
495 | { | |
496 | void __user *buf_fx = buf; | |
497 | int size = xstate_sigframe_size(); | |
498 | ||
499 | if (ia32_frame && use_fxsr()) { | |
500 | buf_fx = buf + sizeof(struct i387_fsave_struct); | |
501 | size += sizeof(struct i387_fsave_struct); | |
502 | } | |
503 | ||
504 | return __fpu__restore_sig(buf, buf_fx, size); | |
505 | } | |
506 | ||
507 | unsigned long | |
508 | fpu__alloc_mathframe(unsigned long sp, int ia32_frame, | |
509 | unsigned long *buf_fx, unsigned long *size) | |
510 | { | |
511 | unsigned long frame_size = xstate_sigframe_size(); | |
512 | ||
513 | *buf_fx = sp = round_down(sp - frame_size, 64); | |
514 | if (ia32_frame && use_fxsr()) { | |
515 | frame_size += sizeof(struct i387_fsave_struct); | |
516 | sp -= sizeof(struct i387_fsave_struct); | |
517 | } | |
518 | ||
519 | *size = frame_size; | |
520 | ||
521 | return sp; | |
522 | } | |
c37b5efe SS |
523 | /* |
524 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
525 | * the presence of the extended state information in the memory layout | |
526 | * pointed by the fpstate pointer in the sigcontext. | |
527 | * This will be saved when ever the FP and extended state context is | |
528 | * saved on the user stack during the signal handler delivery to the user. | |
529 | */ | |
8bcad30f | 530 | static void prepare_fx_sw_frame(void) |
c37b5efe | 531 | { |
72a671ce SS |
532 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
533 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 534 | |
72a671ce SS |
535 | if (config_enabled(CONFIG_X86_32)) |
536 | size += fsave_header_size; | |
c37b5efe SS |
537 | |
538 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 539 | fx_sw_reserved.extended_size = size; |
400e4b20 | 540 | fx_sw_reserved.xfeatures = xfeatures_mask; |
c37b5efe | 541 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 542 | |
72a671ce SS |
543 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
544 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
545 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
546 | } | |
547 | } | |
3c1c7f10 | 548 | |
dc1e35c6 | 549 | /* |
55cc4678 IM |
550 | * Enable the extended processor state save/restore feature. |
551 | * Called once per CPU onlining. | |
dc1e35c6 | 552 | */ |
55cc4678 | 553 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 554 | { |
e84611fc | 555 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
556 | return; |
557 | ||
375074cc | 558 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 559 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
560 | } |
561 | ||
a1488f8b SS |
562 | /* |
563 | * Record the offsets and sizes of different state managed by the xsave | |
564 | * memory layout. | |
565 | */ | |
4995b9db | 566 | static void __init setup_xstate_features(void) |
a1488f8b SS |
567 | { |
568 | int eax, ebx, ecx, edx, leaf = 0x2; | |
569 | ||
84246fe4 | 570 | xfeatures_nr = fls64(xfeatures_mask); |
a1488f8b SS |
571 | |
572 | do { | |
ee813d53 | 573 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
574 | |
575 | if (eax == 0) | |
576 | break; | |
577 | ||
578 | xstate_offsets[leaf] = ebx; | |
579 | xstate_sizes[leaf] = eax; | |
580 | ||
581 | leaf++; | |
582 | } while (1); | |
583 | } | |
584 | ||
33588b52 | 585 | static void print_xstate_feature(u64 xstate_mask) |
69496e10 | 586 | { |
33588b52 | 587 | const char *feature_name; |
69496e10 | 588 | |
33588b52 IM |
589 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
590 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
591 | } |
592 | ||
593 | /* | |
594 | * Print out all the supported xstate features: | |
595 | */ | |
596 | static void print_xstate_features(void) | |
597 | { | |
33588b52 IM |
598 | print_xstate_feature(XSTATE_FP); |
599 | print_xstate_feature(XSTATE_SSE); | |
600 | print_xstate_feature(XSTATE_YMM); | |
601 | print_xstate_feature(XSTATE_BNDREGS); | |
602 | print_xstate_feature(XSTATE_BNDCSR); | |
603 | print_xstate_feature(XSTATE_OPMASK); | |
604 | print_xstate_feature(XSTATE_ZMM_Hi256); | |
605 | print_xstate_feature(XSTATE_Hi16_ZMM); | |
69496e10 IM |
606 | } |
607 | ||
7496d645 FY |
608 | /* |
609 | * This function sets up offsets and sizes of all extended states in | |
610 | * xsave area. This supports both standard format and compacted format | |
611 | * of the xsave aread. | |
612 | * | |
613 | * Input: void | |
614 | * Output: void | |
615 | */ | |
616 | void setup_xstate_comp(void) | |
617 | { | |
614df7fb | 618 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
619 | int i; |
620 | ||
8ff925e1 FY |
621 | /* |
622 | * The FP xstates and SSE xstates are legacy states. They are always | |
623 | * in the fixed offsets in the xsave area in either compacted form | |
624 | * or standard form. | |
625 | */ | |
626 | xstate_comp_offsets[0] = 0; | |
627 | xstate_comp_offsets[1] = offsetof(struct i387_fxsave_struct, xmm_space); | |
7496d645 FY |
628 | |
629 | if (!cpu_has_xsaves) { | |
84246fe4 | 630 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 631 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
632 | xstate_comp_offsets[i] = xstate_offsets[i]; |
633 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
634 | } | |
635 | } | |
636 | return; | |
637 | } | |
638 | ||
639 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
640 | ||
84246fe4 | 641 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 642 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
643 | xstate_comp_sizes[i] = xstate_sizes[i]; |
644 | else | |
645 | xstate_comp_sizes[i] = 0; | |
646 | ||
647 | if (i > 2) | |
648 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
649 | + xstate_comp_sizes[i-1]; | |
650 | ||
651 | } | |
652 | } | |
653 | ||
dc1e35c6 SS |
654 | /* |
655 | * setup the xstate image representing the init state | |
656 | */ | |
26b1f5d0 | 657 | static void setup_init_fpu_buf(void) |
dc1e35c6 | 658 | { |
26b1f5d0 IM |
659 | static int on_boot_cpu = 1; |
660 | ||
661 | if (!on_boot_cpu) | |
662 | return; | |
663 | on_boot_cpu = 0; | |
664 | ||
5d2bd700 SS |
665 | if (!cpu_has_xsave) |
666 | return; | |
667 | ||
668 | setup_xstate_features(); | |
69496e10 | 669 | print_xstate_features(); |
a1488f8b | 670 | |
47c2f292 | 671 | if (cpu_has_xsaves) { |
3e5e1267 IM |
672 | init_xstate_ctx.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
673 | init_xstate_ctx.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
674 | } |
675 | ||
29104e10 SS |
676 | /* |
677 | * Init all the features state with header_bv being 0x0 | |
678 | */ | |
3e5e1267 | 679 | xrstor_state_booting(&init_xstate_ctx, -1); |
3e261c14 | 680 | |
29104e10 SS |
681 | /* |
682 | * Dump the init state again. This is to identify the init state | |
683 | * of any feature which is not represented by all zero's. | |
684 | */ | |
3e5e1267 | 685 | xsave_state_booting(&init_xstate_ctx); |
dc1e35c6 SS |
686 | } |
687 | ||
7e7ce87f | 688 | /* |
614df7fb | 689 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f FY |
690 | */ |
691 | static void __init init_xstate_size(void) | |
692 | { | |
693 | unsigned int eax, ebx, ecx, edx; | |
694 | int i; | |
695 | ||
696 | if (!cpu_has_xsaves) { | |
697 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
698 | xstate_size = ebx; | |
699 | return; | |
700 | } | |
701 | ||
702 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
703 | for (i = 2; i < 64; i++) { | |
614df7fb | 704 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f FY |
705 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
706 | xstate_size += eax; | |
707 | } | |
708 | } | |
709 | } | |
710 | ||
dc1e35c6 SS |
711 | /* |
712 | * Enable and initialize the xsave feature. | |
55cc4678 | 713 | * Called once per system bootup. |
c0841e34 | 714 | * |
c42103b2 | 715 | * ( Not marked __init because of false positive section warnings. ) |
dc1e35c6 | 716 | */ |
55cc4678 | 717 | void fpu__init_system_xstate(void) |
dc1e35c6 SS |
718 | { |
719 | unsigned int eax, ebx, ecx, edx; | |
62db6871 IM |
720 | static bool on_boot_cpu = 1; |
721 | ||
722 | if (!on_boot_cpu) | |
723 | return; | |
724 | on_boot_cpu = 0; | |
dc1e35c6 | 725 | |
e9dbfd67 IM |
726 | if (!cpu_has_xsave) { |
727 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
728 | return; | |
729 | } | |
730 | ||
ee813d53 | 731 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
32d4d9cc | 732 | WARN(1, "x86/fpu: XSTATE_CPUID missing!\n"); |
ee813d53 RR |
733 | return; |
734 | } | |
735 | ||
736 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 737 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 738 | |
614df7fb IM |
739 | if ((xfeatures_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
740 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); | |
dc1e35c6 SS |
741 | BUG(); |
742 | } | |
743 | ||
744 | /* | |
a30469e7 | 745 | * Support only the state known to OS. |
dc1e35c6 | 746 | */ |
614df7fb | 747 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 748 | |
55cc4678 IM |
749 | /* Enable xstate instructions to be able to continue with initialization: */ |
750 | fpu__init_cpu_xstate(); | |
dc1e35c6 SS |
751 | |
752 | /* | |
753 | * Recompute the context size for enabled features | |
754 | */ | |
7e7ce87f | 755 | init_xstate_size(); |
dc1e35c6 | 756 | |
614df7fb | 757 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
c37b5efe | 758 | prepare_fx_sw_frame(); |
5d2bd700 | 759 | setup_init_fpu_buf(); |
dc1e35c6 | 760 | |
32d4d9cc | 761 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is 0x%x bytes, using '%s' format.\n", |
614df7fb | 762 | xfeatures_mask, |
32d4d9cc IM |
763 | xstate_size, |
764 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 765 | } |
82d4150c | 766 | |
9254aaa0 IM |
767 | /* |
768 | * Restore minimal FPU state after suspend: | |
769 | */ | |
770 | void fpu__resume_cpu(void) | |
771 | { | |
772 | /* | |
773 | * Restore XCR0 on xsave capable CPUs: | |
774 | */ | |
775 | if (cpu_has_xsave) | |
776 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
777 | } | |
778 | ||
7496d645 FY |
779 | /* |
780 | * Given the xsave area and a state inside, this function returns the | |
781 | * address of the state. | |
782 | * | |
783 | * This is the API that is called to get xstate address in either | |
784 | * standard format or compacted format of xsave area. | |
785 | * | |
786 | * Inputs: | |
787 | * xsave: base address of the xsave area; | |
788 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
789 | * etc.) | |
790 | * Output: | |
791 | * address of the state in the xsave area. | |
792 | */ | |
793 | void *get_xsave_addr(struct xsave_struct *xsave, int xstate) | |
794 | { | |
795 | int feature = fls64(xstate) - 1; | |
614df7fb | 796 | if (!test_bit(feature, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
797 | return NULL; |
798 | ||
799 | return (void *)xsave + xstate_comp_offsets[feature]; | |
800 | } | |
ba7b3920 | 801 | EXPORT_SYMBOL_GPL(get_xsave_addr); |