[deliverable/linux.git] / arch / x86 / kernel / head_64.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/desc.h>
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>

#ifdef CONFIG_PARAVIRT
#include <asm/asm-offsets.h>
#include <asm/paravirt.h>
#else
#define GET_CR2_INTO_RCX movq %cr2, %rcx
#endif

/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
 * because we need identity-mapped pages.
 *
 */

	.text
	.section .text.head
	.code64
	.globl startup_64
startup_64:

	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded an identity mapped page table
	 * for us.  These identity mapped page tables map all of the
	 * kernel pages and possibly all of memory.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either directly from a 64bit bootloader, or from
	 * arch/x86_64/boot/compressed/head.S.
	 *
	 * We only come here initially at boot nothing else comes here.
	 *
	 * Since we may be loaded at an address different from what we were
	 * compiled to run at we first fixup the physical addresses in our page
	 * tables and then reload them.
	 */

	/* Compute the delta between the address I am compiled to run at and the
	 * address I am actually running at.
	 */
	leaq	_text(%rip), %rbp
	subq	$_text - __START_KERNEL_map, %rbp

	/* Is the address not 2M aligned? */
	movq	%rbp, %rax
	andl	$~LARGE_PAGE_MASK, %eax
	testl	%eax, %eax
	jnz	bad_address

	/* Is the address too large? */
	leaq	_text(%rip), %rdx
	movq	$PGDIR_SIZE, %rax
	cmpq	%rax, %rdx
	jae	bad_address

	/* Fixup the physical addresses in the page table
	 */
	addq	%rbp, init_level4_pgt + 0(%rip)
	addq	%rbp, init_level4_pgt + (258*8)(%rip)
	addq	%rbp, init_level4_pgt + (511*8)(%rip)

	addq	%rbp, level3_ident_pgt + 0(%rip)

	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)

	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)

	/* Add an Identity mapping if I am above 1G */
	leaq	_text(%rip), %rdi
	andq	$LARGE_PAGE_MASK, %rdi

	movq	%rdi, %rax
	shrq	$PUD_SHIFT, %rax
	andq	$(PTRS_PER_PUD - 1), %rax
	jz	ident_complete

	leaq	(level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	leaq	level3_ident_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)

	movq	%rdi, %rax
	shrq	$PMD_SHIFT, %rax
	andq	$(PTRS_PER_PMD - 1), %rax
	leaq	__PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
	leaq	level2_spare_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)
ident_complete:

	/* Fixup the kernel text+data virtual addresses
	 */
	leaq	level2_kernel_pgt(%rip), %rdi
	leaq	4096(%rdi), %r8
	/* See if it is a valid page table entry */
1:	testq	$1, 0(%rdi)
	jz	2f
	addq	%rbp, 0(%rdi)
	/* Go to the next page */
2:	addq	$8, %rdi
	cmp	%r8, %rdi
	jne	1b

	/* Fixup phys_base */
	addq	%rbp, phys_base(%rip)

#ifdef CONFIG_SMP
	addq	%rbp, trampoline_level4_pgt + 0(%rip)
	addq	%rbp, trampoline_level4_pgt + (511*8)(%rip)
#endif
#ifdef CONFIG_ACPI_SLEEP
	addq	%rbp, wakeup_level4_pgt + 0(%rip)
	addq	%rbp, wakeup_level4_pgt + (511*8)(%rip)
#endif

	/* Due to ENTRY(), sometimes the empty space gets filled with
	 * zeros. Better take a jmp than relying on empty space being
	 * filled with 0x90 (nop)
	 */
	jmp secondary_startup_64
ENTRY(secondary_startup_64)
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded a mapped page table.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either from startup_64 (using physical addresses)
	 * or from trampoline.S (using virtual addresses).
	 *
	 * Using virtual addresses from trampoline.S removes the need
	 * to have any identity mapped pages in the kernel page table
	 * after the boot processor executes this code.
	 */

	/* Enable PAE mode and PGE */
	xorq	%rax, %rax
	btsq	$5, %rax
	btsq	$7, %rax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
	addq	phys_base(%rip), %rax
	movq	%rax, %cr3

	/* Ensure I am executing from virtual addresses */
	movq	$1f, %rax
	jmp	*%rax
1:

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btsl	$_EFER_SCE, %eax	/* Enable System Call */
	btl	$20,%edi		/* No Execute supported? */
	jnc     1f
	btsl	$_EFER_NX, %eax
1:	wrmsr				/* Make changes effective */

	/* Setup cr0 */
#define CR0_PM				1		/* protected mode */
#define CR0_MP				(1<<1)
#define CR0_ET				(1<<4)
#define CR0_NE				(1<<5)
#define CR0_WP				(1<<16)
#define CR0_AM				(1<<18)
#define CR0_PAGING 			(1<<31)
	movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq init_rsp(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	cpu_gdt_descr(%rip)

	/* set up data segments. actually 0 would do too */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds
	movl %eax,%ss
	movl %eax,%es

	/*
	 * We don't really need to load %fs or %gs, but load them anyway
	 * to kill any stale realmode selectors.  This allows execution
	 * under VT hardware.
	 */
	movl %eax,%fs
	movl %eax,%gs

	/* 
	 * Setup up a dummy PDA. this is just for some early bootup code
	 * that does in_interrupt() 
	 */ 
	movl	$MSR_GS_BASE,%ecx
	movq	$empty_zero_page,%rax
	movq    %rax,%rdx
	shrq	$32,%rdx
	wrmsr	

	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address, this is only possible as indirect
	 * jump.  In addition we need to ensure %cs is set so we make this
	 * a far return.
	 */
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq

	/* SMP bootup changes these two */
#ifndef CONFIG_HOTPLUG_CPU
	.pushsection .init.data
#endif
	.align	8
	.globl	initial_code
initial_code:
	.quad	x86_64_start_kernel
#ifndef CONFIG_HOTPLUG_CPU
	.popsection
#endif
	.globl init_rsp
init_rsp:
	.quad  init_thread_union+THREAD_SIZE-8

bad_address:
	jmp bad_address

ENTRY(early_idt_handler)
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)
	xorl %eax,%eax
	movq 8(%rsp),%rsi	# get rip
	movq (%rsp),%rdx
	GET_CR2_INTO_RCX
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
#ifdef CONFIG_KALLSYMS	
	leaq early_idt_ripmsg(%rip),%rdi
	movq 8(%rsp),%rsi	# get rip again
	call __print_symbol
#endif
1:	hlt
	jmp 1b
early_recursion_flag:
	.long 0

early_idt_msg:
	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
early_idt_ripmsg:
	.asciz "RIP %s\n"

.balign PAGE_SIZE

#define NEXT_PAGE(name) \
	.balign	PAGE_SIZE; \
ENTRY(name)

/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT)		\
	i = 0 ;					\
	.rept (COUNT) ;				\
	.quad	(START) + (i << 21) + (PERM) ;	\
	i = i + 1 ;				\
	.endr

	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
NEXT_PAGE(init_level4_pgt)
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	257,8,0
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	252,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level3_ident_pgt)
	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	511,8,0

NEXT_PAGE(level3_kernel_pgt)
	.fill	510,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level2_fixmap_pgt)
	.fill	506,8,0
	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	.fill	5,8,0

NEXT_PAGE(level1_fixmap_pgt)
	.fill	512,8,0

NEXT_PAGE(level2_ident_pgt)
	/* Since I easily can, map the first 1G.
	 * Don't set NX because code runs from these pages.
	 */
	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)

NEXT_PAGE(level2_kernel_pgt)
	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	   When you change this change KERNEL_TEXT_SIZE in page.h too. */
	/* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE)
	/* Module mapping starts here */
	.fill	(PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0

NEXT_PAGE(level2_spare_pgt)
	.fill   512,8,0

#undef PMDS
#undef NEXT_PAGE

	.data
	.align 16
	.globl cpu_gdt_descr
cpu_gdt_descr:
	.word	gdt_end-cpu_gdt_table-1
gdt:
	.quad	cpu_gdt_table
#ifdef CONFIG_SMP
	.rept	NR_CPUS-1
	.word	0
	.quad	0
	.endr
#endif

ENTRY(phys_base)
	/* This must match the first entry in level2_kernel_pgt */
	.quad   0x0000000000000000

/* We need valid kernel segments for data and code in long mode too
 * IRET will check the segment types  kkeil 2000/10/28
 * Also sysret mandates a special GDT layout 
 */
		 		
	.section .data.page_aligned, "aw"
	.align PAGE_SIZE

/* The TLS descriptors are currently at a different place compared to i386.
   Hopefully nobody expects them at a fixed place (Wine?) */
	
ENTRY(cpu_gdt_table)
	.quad	0x0000000000000000	/* NULL descriptor */
	.quad	0x00cf9b000000ffff	/* __KERNEL32_CS */
	.quad	0x00af9b000000ffff	/* __KERNEL_CS */
	.quad	0x00cf93000000ffff	/* __KERNEL_DS */
	.quad	0x00cffb000000ffff	/* __USER32_CS */
	.quad	0x00cff3000000ffff	/* __USER_DS, __USER32_DS  */
	.quad	0x00affb000000ffff	/* __USER_CS */
	.quad	0x0			/* unused */
	.quad	0,0			/* TSS */
	.quad	0,0			/* LDT */
	.quad   0,0,0			/* three TLS descriptors */ 
	.quad	0x0000f40000000000	/* node/CPU stored in limit */
gdt_end:	
	/* asm/segment.h:GDT_ENTRIES must match this */	
	/* This should be a multiple of the cache line size */
	/* GDTs of other CPUs are now dynamically allocated */

	/* zero the remaining page */
	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0

	.section .bss, "aw", @nobits
	.align L1_CACHE_BYTES
ENTRY(idt_table)
	.skip 256 * 16

	.section .bss.page_aligned, "aw", @nobits
	.align PAGE_SIZE
ENTRY(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
1ab60e0f	8	* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
1da177e4 LT	9	*/
	10
	11
	12	#include <linux/linkage.h>
	13	#include <linux/threads.h>
f6c2e333	14	#include <linux/init.h>
1da177e4 LT	15	#include <asm/desc.h>
1da177e4 LT	16	#include <asm/segment.h>
67dcbb6b	17	#include <asm/pgtable.h>
1da177e4 LT	18	#include <asm/page.h>
	19	#include <asm/msr.h>
	20	#include <asm/cache.h>
1ab60e0f	21
49a69787 GOC	22	#ifdef CONFIG_PARAVIRT
	23	#include <asm/asm-offsets.h>
	24	#include <asm/paravirt.h>
	25	#else
	26	#define GET_CR2_INTO_RCX movq %cr2, %rcx
	27	#endif
	28
1da177e4	29	/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
1ab60e0f VG	30	* because we need identity-mapped pages.
1ab60e0f VG	31	*
1da177e4 LT	32	*/
	33
	34	.text
92417df0	35	.section .text.head
1ab60e0f VG	36	.code64
	37	.globl startup_64
	38	startup_64:
	39
1da177e4	40	/*
1ab60e0f VG	41	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	42	* and someone has loaded an identity mapped page table
	43	* for us. These identity mapped page tables map all of the
	44	* kernel pages and possibly all of memory.
	45	*
	46	* %esi holds a physical pointer to real_mode_data.
	47	*
	48	* We come here either directly from a 64bit bootloader, or from
	49	* arch/x86_64/boot/compressed/head.S.
	50	*
	51	* We only come here initially at boot nothing else comes here.
	52	*
	53	* Since we may be loaded at an address different from what we were
	54	* compiled to run at we first fixup the physical addresses in our page
	55	* tables and then reload them.
1da177e4 LT	56	*/
1da177e4 LT	57
1ab60e0f VG	58	/* Compute the delta between the address I am compiled to run at and the
1ab60e0f VG	59	* address I am actually running at.
1da177e4	60	*/
1ab60e0f VG	61	leaq _text(%rip), %rbp
	62	subq $_text - __START_KERNEL_map, %rbp
	63
	64	/* Is the address not 2M aligned? */
	65	movq %rbp, %rax
	66	andl $~LARGE_PAGE_MASK, %eax
	67	testl %eax, %eax
	68	jnz bad_address
	69
	70	/* Is the address too large? */
	71	leaq _text(%rip), %rdx
	72	movq $PGDIR_SIZE, %rax
	73	cmpq %rax, %rdx
	74	jae bad_address
	75
	76	/* Fixup the physical addresses in the page table
1da177e4	77	*/
1ab60e0f VG	78	addq %rbp, init_level4_pgt + 0(%rip)
	79	addq %rbp, init_level4_pgt + (258*8)(%rip)
	80	addq %rbp, init_level4_pgt + (511*8)(%rip)
	81
	82	addq %rbp, level3_ident_pgt + 0(%rip)
b1c931e3	83
1ab60e0f	84	addq %rbp, level3_kernel_pgt + (510*8)(%rip)
b1c931e3 EB	85	addq %rbp, level3_kernel_pgt + (511*8)(%rip)
	86
	87	addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
1ab60e0f VG	88
	89	/* Add an Identity mapping if I am above 1G */
	90	leaq _text(%rip), %rdi
	91	andq $LARGE_PAGE_MASK, %rdi
	92
	93	movq %rdi, %rax
	94	shrq $PUD_SHIFT, %rax
	95	andq $(PTRS_PER_PUD - 1), %rax
	96	jz ident_complete
	97
	98	leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	99	leaq level3_ident_pgt(%rip), %rbx
	100	movq %rdx, 0(%rbx, %rax, 8)
	101
	102	movq %rdi, %rax
	103	shrq $PMD_SHIFT, %rax
	104	andq $(PTRS_PER_PMD - 1), %rax
	105	leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
	106	leaq level2_spare_pgt(%rip), %rbx
	107	movq %rdx, 0(%rbx, %rax, 8)
	108	ident_complete:
	109
	110	/* Fixup the kernel text+data virtual addresses
	111	*/
	112	leaq level2_kernel_pgt(%rip), %rdi
	113	leaq 4096(%rdi), %r8
	114	/* See if it is a valid page table entry */
	115	1: testq $1, 0(%rdi)
	116	jz 2f
	117	addq %rbp, 0(%rdi)
	118	/* Go to the next page */
	119	2: addq $8, %rdi
	120	cmp %r8, %rdi
	121	jne 1b
	122
	123	/* Fixup phys_base */
	124	addq %rbp, phys_base(%rip)
1da177e4	125
1ab60e0f VG	126	#ifdef CONFIG_SMP
	127	addq %rbp, trampoline_level4_pgt + 0(%rip)
	128	addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
	129	#endif
673d5b43	130	#ifdef CONFIG_ACPI_SLEEP
1ab60e0f VG	131	addq %rbp, wakeup_level4_pgt + 0(%rip)
	132	addq %rbp, wakeup_level4_pgt + (511*8)(%rip)
	133	#endif
1da177e4	134
1ab60e0f VG	135	/* Due to ENTRY(), sometimes the empty space gets filled with
	136	* zeros. Better take a jmp than relying on empty space being
	137	* filled with 0x90 (nop)
1da177e4	138	*/
1ab60e0f	139	jmp secondary_startup_64
90b1c208	140	ENTRY(secondary_startup_64)
1ab60e0f VG	141	/*
	142	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	143	* and someone has loaded a mapped page table.
	144	*
	145	* %esi holds a physical pointer to real_mode_data.
	146	*
	147	* We come here either from startup_64 (using physical addresses)
	148	* or from trampoline.S (using virtual addresses).
	149	*
	150	* Using virtual addresses from trampoline.S removes the need
	151	* to have any identity mapped pages in the kernel page table
	152	* after the boot processor executes this code.
1da177e4 LT	153	*/
	154
	155	/* Enable PAE mode and PGE */
	156	xorq %rax, %rax
	157	btsq $5, %rax
	158	btsq $7, %rax
	159	movq %rax, %cr4
	160
	161	/* Setup early boot stage 4 level pagetables. */
cfd243d4	162	movq $(init_level4_pgt - __START_KERNEL_map), %rax
1ab60e0f	163	addq phys_base(%rip), %rax
1da177e4 LT	164	movq %rax, %cr3
1da177e4 LT	165
1ab60e0f VG	166	/* Ensure I am executing from virtual addresses */
	167	movq $1f, %rax
	168	jmp *%rax
	169	1:
	170
1da177e4 LT	171	/* Check if nx is implemented */
	172	movl $0x80000001, %eax
	173	cpuid
	174	movl %edx,%edi
	175
	176	/* Setup EFER (Extended Feature Enable Register) */
	177	movl $MSR_EFER, %ecx
	178	rdmsr
1ab60e0f VG	179	btsl $_EFER_SCE, %eax /* Enable System Call */
1ab60e0f VG	180	btl $20,%edi /* No Execute supported? */
1da177e4 LT	181	jnc 1f
1da177e4 LT	182	btsl $_EFER_NX, %eax
1ab60e0f	183	1: wrmsr /* Make changes effective */
1da177e4 LT	184
1da177e4 LT	185	/* Setup cr0 */
3829ee6b AK	186	#define CR0_PM 1 /* protected mode */
	187	#define CR0_MP (1<<1)
	188	#define CR0_ET (1<<4)
	189	#define CR0_NE (1<<5)
	190	#define CR0_WP (1<<16)
	191	#define CR0_AM (1<<18)
	192	#define CR0_PAGING (1<<31)
	193	movl $CR0_PM\|CR0_MP\|CR0_ET\|CR0_NE\|CR0_WP\|CR0_AM\|CR0_PAGING,%eax
1da177e4 LT	194	/* Make changes effective */
	195	movq %rax, %cr0
	196
	197	/* Setup a boot time stack */
	198	movq init_rsp(%rip),%rsp
	199
	200	/* zero EFLAGS after setting rsp */
	201	pushq $0
	202	popfq
	203
	204	/*
	205	* We must switch to a new descriptor in kernel space for the GDT
	206	* because soon the kernel won't have access anymore to the userspace
	207	* addresses where we're currently running on. We have to do that here
	208	* because in 32bit we couldn't load a 64bit linear address.
	209	*/
1ab60e0f	210	lgdt cpu_gdt_descr(%rip)
1da177e4	211
ffb60175 ZA	212	/* set up data segments. actually 0 would do too */
	213	movl $__KERNEL_DS,%eax
	214	movl %eax,%ds
	215	movl %eax,%ss
	216	movl %eax,%es
	217
	218	/*
	219	* We don't really need to load %fs or %gs, but load them anyway
	220	* to kill any stale realmode selectors. This allows execution
	221	* under VT hardware.
	222	*/
	223	movl %eax,%fs
	224	movl %eax,%gs
	225
1da177e4 LT	226	/*
	227	* Setup up a dummy PDA. this is just for some early bootup code
	228	* that does in_interrupt()
	229	*/
	230	movl $MSR_GS_BASE,%ecx
	231	movq $empty_zero_page,%rax
	232	movq %rax,%rdx
	233	shrq $32,%rdx
	234	wrmsr
	235
1da177e4 LT	236	/* esi is pointer to real mode structure with interesting info.
	237	pass it to C */
	238	movl %esi, %edi
	239
	240	/* Finally jump to run C code and to be on real kernel address
	241	* Since we are running on identity-mapped space we have to jump
26374c7b EB	242	* to the full 64bit address, this is only possible as indirect
	243	* jump. In addition we need to ensure %cs is set so we make this
	244	* a far return.
1da177e4 LT	245	*/
1da177e4 LT	246	movq initial_code(%rip),%rax
26374c7b EB	247	pushq $0 # fake return address to stop unwinder
	248	pushq $__KERNEL_CS # set correct cs
	249	pushq %rax # target address in negative space
	250	lretq
1da177e4	251
e57113bc	252	/* SMP bootup changes these two */
92417df0 AK	253	#ifndef CONFIG_HOTPLUG_CPU
	254	.pushsection .init.data
	255	#endif
e57113bc	256	.align 8
1da177e4 LT	257	.globl initial_code
	258	initial_code:
	259	.quad x86_64_start_kernel
92417df0 AK	260	#ifndef CONFIG_HOTPLUG_CPU
	261	.popsection
	262	#endif
1da177e4 LT	263	.globl init_rsp
	264	init_rsp:
	265	.quad init_thread_union+THREAD_SIZE-8
	266
1ab60e0f VG	267	bad_address:
	268	jmp bad_address
	269
1da177e4	270	ENTRY(early_idt_handler)
b957591f AK	271	cmpl $2,early_recursion_flag(%rip)
	272	jz 1f
	273	incl early_recursion_flag(%rip)
1da177e4 LT	274	xorl %eax,%eax
	275	movq 8(%rsp),%rsi # get rip
	276	movq (%rsp),%rdx
49a69787	277	GET_CR2_INTO_RCX
1da177e4 LT	278	leaq early_idt_msg(%rip),%rdi
1da177e4 LT	279	call early_printk
b957591f AK	280	cmpl $2,early_recursion_flag(%rip)
	281	jz 1f
	282	call dump_stack
6574ffd7 AK	283	#ifdef CONFIG_KALLSYMS
	284	leaq early_idt_ripmsg(%rip),%rdi
	285	movq 8(%rsp),%rsi # get rip again
	286	call __print_symbol
	287	#endif
1da177e4 LT	288	1: hlt
1da177e4 LT	289	jmp 1b
b957591f AK	290	early_recursion_flag:
b957591f AK	291	.long 0
1da177e4 LT	292
	293	early_idt_msg:
	294	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
6574ffd7 AK	295	early_idt_ripmsg:
6574ffd7 AK	296	.asciz "RIP %s\n"
1da177e4	297
1ab60e0f	298	.balign PAGE_SIZE
1da177e4	299
f0cf5d1a	300	#define NEXT_PAGE(name) \
67dcbb6b	301	.balign PAGE_SIZE; \
f0cf5d1a JB	302	ENTRY(name)
f0cf5d1a JB	303
67dcbb6b VG	304	/* Automate the creation of 1 to 1 mapping pmd entries */
	305	#define PMDS(START, PERM, COUNT) \
	306	i = 0 ; \
	307	.rept (COUNT) ; \
	308	.quad (START) + (i << 21) + (PERM) ; \
	309	i = i + 1 ; \
	310	.endr
	311
cfd243d4 VG	312	/*
	313	* This default setting generates an ident mapping at address 0x100000
	314	* and a mapping for the kernel that precisely maps virtual address
	315	* 0xffffffff80000000 to physical address 0x000000. (always using
	316	* 2Mbyte large pages provided by PAE mode)
	317	*/
f0cf5d1a	318	NEXT_PAGE(init_level4_pgt)
cfd243d4 VG	319	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	320	.fill 257,8,0
	321	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	322	.fill 252,8,0
	323	/* (2^48-(2102410241024))/(2^39) = 511 /
	324	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
1da177e4	325
f0cf5d1a	326	NEXT_PAGE(level3_ident_pgt)
67dcbb6b	327	.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
1da177e4 LT	328	.fill 511,8,0
1da177e4 LT	329
f0cf5d1a	330	NEXT_PAGE(level3_kernel_pgt)
1da177e4 LT	331	.fill 510,8,0
1da177e4 LT	332	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
67dcbb6b	333	.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
b1c931e3 EB	334	.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	335
	336	NEXT_PAGE(level2_fixmap_pgt)
	337	.fill 506,8,0
	338	.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	339	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	340	.fill 5,8,0
	341
	342	NEXT_PAGE(level1_fixmap_pgt)
	343	.fill 512,8,0
1da177e4	344
f0cf5d1a	345	NEXT_PAGE(level2_ident_pgt)
67dcbb6b VG	346	/* Since I easily can, map the first 1G.
	347	* Don't set NX because code runs from these pages.
	348	*/
	349	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
1ab60e0f	350
f0cf5d1a	351	NEXT_PAGE(level2_kernel_pgt)
1da177e4 LT	352	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	353	When you change this change KERNEL_TEXT_SIZE in page.h too. */
	354	/* (2^48-(2102410241024)-((2^39)511)-((2^30)510)) = 0 /
6e351535	355	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC\|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE)
1da177e4	356	/* Module mapping starts here */
67dcbb6b	357	.fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0
1da177e4	358
1ab60e0f VG	359	NEXT_PAGE(level2_spare_pgt)
	360	.fill 512,8,0
	361
67dcbb6b	362	#undef PMDS
f0cf5d1a	363	#undef NEXT_PAGE
1da177e4	364
f0cf5d1a	365	.data
1da177e4 LT	366	.align 16
	367	.globl cpu_gdt_descr
	368	cpu_gdt_descr:
e57113bc	369	.word gdt_end-cpu_gdt_table-1
1da177e4 LT	370	gdt:
	371	.quad cpu_gdt_table
	372	#ifdef CONFIG_SMP
	373	.rept NR_CPUS-1
	374	.word 0
	375	.quad 0
	376	.endr
	377	#endif
	378
1ab60e0f VG	379	ENTRY(phys_base)
	380	/* This must match the first entry in level2_kernel_pgt */
	381	.quad 0x0000000000000000
	382
1da177e4 LT	383	/* We need valid kernel segments for data and code in long mode too
	384	* IRET will check the segment types kkeil 2000/10/28
	385	* Also sysret mandates a special GDT layout
	386	*/
	387
e57113bc JB	388	.section .data.page_aligned, "aw"
e57113bc JB	389	.align PAGE_SIZE
1da177e4 LT	390
	391	/* The TLS descriptors are currently at a different place compared to i386.
	392	Hopefully nobody expects them at a fixed place (Wine?) */
	393
	394	ENTRY(cpu_gdt_table)
	395	.quad 0x0000000000000000 /* NULL descriptor */
30f47289 VG	396	.quad 0x00cf9b000000ffff /* __KERNEL32_CS */
	397	.quad 0x00af9b000000ffff /* __KERNEL_CS */
	398	.quad 0x00cf93000000ffff /* __KERNEL_DS */
	399	.quad 0x00cffb000000ffff /* __USER32_CS */
	400	.quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
	401	.quad 0x00affb000000ffff /* __USER_CS */
cdc4b9c0	402	.quad 0x0 /* unused */
1da177e4 LT	403	.quad 0,0 /* TSS */
	404	.quad 0,0 /* LDT */
	405	.quad 0,0,0 /* three TLS descriptors */
c08c8205	406	.quad 0x0000f40000000000 /* node/CPU stored in limit */
1da177e4 LT	407	gdt_end:
	408	/* asm/segment.h:GDT_ENTRIES must match this */
	409	/* This should be a multiple of the cache line size */
c11efdf9 RT	410	/* GDTs of other CPUs are now dynamically allocated */
	411
	412	/* zero the remaining page */
	413	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
1da177e4	414
e57113bc JB	415	.section .bss, "aw", @nobits
	416	.align L1_CACHE_BYTES
	417	ENTRY(idt_table)
	418	.skip 256 * 16
1da177e4	419
e57113bc JB	420	.section .bss.page_aligned, "aw", @nobits
	421	.align PAGE_SIZE
	422	ENTRY(empty_zero_page)
	423	.skip PAGE_SIZE