Commit | Line | Data |
---|---|---|
5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
5d0cf410 | 3 | #include <linux/errno.h> |
4 | #include <linux/hpet.h> | |
5 | #include <linux/init.h> | |
399afa4f ML |
6 | #include <linux/sysdev.h> |
7 | #include <linux/pm.h> | |
0655d7c3 | 8 | #include <linux/delay.h> |
5d0cf410 | 9 | |
10 | #include <asm/hpet.h> | |
06a24dec | 11 | #include <asm/i8253.h> |
5d0cf410 | 12 | #include <asm/io.h> |
13 | ||
7f9f303a | 14 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 15 | #define HPET_SHIFT 22 |
16 | ||
17 | /* FSEC = 10^-15 NSEC = 10^-9 */ | |
18 | #define FSEC_PER_NSEC 1000000 | |
19 | ||
e9e2cdb4 TG |
20 | /* |
21 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
22 | */ | |
23 | unsigned long hpet_address; | |
06a24dec | 24 | static void __iomem *hpet_virt_address; |
e9e2cdb4 TG |
25 | |
26 | static inline unsigned long hpet_readl(unsigned long a) | |
27 | { | |
28 | return readl(hpet_virt_address + a); | |
29 | } | |
30 | ||
31 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
32 | { | |
33 | writel(d, hpet_virt_address + a); | |
34 | } | |
35 | ||
06a24dec TG |
36 | static inline void hpet_set_mapping(void) |
37 | { | |
38 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
39 | } | |
40 | ||
41 | static inline void hpet_clear_mapping(void) | |
42 | { | |
43 | iounmap(hpet_virt_address); | |
44 | hpet_virt_address = NULL; | |
45 | } | |
46 | ||
e9e2cdb4 TG |
47 | /* |
48 | * HPET command line enable / disable | |
49 | */ | |
50 | static int boot_hpet_disable; | |
51 | ||
52 | static int __init hpet_setup(char* str) | |
53 | { | |
54 | if (str) { | |
55 | if (!strncmp("disable", str, 7)) | |
56 | boot_hpet_disable = 1; | |
57 | } | |
58 | return 1; | |
59 | } | |
60 | __setup("hpet=", hpet_setup); | |
61 | ||
62 | static inline int is_hpet_capable(void) | |
63 | { | |
64 | return (!boot_hpet_disable && hpet_address); | |
65 | } | |
66 | ||
67 | /* | |
68 | * HPET timer interrupt enable / disable | |
69 | */ | |
70 | static int hpet_legacy_int_enabled; | |
71 | ||
72 | /** | |
73 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
74 | */ | |
75 | int is_hpet_enabled(void) | |
76 | { | |
77 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
78 | } | |
79 | ||
80 | /* | |
81 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
82 | * timer 0 and timer 1 in case of RTC emulation. | |
83 | */ | |
84 | #ifdef CONFIG_HPET | |
85 | static void hpet_reserve_platform_timers(unsigned long id) | |
86 | { | |
87 | struct hpet __iomem *hpet = hpet_virt_address; | |
88 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; | |
89 | unsigned int nrtimers, i; | |
90 | struct hpet_data hd; | |
91 | ||
92 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
93 | ||
94 | memset(&hd, 0, sizeof (hd)); | |
95 | hd.hd_phys_address = hpet_address; | |
06a24dec | 96 | hd.hd_address = hpet; |
e9e2cdb4 TG |
97 | hd.hd_nirqs = nrtimers; |
98 | hd.hd_flags = HPET_DATA_PLATFORM; | |
99 | hpet_reserve_timer(&hd, 0); | |
100 | ||
101 | #ifdef CONFIG_HPET_EMULATE_RTC | |
102 | hpet_reserve_timer(&hd, 1); | |
103 | #endif | |
104 | ||
105 | hd.hd_irq[0] = HPET_LEGACY_8254; | |
106 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
107 | ||
108 | for (i = 2; i < nrtimers; timer++, i++) | |
109 | hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> | |
110 | Tn_INT_ROUTE_CNF_SHIFT; | |
111 | ||
112 | hpet_alloc(&hd); | |
113 | ||
114 | } | |
115 | #else | |
116 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
117 | #endif | |
118 | ||
119 | /* | |
120 | * Common hpet info | |
121 | */ | |
122 | static unsigned long hpet_period; | |
123 | ||
124 | static void hpet_set_mode(enum clock_event_mode mode, | |
125 | struct clock_event_device *evt); | |
126 | static int hpet_next_event(unsigned long delta, | |
127 | struct clock_event_device *evt); | |
128 | ||
129 | /* | |
130 | * The hpet clock event device | |
131 | */ | |
132 | static struct clock_event_device hpet_clockevent = { | |
133 | .name = "hpet", | |
134 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
135 | .set_mode = hpet_set_mode, | |
136 | .set_next_event = hpet_next_event, | |
137 | .shift = 32, | |
138 | .irq = 0, | |
139 | }; | |
140 | ||
141 | static void hpet_start_counter(void) | |
142 | { | |
143 | unsigned long cfg = hpet_readl(HPET_CFG); | |
144 | ||
145 | cfg &= ~HPET_CFG_ENABLE; | |
146 | hpet_writel(cfg, HPET_CFG); | |
147 | hpet_writel(0, HPET_COUNTER); | |
148 | hpet_writel(0, HPET_COUNTER + 4); | |
149 | cfg |= HPET_CFG_ENABLE; | |
150 | hpet_writel(cfg, HPET_CFG); | |
151 | } | |
152 | ||
153 | static void hpet_enable_int(void) | |
154 | { | |
155 | unsigned long cfg = hpet_readl(HPET_CFG); | |
156 | ||
157 | cfg |= HPET_CFG_LEGACY; | |
158 | hpet_writel(cfg, HPET_CFG); | |
159 | hpet_legacy_int_enabled = 1; | |
160 | } | |
161 | ||
162 | static void hpet_set_mode(enum clock_event_mode mode, | |
163 | struct clock_event_device *evt) | |
164 | { | |
165 | unsigned long cfg, cmp, now; | |
166 | uint64_t delta; | |
167 | ||
168 | switch(mode) { | |
169 | case CLOCK_EVT_MODE_PERIODIC: | |
170 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; | |
171 | delta >>= hpet_clockevent.shift; | |
172 | now = hpet_readl(HPET_COUNTER); | |
173 | cmp = now + (unsigned long) delta; | |
174 | cfg = hpet_readl(HPET_T0_CFG); | |
175 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | |
176 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
177 | hpet_writel(cfg, HPET_T0_CFG); | |
178 | /* | |
179 | * The first write after writing TN_SETVAL to the | |
180 | * config register sets the counter value, the second | |
181 | * write sets the period. | |
182 | */ | |
183 | hpet_writel(cmp, HPET_T0_CMP); | |
184 | udelay(1); | |
185 | hpet_writel((unsigned long) delta, HPET_T0_CMP); | |
186 | break; | |
187 | ||
188 | case CLOCK_EVT_MODE_ONESHOT: | |
189 | cfg = hpet_readl(HPET_T0_CFG); | |
190 | cfg &= ~HPET_TN_PERIODIC; | |
191 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
192 | hpet_writel(cfg, HPET_T0_CFG); | |
193 | break; | |
194 | ||
195 | case CLOCK_EVT_MODE_UNUSED: | |
196 | case CLOCK_EVT_MODE_SHUTDOWN: | |
197 | cfg = hpet_readl(HPET_T0_CFG); | |
198 | cfg &= ~HPET_TN_ENABLE; | |
199 | hpet_writel(cfg, HPET_T0_CFG); | |
200 | break; | |
18de5bc4 TG |
201 | |
202 | case CLOCK_EVT_MODE_RESUME: | |
203 | hpet_enable_int(); | |
204 | break; | |
e9e2cdb4 TG |
205 | } |
206 | } | |
207 | ||
208 | static int hpet_next_event(unsigned long delta, | |
209 | struct clock_event_device *evt) | |
210 | { | |
211 | unsigned long cnt; | |
212 | ||
213 | cnt = hpet_readl(HPET_COUNTER); | |
214 | cnt += delta; | |
215 | hpet_writel(cnt, HPET_T0_CMP); | |
216 | ||
c7f6d15f | 217 | return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; |
e9e2cdb4 TG |
218 | } |
219 | ||
6bb74df4 | 220 | /* |
221 | * Clock source related code | |
222 | */ | |
223 | static cycle_t read_hpet(void) | |
224 | { | |
225 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
226 | } | |
227 | ||
228 | static struct clocksource clocksource_hpet = { | |
229 | .name = "hpet", | |
230 | .rating = 250, | |
231 | .read = read_hpet, | |
232 | .mask = HPET_MASK, | |
233 | .shift = HPET_SHIFT, | |
234 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
18de5bc4 | 235 | .resume = hpet_start_counter, |
6bb74df4 | 236 | }; |
237 | ||
e9e2cdb4 TG |
238 | /* |
239 | * Try to setup the HPET timer | |
240 | */ | |
241 | int __init hpet_enable(void) | |
242 | { | |
243 | unsigned long id; | |
244 | uint64_t hpet_freq; | |
075bcd1f TG |
245 | u64 tmp, start, now; |
246 | cycle_t t1; | |
e9e2cdb4 TG |
247 | |
248 | if (!is_hpet_capable()) | |
249 | return 0; | |
250 | ||
06a24dec | 251 | hpet_set_mapping(); |
e9e2cdb4 TG |
252 | |
253 | /* | |
254 | * Read the period and check for a sane value: | |
255 | */ | |
256 | hpet_period = hpet_readl(HPET_PERIOD); | |
257 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) | |
258 | goto out_nohpet; | |
259 | ||
260 | /* | |
261 | * The period is a femto seconds value. We need to calculate the | |
262 | * scaled math multiplication factor for nanosecond to hpet tick | |
263 | * conversion. | |
264 | */ | |
265 | hpet_freq = 1000000000000000ULL; | |
266 | do_div(hpet_freq, hpet_period); | |
267 | hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, | |
268 | NSEC_PER_SEC, 32); | |
269 | /* Calculate the min / max delta */ | |
270 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
271 | &hpet_clockevent); | |
272 | hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, | |
273 | &hpet_clockevent); | |
274 | ||
275 | /* | |
276 | * Read the HPET ID register to retrieve the IRQ routing | |
277 | * information and the number of channels | |
278 | */ | |
279 | id = hpet_readl(HPET_ID); | |
280 | ||
281 | #ifdef CONFIG_HPET_EMULATE_RTC | |
282 | /* | |
283 | * The legacy routing mode needs at least two channels, tick timer | |
284 | * and the rtc emulation channel. | |
285 | */ | |
286 | if (!(id & HPET_ID_NUMBER)) | |
287 | goto out_nohpet; | |
288 | #endif | |
289 | ||
290 | /* Start the counter */ | |
291 | hpet_start_counter(); | |
292 | ||
075bcd1f TG |
293 | /* Verify whether hpet counter works */ |
294 | t1 = read_hpet(); | |
295 | rdtscll(start); | |
296 | ||
297 | /* | |
298 | * We don't know the TSC frequency yet, but waiting for | |
299 | * 200000 TSC cycles is safe: | |
300 | * 4 GHz == 50us | |
301 | * 1 GHz == 200us | |
302 | */ | |
303 | do { | |
304 | rep_nop(); | |
305 | rdtscll(now); | |
306 | } while ((now - start) < 200000UL); | |
307 | ||
308 | if (t1 == read_hpet()) { | |
309 | printk(KERN_WARNING | |
310 | "HPET counter not counting. HPET disabled\n"); | |
311 | goto out_nohpet; | |
312 | } | |
313 | ||
6bb74df4 | 314 | /* Initialize and register HPET clocksource |
315 | * | |
316 | * hpet period is in femto seconds per cycle | |
317 | * so we need to convert this to ns/cyc units | |
318 | * aproximated by mult/2^shift | |
319 | * | |
320 | * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift | |
321 | * fsec/cyc * 1ns/1000000fsec * 2^shift = mult | |
322 | * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult | |
323 | * (fsec/cyc << shift)/1000000 = mult | |
324 | * (hpet_period << shift)/FSEC_PER_NSEC = mult | |
325 | */ | |
326 | tmp = (u64)hpet_period << HPET_SHIFT; | |
327 | do_div(tmp, FSEC_PER_NSEC); | |
328 | clocksource_hpet.mult = (u32)tmp; | |
329 | ||
330 | clocksource_register(&clocksource_hpet); | |
331 | ||
e9e2cdb4 TG |
332 | if (id & HPET_ID_LEGSUP) { |
333 | hpet_enable_int(); | |
334 | hpet_reserve_platform_timers(id); | |
335 | /* | |
336 | * Start hpet with the boot cpu mask and make it | |
337 | * global after the IO_APIC has been initialized. | |
338 | */ | |
43d6ca01 | 339 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); |
e9e2cdb4 TG |
340 | clockevents_register_device(&hpet_clockevent); |
341 | global_clock_event = &hpet_clockevent; | |
342 | return 1; | |
343 | } | |
344 | return 0; | |
5d0cf410 | 345 | |
e9e2cdb4 | 346 | out_nohpet: |
06a24dec | 347 | hpet_clear_mapping(); |
399afa4f | 348 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
349 | return 0; |
350 | } | |
351 | ||
e9e2cdb4 TG |
352 | #ifdef CONFIG_HPET_EMULATE_RTC |
353 | ||
354 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
355 | * is enabled, we support RTC interrupt functionality in software. | |
356 | * RTC has 3 kinds of interrupts: | |
357 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
358 | * is updated | |
359 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
360 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
361 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
362 | * (1) and (2) above are implemented using polling at a frequency of | |
363 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
364 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
365 | * For (3), we use interrupts at 64Hz or user specified periodic | |
366 | * frequency, whichever is higher. | |
367 | */ | |
368 | #include <linux/mc146818rtc.h> | |
369 | #include <linux/rtc.h> | |
370 | ||
371 | #define DEFAULT_RTC_INT_FREQ 64 | |
372 | #define DEFAULT_RTC_SHIFT 6 | |
373 | #define RTC_NUM_INTS 1 | |
374 | ||
375 | static unsigned long hpet_rtc_flags; | |
376 | static unsigned long hpet_prev_update_sec; | |
377 | static struct rtc_time hpet_alarm_time; | |
378 | static unsigned long hpet_pie_count; | |
379 | static unsigned long hpet_t1_cmp; | |
380 | static unsigned long hpet_default_delta; | |
381 | static unsigned long hpet_pie_delta; | |
382 | static unsigned long hpet_pie_limit; | |
383 | ||
384 | /* | |
385 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
386 | * is not supported by all HPET implementations for timer 1. | |
387 | * | |
388 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
389 | */ | |
390 | int hpet_rtc_timer_init(void) | |
391 | { | |
392 | unsigned long cfg, cnt, delta, flags; | |
393 | ||
394 | if (!is_hpet_enabled()) | |
395 | return 0; | |
396 | ||
397 | if (!hpet_default_delta) { | |
398 | uint64_t clc; | |
399 | ||
400 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
401 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
402 | hpet_default_delta = (unsigned long) clc; | |
403 | } | |
404 | ||
405 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
406 | delta = hpet_default_delta; | |
407 | else | |
408 | delta = hpet_pie_delta; | |
409 | ||
410 | local_irq_save(flags); | |
411 | ||
412 | cnt = delta + hpet_readl(HPET_COUNTER); | |
413 | hpet_writel(cnt, HPET_T1_CMP); | |
414 | hpet_t1_cmp = cnt; | |
415 | ||
416 | cfg = hpet_readl(HPET_T1_CFG); | |
417 | cfg &= ~HPET_TN_PERIODIC; | |
418 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
419 | hpet_writel(cfg, HPET_T1_CFG); | |
420 | ||
421 | local_irq_restore(flags); | |
422 | ||
423 | return 1; | |
424 | } | |
425 | ||
426 | /* | |
427 | * The functions below are called from rtc driver. | |
428 | * Return 0 if HPET is not being used. | |
429 | * Otherwise do the necessary changes and return 1. | |
430 | */ | |
431 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
432 | { | |
433 | if (!is_hpet_enabled()) | |
434 | return 0; | |
435 | ||
436 | hpet_rtc_flags &= ~bit_mask; | |
437 | return 1; | |
438 | } | |
439 | ||
440 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
441 | { | |
442 | unsigned long oldbits = hpet_rtc_flags; | |
443 | ||
444 | if (!is_hpet_enabled()) | |
445 | return 0; | |
446 | ||
447 | hpet_rtc_flags |= bit_mask; | |
448 | ||
449 | if (!oldbits) | |
450 | hpet_rtc_timer_init(); | |
451 | ||
452 | return 1; | |
453 | } | |
454 | ||
455 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
456 | unsigned char sec) | |
457 | { | |
458 | if (!is_hpet_enabled()) | |
459 | return 0; | |
460 | ||
461 | hpet_alarm_time.tm_hour = hrs; | |
462 | hpet_alarm_time.tm_min = min; | |
463 | hpet_alarm_time.tm_sec = sec; | |
464 | ||
465 | return 1; | |
466 | } | |
467 | ||
468 | int hpet_set_periodic_freq(unsigned long freq) | |
469 | { | |
470 | uint64_t clc; | |
471 | ||
472 | if (!is_hpet_enabled()) | |
473 | return 0; | |
474 | ||
475 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
476 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
477 | else { | |
478 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
479 | do_div(clc, freq); | |
480 | clc >>= hpet_clockevent.shift; | |
481 | hpet_pie_delta = (unsigned long) clc; | |
482 | } | |
483 | return 1; | |
484 | } | |
485 | ||
486 | int hpet_rtc_dropped_irq(void) | |
487 | { | |
488 | return is_hpet_enabled(); | |
489 | } | |
490 | ||
491 | static void hpet_rtc_timer_reinit(void) | |
492 | { | |
493 | unsigned long cfg, delta; | |
494 | int lost_ints = -1; | |
495 | ||
496 | if (unlikely(!hpet_rtc_flags)) { | |
497 | cfg = hpet_readl(HPET_T1_CFG); | |
498 | cfg &= ~HPET_TN_ENABLE; | |
499 | hpet_writel(cfg, HPET_T1_CFG); | |
500 | return; | |
501 | } | |
502 | ||
503 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
504 | delta = hpet_default_delta; | |
505 | else | |
506 | delta = hpet_pie_delta; | |
507 | ||
508 | /* | |
509 | * Increment the comparator value until we are ahead of the | |
510 | * current count. | |
511 | */ | |
512 | do { | |
513 | hpet_t1_cmp += delta; | |
514 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
515 | lost_ints++; | |
516 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
517 | ||
518 | if (lost_ints) { | |
519 | if (hpet_rtc_flags & RTC_PIE) | |
520 | hpet_pie_count += lost_ints; | |
521 | if (printk_ratelimit()) | |
522 | printk(KERN_WARNING "rtc: lost %d interrupts\n", | |
523 | lost_ints); | |
524 | } | |
525 | } | |
526 | ||
527 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
528 | { | |
529 | struct rtc_time curr_time; | |
530 | unsigned long rtc_int_flag = 0; | |
531 | ||
532 | hpet_rtc_timer_reinit(); | |
533 | ||
534 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
535 | rtc_get_rtc_time(&curr_time); | |
536 | ||
537 | if (hpet_rtc_flags & RTC_UIE && | |
538 | curr_time.tm_sec != hpet_prev_update_sec) { | |
539 | rtc_int_flag = RTC_UF; | |
540 | hpet_prev_update_sec = curr_time.tm_sec; | |
541 | } | |
542 | ||
543 | if (hpet_rtc_flags & RTC_PIE && | |
544 | ++hpet_pie_count >= hpet_pie_limit) { | |
545 | rtc_int_flag |= RTC_PF; | |
546 | hpet_pie_count = 0; | |
547 | } | |
548 | ||
549 | if (hpet_rtc_flags & RTC_PIE && | |
550 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && | |
551 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
552 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
553 | rtc_int_flag |= RTC_AF; | |
554 | ||
555 | if (rtc_int_flag) { | |
556 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
557 | rtc_interrupt(rtc_int_flag, dev_id); | |
558 | } | |
559 | return IRQ_HANDLED; | |
560 | } | |
561 | #endif |