Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
375074cc | 16 | #include <asm/tlbflush.h> |
1da177e4 | 17 | #include <asm/uaccess.h> |
f668964e IM |
18 | #include <asm/ptrace.h> |
19 | #include <asm/i387.h> | |
1361b83a | 20 | #include <asm/fpu-internal.h> |
f668964e | 21 | #include <asm/user.h> |
1da177e4 | 22 | |
14e153ef ON |
23 | static DEFINE_PER_CPU(bool, in_kernel_fpu); |
24 | ||
7575637a ON |
25 | void kernel_fpu_disable(void) |
26 | { | |
27 | WARN_ON(this_cpu_read(in_kernel_fpu)); | |
28 | this_cpu_write(in_kernel_fpu, true); | |
29 | } | |
30 | ||
31 | void kernel_fpu_enable(void) | |
32 | { | |
33 | this_cpu_write(in_kernel_fpu, false); | |
34 | } | |
35 | ||
8546c008 LT |
36 | /* |
37 | * Were we in an interrupt that interrupted kernel mode? | |
38 | * | |
304bceda | 39 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
40 | * pair does nothing at all: the thread must not have fpu (so |
41 | * that we don't try to save the FPU state), and TS must | |
42 | * be set (so that the clts/stts pair does nothing that is | |
43 | * visible in the interrupted kernel thread). | |
5187b28f | 44 | * |
4b2e762e ON |
45 | * Except for the eagerfpu case when we return true; in the likely case |
46 | * the thread has FPU but we are not going to set/clear TS. | |
8546c008 LT |
47 | */ |
48 | static inline bool interrupted_kernel_fpu_idle(void) | |
49 | { | |
14e153ef ON |
50 | if (this_cpu_read(in_kernel_fpu)) |
51 | return false; | |
52 | ||
5d2bd700 | 53 | if (use_eager_fpu()) |
4b2e762e | 54 | return true; |
304bceda | 55 | |
8546c008 LT |
56 | return !__thread_has_fpu(current) && |
57 | (read_cr0() & X86_CR0_TS); | |
58 | } | |
59 | ||
60 | /* | |
61 | * Were we in user mode (or vm86 mode) when we were | |
62 | * interrupted? | |
63 | * | |
64 | * Doing kernel_fpu_begin/end() is ok if we are running | |
65 | * in an interrupt context from user mode - we'll just | |
66 | * save the FPU state as required. | |
67 | */ | |
68 | static inline bool interrupted_user_mode(void) | |
69 | { | |
70 | struct pt_regs *regs = get_irq_regs(); | |
f39b6f0e | 71 | return regs && user_mode(regs); |
8546c008 LT |
72 | } |
73 | ||
74 | /* | |
75 | * Can we use the FPU in kernel mode with the | |
76 | * whole "kernel_fpu_begin/end()" sequence? | |
77 | * | |
78 | * It's always ok in process context (ie "not interrupt") | |
79 | * but it is sometimes ok even from an irq. | |
80 | */ | |
81 | bool irq_fpu_usable(void) | |
82 | { | |
83 | return !in_interrupt() || | |
84 | interrupted_user_mode() || | |
85 | interrupted_kernel_fpu_idle(); | |
86 | } | |
87 | EXPORT_SYMBOL(irq_fpu_usable); | |
88 | ||
b1a74bf8 | 89 | void __kernel_fpu_begin(void) |
8546c008 LT |
90 | { |
91 | struct task_struct *me = current; | |
92 | ||
14e153ef ON |
93 | this_cpu_write(in_kernel_fpu, true); |
94 | ||
8546c008 | 95 | if (__thread_has_fpu(me)) { |
5187b28f | 96 | __save_init_fpu(me); |
7aeccb83 | 97 | } else { |
c6ae41e7 | 98 | this_cpu_write(fpu_owner_task, NULL); |
7aeccb83 ON |
99 | if (!use_eager_fpu()) |
100 | clts(); | |
8546c008 LT |
101 | } |
102 | } | |
b1a74bf8 | 103 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 104 | |
b1a74bf8 | 105 | void __kernel_fpu_end(void) |
8546c008 | 106 | { |
33a3ebdc ON |
107 | struct task_struct *me = current; |
108 | ||
109 | if (__thread_has_fpu(me)) { | |
110 | if (WARN_ON(restore_fpu_checking(me))) | |
b85e67d1 | 111 | fpu_reset_state(me); |
33a3ebdc | 112 | } else if (!use_eager_fpu()) { |
304bceda | 113 | stts(); |
731bd6a9 | 114 | } |
14e153ef ON |
115 | |
116 | this_cpu_write(in_kernel_fpu, false); | |
8546c008 | 117 | } |
b1a74bf8 | 118 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 | 119 | |
4af08f2f IM |
120 | /* |
121 | * Save the FPU state (initialize it if necessary): | |
87cdb98a IM |
122 | * |
123 | * This only ever gets called for the current task. | |
4af08f2f | 124 | */ |
0a781551 | 125 | void fpu__save(struct task_struct *tsk) |
8546c008 | 126 | { |
87cdb98a IM |
127 | WARN_ON(tsk != current); |
128 | ||
8546c008 LT |
129 | preempt_disable(); |
130 | if (__thread_has_fpu(tsk)) { | |
1a2a7f4e ON |
131 | if (use_eager_fpu()) { |
132 | __save_fpu(tsk); | |
133 | } else { | |
134 | __save_init_fpu(tsk); | |
135 | __thread_fpu_end(tsk); | |
136 | } | |
a9241ea5 | 137 | } |
8546c008 LT |
138 | preempt_enable(); |
139 | } | |
4af08f2f | 140 | EXPORT_SYMBOL_GPL(fpu__save); |
8546c008 | 141 | |
72a671ce | 142 | unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 143 | unsigned int xstate_size; |
f45755b8 | 144 | EXPORT_SYMBOL_GPL(xstate_size); |
148f9bb8 | 145 | static struct i387_fxsave_struct fx_scratch; |
1da177e4 | 146 | |
148f9bb8 | 147 | static void mxcsr_feature_mask_init(void) |
1da177e4 LT |
148 | { |
149 | unsigned long mask = 0; | |
f668964e | 150 | |
1da177e4 | 151 | if (cpu_has_fxsr) { |
61c4628b | 152 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
eaa5a990 | 153 | asm volatile("fxsave %0" : "+m" (fx_scratch)); |
61c4628b | 154 | mask = fx_scratch.mxcsr_mask; |
3b095a04 CG |
155 | if (mask == 0) |
156 | mask = 0x0000ffbf; | |
157 | } | |
1da177e4 | 158 | mxcsr_feature_mask &= mask; |
1da177e4 LT |
159 | } |
160 | ||
148f9bb8 | 161 | static void init_thread_xstate(void) |
61c4628b | 162 | { |
0e49bf66 RR |
163 | /* |
164 | * Note that xstate_size might be overwriten later during | |
165 | * xsave_init(). | |
166 | */ | |
167 | ||
60e019eb | 168 | if (!cpu_has_fpu) { |
1f999ab5 RR |
169 | /* |
170 | * Disable xsave as we do not support it if i387 | |
171 | * emulation is enabled. | |
172 | */ | |
173 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
174 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
e8a496ac SS |
175 | xstate_size = sizeof(struct i387_soft_struct); |
176 | return; | |
177 | } | |
178 | ||
61c4628b SS |
179 | if (cpu_has_fxsr) |
180 | xstate_size = sizeof(struct i387_fxsave_struct); | |
61c4628b SS |
181 | else |
182 | xstate_size = sizeof(struct i387_fsave_struct); | |
61c4628b SS |
183 | } |
184 | ||
44210111 RM |
185 | /* |
186 | * Called at bootup to set up the initial FPU state that is later cloned | |
187 | * into all processes. | |
188 | */ | |
0e49bf66 | 189 | |
148f9bb8 | 190 | void fpu_init(void) |
44210111 | 191 | { |
6ac8bac2 BG |
192 | unsigned long cr0; |
193 | unsigned long cr4_mask = 0; | |
44210111 | 194 | |
60e019eb PA |
195 | #ifndef CONFIG_MATH_EMULATION |
196 | if (!cpu_has_fpu) { | |
197 | pr_emerg("No FPU found and no math emulation present\n"); | |
198 | pr_emerg("Giving up\n"); | |
199 | for (;;) | |
200 | asm volatile("hlt"); | |
201 | } | |
202 | #endif | |
6ac8bac2 BG |
203 | if (cpu_has_fxsr) |
204 | cr4_mask |= X86_CR4_OSFXSR; | |
205 | if (cpu_has_xmm) | |
206 | cr4_mask |= X86_CR4_OSXMMEXCPT; | |
207 | if (cr4_mask) | |
375074cc | 208 | cr4_set_bits(cr4_mask); |
6ac8bac2 BG |
209 | |
210 | cr0 = read_cr0(); | |
211 | cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ | |
60e019eb | 212 | if (!cpu_has_fpu) |
6ac8bac2 BG |
213 | cr0 |= X86_CR0_EM; |
214 | write_cr0(cr0); | |
44210111 | 215 | |
6f5298c2 FY |
216 | /* |
217 | * init_thread_xstate is only called once to avoid overriding | |
218 | * xstate_size during boot time or during CPU hotplug. | |
219 | */ | |
220 | if (xstate_size == 0) | |
dc1e35c6 | 221 | init_thread_xstate(); |
dc1e35c6 | 222 | |
44210111 | 223 | mxcsr_feature_mask_init(); |
5d2bd700 SS |
224 | xsave_init(); |
225 | eager_fpu_init(); | |
44210111 | 226 | } |
0e49bf66 | 227 | |
5ee481da | 228 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 229 | { |
60e019eb | 230 | if (!cpu_has_fpu) { |
86603283 AK |
231 | finit_soft_fpu(&fpu->state->soft); |
232 | return; | |
e8a496ac | 233 | } |
e8a496ac | 234 | |
1d23c451 ON |
235 | memset(fpu->state, 0, xstate_size); |
236 | ||
1da177e4 | 237 | if (cpu_has_fxsr) { |
5d2bd700 | 238 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 239 | } else { |
86603283 | 240 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
241 | fp->cwd = 0xffff037fu; |
242 | fp->swd = 0xffff0000u; | |
243 | fp->twd = 0xffffffffu; | |
244 | fp->fos = 0xffff0000u; | |
1da177e4 | 245 | } |
86603283 | 246 | } |
5ee481da | 247 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 | 248 | |
97185c95 IM |
249 | /* |
250 | * Allocate the backing store for the current task's FPU registers | |
251 | * and initialize the registers themselves as well. | |
252 | * | |
253 | * Can fail. | |
254 | */ | |
255 | int fpstate_alloc_init(struct task_struct *curr) | |
256 | { | |
257 | int ret; | |
258 | ||
259 | if (WARN_ON_ONCE(curr != current)) | |
260 | return -EINVAL; | |
261 | if (WARN_ON_ONCE(curr->flags & PF_USED_MATH)) | |
262 | return -EINVAL; | |
263 | ||
264 | /* | |
265 | * Memory allocation at the first usage of the FPU and other state. | |
266 | */ | |
267 | ret = fpu_alloc(&curr->thread.fpu); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | fpu_finit(&curr->thread.fpu); | |
272 | ||
273 | /* Safe to do for the current task: */ | |
274 | curr->flags |= PF_USED_MATH; | |
275 | ||
276 | return 0; | |
277 | } | |
278 | EXPORT_SYMBOL_GPL(fpstate_alloc_init); | |
279 | ||
86603283 AK |
280 | /* |
281 | * The _current_ task is using the FPU for the first time | |
282 | * so initialize it and set the mxcsr to its default | |
283 | * value at reset if we support XMM instructions and then | |
0d2eb44f | 284 | * remember the current task has used the FPU. |
86603283 | 285 | */ |
bda28379 | 286 | static int init_fpu(struct task_struct *tsk) |
86603283 AK |
287 | { |
288 | int ret; | |
289 | ||
290 | if (tsk_used_math(tsk)) { | |
60e019eb | 291 | if (cpu_has_fpu && tsk == current) |
0a781551 | 292 | fpu__save(tsk); |
6a5fe895 | 293 | task_disable_lazy_fpu_restore(tsk); |
86603283 AK |
294 | return 0; |
295 | } | |
296 | ||
44210111 | 297 | /* |
86603283 | 298 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 299 | */ |
86603283 AK |
300 | ret = fpu_alloc(&tsk->thread.fpu); |
301 | if (ret) | |
302 | return ret; | |
303 | ||
304 | fpu_finit(&tsk->thread.fpu); | |
305 | ||
1da177e4 | 306 | set_stopped_child_used_math(tsk); |
aa283f49 | 307 | return 0; |
1da177e4 LT |
308 | } |
309 | ||
5b3efd50 SS |
310 | /* |
311 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
312 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
313 | * capabilites supported by the xsave. | |
314 | */ | |
44210111 RM |
315 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
316 | { | |
317 | return tsk_used_math(target) ? regset->n : 0; | |
318 | } | |
1da177e4 | 319 | |
44210111 | 320 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 321 | { |
44210111 RM |
322 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
323 | } | |
1da177e4 | 324 | |
44210111 RM |
325 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
326 | unsigned int pos, unsigned int count, | |
327 | void *kbuf, void __user *ubuf) | |
328 | { | |
aa283f49 SS |
329 | int ret; |
330 | ||
44210111 RM |
331 | if (!cpu_has_fxsr) |
332 | return -ENODEV; | |
333 | ||
aa283f49 SS |
334 | ret = init_fpu(target); |
335 | if (ret) | |
336 | return ret; | |
44210111 | 337 | |
29104e10 SS |
338 | sanitize_i387_state(target); |
339 | ||
44210111 | 340 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 341 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 342 | } |
44210111 RM |
343 | |
344 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
345 | unsigned int pos, unsigned int count, | |
346 | const void *kbuf, const void __user *ubuf) | |
347 | { | |
348 | int ret; | |
349 | ||
350 | if (!cpu_has_fxsr) | |
351 | return -ENODEV; | |
352 | ||
aa283f49 SS |
353 | ret = init_fpu(target); |
354 | if (ret) | |
355 | return ret; | |
356 | ||
29104e10 SS |
357 | sanitize_i387_state(target); |
358 | ||
44210111 | 359 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 360 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
361 | |
362 | /* | |
363 | * mxcsr reserved bits must be masked to zero for security reasons. | |
364 | */ | |
86603283 | 365 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 366 | |
42deec6f SS |
367 | /* |
368 | * update the header bits in the xsave header, indicating the | |
369 | * presence of FP and SSE state. | |
370 | */ | |
371 | if (cpu_has_xsave) | |
86603283 | 372 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 373 | |
44210111 RM |
374 | return ret; |
375 | } | |
376 | ||
5b3efd50 SS |
377 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
378 | unsigned int pos, unsigned int count, | |
379 | void *kbuf, void __user *ubuf) | |
380 | { | |
18ecb3bf | 381 | struct xsave_struct *xsave; |
5b3efd50 SS |
382 | int ret; |
383 | ||
384 | if (!cpu_has_xsave) | |
385 | return -ENODEV; | |
386 | ||
387 | ret = init_fpu(target); | |
388 | if (ret) | |
389 | return ret; | |
390 | ||
18ecb3bf BP |
391 | xsave = &target->thread.fpu.state->xsave; |
392 | ||
5b3efd50 | 393 | /* |
ff7fbc72 SS |
394 | * Copy the 48bytes defined by the software first into the xstate |
395 | * memory layout in the thread struct, so that we can copy the entire | |
396 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 397 | */ |
e7f180dc ON |
398 | memcpy(&xsave->i387.sw_reserved, |
399 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 | 400 | /* |
ff7fbc72 | 401 | * Copy the xstate memory layout. |
5b3efd50 | 402 | */ |
e7f180dc | 403 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
404 | return ret; |
405 | } | |
406 | ||
407 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
408 | unsigned int pos, unsigned int count, | |
409 | const void *kbuf, const void __user *ubuf) | |
410 | { | |
18ecb3bf | 411 | struct xsave_struct *xsave; |
5b3efd50 | 412 | int ret; |
5b3efd50 SS |
413 | |
414 | if (!cpu_has_xsave) | |
415 | return -ENODEV; | |
416 | ||
417 | ret = init_fpu(target); | |
418 | if (ret) | |
419 | return ret; | |
420 | ||
18ecb3bf BP |
421 | xsave = &target->thread.fpu.state->xsave; |
422 | ||
e7f180dc | 423 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
424 | /* |
425 | * mxcsr reserved bits must be masked to zero for security reasons. | |
426 | */ | |
e7f180dc ON |
427 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
428 | xsave->xsave_hdr.xstate_bv &= pcntxt_mask; | |
5b3efd50 SS |
429 | /* |
430 | * These bits must be zero. | |
431 | */ | |
e7f180dc | 432 | memset(&xsave->xsave_hdr.reserved, 0, 48); |
5b3efd50 SS |
433 | return ret; |
434 | } | |
435 | ||
44210111 | 436 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 437 | |
1da177e4 LT |
438 | /* |
439 | * FPU tag word conversions. | |
440 | */ | |
441 | ||
3b095a04 | 442 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
443 | { |
444 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 445 | |
1da177e4 | 446 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 447 | tmp = ~twd; |
44210111 | 448 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
449 | /* and move the valid bits to the lower byte. */ |
450 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
451 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
452 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 453 | |
3b095a04 | 454 | return tmp; |
1da177e4 LT |
455 | } |
456 | ||
497888cf | 457 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
458 | #define FP_EXP_TAG_VALID 0 |
459 | #define FP_EXP_TAG_ZERO 1 | |
460 | #define FP_EXP_TAG_SPECIAL 2 | |
461 | #define FP_EXP_TAG_EMPTY 3 | |
462 | ||
463 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
464 | { | |
465 | struct _fpxreg *st; | |
466 | u32 tos = (fxsave->swd >> 11) & 7; | |
467 | u32 twd = (unsigned long) fxsave->twd; | |
468 | u32 tag; | |
469 | u32 ret = 0xffff0000u; | |
470 | int i; | |
1da177e4 | 471 | |
44210111 | 472 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
473 | if (twd & 0x1) { |
474 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 475 | |
3b095a04 | 476 | switch (st->exponent & 0x7fff) { |
1da177e4 | 477 | case 0x7fff: |
44210111 | 478 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
479 | break; |
480 | case 0x0000: | |
3b095a04 CG |
481 | if (!st->significand[0] && |
482 | !st->significand[1] && | |
483 | !st->significand[2] && | |
44210111 RM |
484 | !st->significand[3]) |
485 | tag = FP_EXP_TAG_ZERO; | |
486 | else | |
487 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
488 | break; |
489 | default: | |
44210111 RM |
490 | if (st->significand[3] & 0x8000) |
491 | tag = FP_EXP_TAG_VALID; | |
492 | else | |
493 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
494 | break; |
495 | } | |
496 | } else { | |
44210111 | 497 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 498 | } |
44210111 | 499 | ret |= tag << (2 * i); |
1da177e4 LT |
500 | } |
501 | return ret; | |
502 | } | |
503 | ||
504 | /* | |
44210111 | 505 | * FXSR floating point environment conversions. |
1da177e4 LT |
506 | */ |
507 | ||
72a671ce | 508 | void |
f668964e | 509 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 510 | { |
86603283 | 511 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
512 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
513 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
514 | int i; | |
1da177e4 | 515 | |
44210111 RM |
516 | env->cwd = fxsave->cwd | 0xffff0000u; |
517 | env->swd = fxsave->swd | 0xffff0000u; | |
518 | env->twd = twd_fxsr_to_i387(fxsave); | |
519 | ||
520 | #ifdef CONFIG_X86_64 | |
521 | env->fip = fxsave->rip; | |
522 | env->foo = fxsave->rdp; | |
10c11f30 BG |
523 | /* |
524 | * should be actually ds/cs at fpu exception time, but | |
525 | * that information is not available in 64bit mode. | |
526 | */ | |
527 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 528 | if (tsk == current) { |
10c11f30 | 529 | savesegment(ds, env->fos); |
1da177e4 | 530 | } else { |
10c11f30 | 531 | env->fos = tsk->thread.ds; |
1da177e4 | 532 | } |
10c11f30 | 533 | env->fos |= 0xffff0000; |
44210111 RM |
534 | #else |
535 | env->fip = fxsave->fip; | |
609b5297 | 536 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
537 | env->foo = fxsave->foo; |
538 | env->fos = fxsave->fos; | |
539 | #endif | |
1da177e4 | 540 | |
44210111 RM |
541 | for (i = 0; i < 8; ++i) |
542 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
543 | } |
544 | ||
72a671ce SS |
545 | void convert_to_fxsr(struct task_struct *tsk, |
546 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 547 | |
1da177e4 | 548 | { |
86603283 | 549 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
550 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
551 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
552 | int i; | |
1da177e4 | 553 | |
44210111 RM |
554 | fxsave->cwd = env->cwd; |
555 | fxsave->swd = env->swd; | |
556 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
557 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
558 | #ifdef CONFIG_X86_64 | |
559 | fxsave->rip = env->fip; | |
560 | fxsave->rdp = env->foo; | |
561 | /* cs and ds ignored */ | |
562 | #else | |
563 | fxsave->fip = env->fip; | |
564 | fxsave->fcs = (env->fcs & 0xffff); | |
565 | fxsave->foo = env->foo; | |
566 | fxsave->fos = env->fos; | |
567 | #endif | |
1da177e4 | 568 | |
44210111 RM |
569 | for (i = 0; i < 8; ++i) |
570 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
571 | } |
572 | ||
44210111 RM |
573 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
574 | unsigned int pos, unsigned int count, | |
575 | void *kbuf, void __user *ubuf) | |
1da177e4 | 576 | { |
44210111 | 577 | struct user_i387_ia32_struct env; |
aa283f49 | 578 | int ret; |
1da177e4 | 579 | |
aa283f49 SS |
580 | ret = init_fpu(target); |
581 | if (ret) | |
582 | return ret; | |
1da177e4 | 583 | |
60e019eb | 584 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
585 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
586 | ||
60e019eb | 587 | if (!cpu_has_fxsr) |
44210111 | 588 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 589 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 590 | -1); |
1da177e4 | 591 | |
29104e10 SS |
592 | sanitize_i387_state(target); |
593 | ||
44210111 RM |
594 | if (kbuf && pos == 0 && count == sizeof(env)) { |
595 | convert_from_fxsr(kbuf, target); | |
596 | return 0; | |
1da177e4 | 597 | } |
44210111 RM |
598 | |
599 | convert_from_fxsr(&env, target); | |
f668964e | 600 | |
44210111 | 601 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
602 | } |
603 | ||
44210111 RM |
604 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
605 | unsigned int pos, unsigned int count, | |
606 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 607 | { |
44210111 RM |
608 | struct user_i387_ia32_struct env; |
609 | int ret; | |
1da177e4 | 610 | |
aa283f49 SS |
611 | ret = init_fpu(target); |
612 | if (ret) | |
613 | return ret; | |
614 | ||
29104e10 SS |
615 | sanitize_i387_state(target); |
616 | ||
60e019eb | 617 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
618 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
619 | ||
60e019eb | 620 | if (!cpu_has_fxsr) |
44210111 | 621 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
60e019eb PA |
622 | &target->thread.fpu.state->fsave, 0, |
623 | -1); | |
44210111 RM |
624 | |
625 | if (pos > 0 || count < sizeof(env)) | |
626 | convert_from_fxsr(&env, target); | |
627 | ||
628 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
629 | if (!ret) | |
630 | convert_to_fxsr(target, &env); | |
631 | ||
42deec6f SS |
632 | /* |
633 | * update the header bit in the xsave header, indicating the | |
634 | * presence of FP. | |
635 | */ | |
636 | if (cpu_has_xsave) | |
86603283 | 637 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 638 | return ret; |
1da177e4 LT |
639 | } |
640 | ||
1da177e4 LT |
641 | /* |
642 | * FPU state for core dumps. | |
60b3b9af RM |
643 | * This is only used for a.out dumps now. |
644 | * It is declared generically using elf_fpregset_t (which is | |
645 | * struct user_i387_struct) but is in fact only used for 32-bit | |
646 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 647 | */ |
3b095a04 | 648 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 649 | { |
1da177e4 | 650 | struct task_struct *tsk = current; |
f668964e | 651 | int fpvalid; |
1da177e4 LT |
652 | |
653 | fpvalid = !!used_math(); | |
60b3b9af RM |
654 | if (fpvalid) |
655 | fpvalid = !fpregs_get(tsk, NULL, | |
656 | 0, sizeof(struct user_i387_ia32_struct), | |
657 | fpu, NULL); | |
1da177e4 LT |
658 | |
659 | return fpvalid; | |
660 | } | |
129f6946 | 661 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 662 | |
60b3b9af | 663 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |
60e019eb PA |
664 | |
665 | static int __init no_387(char *s) | |
666 | { | |
667 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
668 | return 1; | |
669 | } | |
670 | ||
671 | __setup("no387", no_387); | |
672 | ||
1a7dc0db IM |
673 | /* |
674 | * Set the X86_FEATURE_FPU CPU-capability bit based on | |
675 | * trying to execute an actual sequence of FPU instructions: | |
676 | */ | |
677 | void fpu__detect(struct cpuinfo_x86 *c) | |
60e019eb PA |
678 | { |
679 | unsigned long cr0; | |
680 | u16 fsw, fcw; | |
681 | ||
682 | fsw = fcw = 0xffff; | |
683 | ||
684 | cr0 = read_cr0(); | |
685 | cr0 &= ~(X86_CR0_TS | X86_CR0_EM); | |
686 | write_cr0(cr0); | |
687 | ||
688 | asm volatile("fninit ; fnstsw %0 ; fnstcw %1" | |
689 | : "+m" (fsw), "+m" (fcw)); | |
690 | ||
691 | if (fsw == 0 && (fcw & 0x103f) == 0x003f) | |
692 | set_cpu_cap(c, X86_FEATURE_FPU); | |
693 | else | |
694 | clear_cpu_cap(c, X86_FEATURE_FPU); | |
695 | ||
696 | /* The final cr0 value is set in fpu_init() */ | |
697 | } |