Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
1da177e4 | 16 | #include <asm/uaccess.h> |
f668964e IM |
17 | #include <asm/ptrace.h> |
18 | #include <asm/i387.h> | |
1361b83a | 19 | #include <asm/fpu-internal.h> |
f668964e | 20 | #include <asm/user.h> |
1da177e4 | 21 | |
8546c008 LT |
22 | /* |
23 | * Were we in an interrupt that interrupted kernel mode? | |
24 | * | |
304bceda | 25 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
26 | * pair does nothing at all: the thread must not have fpu (so |
27 | * that we don't try to save the FPU state), and TS must | |
28 | * be set (so that the clts/stts pair does nothing that is | |
29 | * visible in the interrupted kernel thread). | |
5187b28f PR |
30 | * |
31 | * Except for the eagerfpu case when we return 1 unless we've already | |
32 | * been eager and saved the state in kernel_fpu_begin(). | |
8546c008 LT |
33 | */ |
34 | static inline bool interrupted_kernel_fpu_idle(void) | |
35 | { | |
5d2bd700 | 36 | if (use_eager_fpu()) |
5187b28f | 37 | return __thread_has_fpu(current); |
304bceda | 38 | |
8546c008 LT |
39 | return !__thread_has_fpu(current) && |
40 | (read_cr0() & X86_CR0_TS); | |
41 | } | |
42 | ||
43 | /* | |
44 | * Were we in user mode (or vm86 mode) when we were | |
45 | * interrupted? | |
46 | * | |
47 | * Doing kernel_fpu_begin/end() is ok if we are running | |
48 | * in an interrupt context from user mode - we'll just | |
49 | * save the FPU state as required. | |
50 | */ | |
51 | static inline bool interrupted_user_mode(void) | |
52 | { | |
53 | struct pt_regs *regs = get_irq_regs(); | |
54 | return regs && user_mode_vm(regs); | |
55 | } | |
56 | ||
57 | /* | |
58 | * Can we use the FPU in kernel mode with the | |
59 | * whole "kernel_fpu_begin/end()" sequence? | |
60 | * | |
61 | * It's always ok in process context (ie "not interrupt") | |
62 | * but it is sometimes ok even from an irq. | |
63 | */ | |
64 | bool irq_fpu_usable(void) | |
65 | { | |
66 | return !in_interrupt() || | |
67 | interrupted_user_mode() || | |
68 | interrupted_kernel_fpu_idle(); | |
69 | } | |
70 | EXPORT_SYMBOL(irq_fpu_usable); | |
71 | ||
b1a74bf8 | 72 | void __kernel_fpu_begin(void) |
8546c008 LT |
73 | { |
74 | struct task_struct *me = current; | |
75 | ||
8546c008 | 76 | if (__thread_has_fpu(me)) { |
8546c008 | 77 | __thread_clear_has_fpu(me); |
5187b28f | 78 | __save_init_fpu(me); |
b1a74bf8 | 79 | /* We do 'stts()' in __kernel_fpu_end() */ |
5d2bd700 | 80 | } else if (!use_eager_fpu()) { |
c6ae41e7 | 81 | this_cpu_write(fpu_owner_task, NULL); |
8546c008 LT |
82 | clts(); |
83 | } | |
84 | } | |
b1a74bf8 | 85 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 86 | |
b1a74bf8 | 87 | void __kernel_fpu_end(void) |
8546c008 | 88 | { |
5d2bd700 | 89 | if (use_eager_fpu()) |
304bceda SS |
90 | math_state_restore(); |
91 | else | |
92 | stts(); | |
8546c008 | 93 | } |
b1a74bf8 | 94 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 LT |
95 | |
96 | void unlazy_fpu(struct task_struct *tsk) | |
97 | { | |
98 | preempt_disable(); | |
99 | if (__thread_has_fpu(tsk)) { | |
100 | __save_init_fpu(tsk); | |
101 | __thread_fpu_end(tsk); | |
102 | } else | |
103 | tsk->fpu_counter = 0; | |
104 | preempt_enable(); | |
105 | } | |
106 | EXPORT_SYMBOL(unlazy_fpu); | |
107 | ||
72a671ce | 108 | unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 109 | unsigned int xstate_size; |
f45755b8 | 110 | EXPORT_SYMBOL_GPL(xstate_size); |
61c4628b | 111 | static struct i387_fxsave_struct fx_scratch __cpuinitdata; |
1da177e4 | 112 | |
1361b83a | 113 | static void __cpuinit mxcsr_feature_mask_init(void) |
1da177e4 LT |
114 | { |
115 | unsigned long mask = 0; | |
f668964e | 116 | |
1da177e4 | 117 | if (cpu_has_fxsr) { |
61c4628b SS |
118 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
119 | asm volatile("fxsave %0" : : "m" (fx_scratch)); | |
120 | mask = fx_scratch.mxcsr_mask; | |
3b095a04 CG |
121 | if (mask == 0) |
122 | mask = 0x0000ffbf; | |
123 | } | |
1da177e4 | 124 | mxcsr_feature_mask &= mask; |
1da177e4 LT |
125 | } |
126 | ||
0e49bf66 | 127 | static void __cpuinit init_thread_xstate(void) |
61c4628b | 128 | { |
0e49bf66 RR |
129 | /* |
130 | * Note that xstate_size might be overwriten later during | |
131 | * xsave_init(). | |
132 | */ | |
133 | ||
e8a496ac | 134 | if (!HAVE_HWFP) { |
1f999ab5 RR |
135 | /* |
136 | * Disable xsave as we do not support it if i387 | |
137 | * emulation is enabled. | |
138 | */ | |
139 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
140 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
e8a496ac SS |
141 | xstate_size = sizeof(struct i387_soft_struct); |
142 | return; | |
143 | } | |
144 | ||
61c4628b SS |
145 | if (cpu_has_fxsr) |
146 | xstate_size = sizeof(struct i387_fxsave_struct); | |
61c4628b SS |
147 | else |
148 | xstate_size = sizeof(struct i387_fsave_struct); | |
61c4628b SS |
149 | } |
150 | ||
44210111 RM |
151 | /* |
152 | * Called at bootup to set up the initial FPU state that is later cloned | |
153 | * into all processes. | |
154 | */ | |
0e49bf66 | 155 | |
44210111 RM |
156 | void __cpuinit fpu_init(void) |
157 | { | |
6ac8bac2 BG |
158 | unsigned long cr0; |
159 | unsigned long cr4_mask = 0; | |
44210111 | 160 | |
6ac8bac2 BG |
161 | if (cpu_has_fxsr) |
162 | cr4_mask |= X86_CR4_OSFXSR; | |
163 | if (cpu_has_xmm) | |
164 | cr4_mask |= X86_CR4_OSXMMEXCPT; | |
165 | if (cr4_mask) | |
166 | set_in_cr4(cr4_mask); | |
167 | ||
168 | cr0 = read_cr0(); | |
169 | cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ | |
170 | if (!HAVE_HWFP) | |
171 | cr0 |= X86_CR0_EM; | |
172 | write_cr0(cr0); | |
44210111 | 173 | |
6f5298c2 FY |
174 | /* |
175 | * init_thread_xstate is only called once to avoid overriding | |
176 | * xstate_size during boot time or during CPU hotplug. | |
177 | */ | |
178 | if (xstate_size == 0) | |
dc1e35c6 | 179 | init_thread_xstate(); |
dc1e35c6 | 180 | |
44210111 | 181 | mxcsr_feature_mask_init(); |
5d2bd700 SS |
182 | xsave_init(); |
183 | eager_fpu_init(); | |
44210111 | 184 | } |
0e49bf66 | 185 | |
5ee481da | 186 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 187 | { |
e8a496ac | 188 | if (!HAVE_HWFP) { |
86603283 AK |
189 | finit_soft_fpu(&fpu->state->soft); |
190 | return; | |
e8a496ac | 191 | } |
e8a496ac | 192 | |
1da177e4 | 193 | if (cpu_has_fxsr) { |
5d2bd700 | 194 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 195 | } else { |
86603283 | 196 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
197 | memset(fp, 0, xstate_size); |
198 | fp->cwd = 0xffff037fu; | |
199 | fp->swd = 0xffff0000u; | |
200 | fp->twd = 0xffffffffu; | |
201 | fp->fos = 0xffff0000u; | |
1da177e4 | 202 | } |
86603283 | 203 | } |
5ee481da | 204 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 AK |
205 | |
206 | /* | |
207 | * The _current_ task is using the FPU for the first time | |
208 | * so initialize it and set the mxcsr to its default | |
209 | * value at reset if we support XMM instructions and then | |
0d2eb44f | 210 | * remember the current task has used the FPU. |
86603283 AK |
211 | */ |
212 | int init_fpu(struct task_struct *tsk) | |
213 | { | |
214 | int ret; | |
215 | ||
216 | if (tsk_used_math(tsk)) { | |
217 | if (HAVE_HWFP && tsk == current) | |
218 | unlazy_fpu(tsk); | |
089f9fba | 219 | tsk->thread.fpu.last_cpu = ~0; |
86603283 AK |
220 | return 0; |
221 | } | |
222 | ||
44210111 | 223 | /* |
86603283 | 224 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 225 | */ |
86603283 AK |
226 | ret = fpu_alloc(&tsk->thread.fpu); |
227 | if (ret) | |
228 | return ret; | |
229 | ||
230 | fpu_finit(&tsk->thread.fpu); | |
231 | ||
1da177e4 | 232 | set_stopped_child_used_math(tsk); |
aa283f49 | 233 | return 0; |
1da177e4 | 234 | } |
e5c30142 | 235 | EXPORT_SYMBOL_GPL(init_fpu); |
1da177e4 | 236 | |
5b3efd50 SS |
237 | /* |
238 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
239 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
240 | * capabilites supported by the xsave. | |
241 | */ | |
44210111 RM |
242 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
243 | { | |
244 | return tsk_used_math(target) ? regset->n : 0; | |
245 | } | |
1da177e4 | 246 | |
44210111 | 247 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 248 | { |
44210111 RM |
249 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
250 | } | |
1da177e4 | 251 | |
44210111 RM |
252 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
253 | unsigned int pos, unsigned int count, | |
254 | void *kbuf, void __user *ubuf) | |
255 | { | |
aa283f49 SS |
256 | int ret; |
257 | ||
44210111 RM |
258 | if (!cpu_has_fxsr) |
259 | return -ENODEV; | |
260 | ||
aa283f49 SS |
261 | ret = init_fpu(target); |
262 | if (ret) | |
263 | return ret; | |
44210111 | 264 | |
29104e10 SS |
265 | sanitize_i387_state(target); |
266 | ||
44210111 | 267 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 268 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 269 | } |
44210111 RM |
270 | |
271 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
272 | unsigned int pos, unsigned int count, | |
273 | const void *kbuf, const void __user *ubuf) | |
274 | { | |
275 | int ret; | |
276 | ||
277 | if (!cpu_has_fxsr) | |
278 | return -ENODEV; | |
279 | ||
aa283f49 SS |
280 | ret = init_fpu(target); |
281 | if (ret) | |
282 | return ret; | |
283 | ||
29104e10 SS |
284 | sanitize_i387_state(target); |
285 | ||
44210111 | 286 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 287 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
288 | |
289 | /* | |
290 | * mxcsr reserved bits must be masked to zero for security reasons. | |
291 | */ | |
86603283 | 292 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 293 | |
42deec6f SS |
294 | /* |
295 | * update the header bits in the xsave header, indicating the | |
296 | * presence of FP and SSE state. | |
297 | */ | |
298 | if (cpu_has_xsave) | |
86603283 | 299 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 300 | |
44210111 RM |
301 | return ret; |
302 | } | |
303 | ||
5b3efd50 SS |
304 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
305 | unsigned int pos, unsigned int count, | |
306 | void *kbuf, void __user *ubuf) | |
307 | { | |
308 | int ret; | |
309 | ||
310 | if (!cpu_has_xsave) | |
311 | return -ENODEV; | |
312 | ||
313 | ret = init_fpu(target); | |
314 | if (ret) | |
315 | return ret; | |
316 | ||
317 | /* | |
ff7fbc72 SS |
318 | * Copy the 48bytes defined by the software first into the xstate |
319 | * memory layout in the thread struct, so that we can copy the entire | |
320 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 321 | */ |
86603283 | 322 | memcpy(&target->thread.fpu.state->fxsave.sw_reserved, |
ff7fbc72 | 323 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); |
5b3efd50 SS |
324 | |
325 | /* | |
ff7fbc72 | 326 | * Copy the xstate memory layout. |
5b3efd50 SS |
327 | */ |
328 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
86603283 | 329 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
330 | return ret; |
331 | } | |
332 | ||
333 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
334 | unsigned int pos, unsigned int count, | |
335 | const void *kbuf, const void __user *ubuf) | |
336 | { | |
337 | int ret; | |
338 | struct xsave_hdr_struct *xsave_hdr; | |
339 | ||
340 | if (!cpu_has_xsave) | |
341 | return -ENODEV; | |
342 | ||
343 | ret = init_fpu(target); | |
344 | if (ret) | |
345 | return ret; | |
346 | ||
347 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
86603283 | 348 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
349 | |
350 | /* | |
351 | * mxcsr reserved bits must be masked to zero for security reasons. | |
352 | */ | |
86603283 | 353 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
5b3efd50 | 354 | |
86603283 | 355 | xsave_hdr = &target->thread.fpu.state->xsave.xsave_hdr; |
5b3efd50 SS |
356 | |
357 | xsave_hdr->xstate_bv &= pcntxt_mask; | |
358 | /* | |
359 | * These bits must be zero. | |
360 | */ | |
361 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
44210111 | 366 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 367 | |
1da177e4 LT |
368 | /* |
369 | * FPU tag word conversions. | |
370 | */ | |
371 | ||
3b095a04 | 372 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
373 | { |
374 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 375 | |
1da177e4 | 376 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 377 | tmp = ~twd; |
44210111 | 378 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
379 | /* and move the valid bits to the lower byte. */ |
380 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
381 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
382 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 383 | |
3b095a04 | 384 | return tmp; |
1da177e4 LT |
385 | } |
386 | ||
497888cf | 387 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
388 | #define FP_EXP_TAG_VALID 0 |
389 | #define FP_EXP_TAG_ZERO 1 | |
390 | #define FP_EXP_TAG_SPECIAL 2 | |
391 | #define FP_EXP_TAG_EMPTY 3 | |
392 | ||
393 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
394 | { | |
395 | struct _fpxreg *st; | |
396 | u32 tos = (fxsave->swd >> 11) & 7; | |
397 | u32 twd = (unsigned long) fxsave->twd; | |
398 | u32 tag; | |
399 | u32 ret = 0xffff0000u; | |
400 | int i; | |
1da177e4 | 401 | |
44210111 | 402 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
403 | if (twd & 0x1) { |
404 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 405 | |
3b095a04 | 406 | switch (st->exponent & 0x7fff) { |
1da177e4 | 407 | case 0x7fff: |
44210111 | 408 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
409 | break; |
410 | case 0x0000: | |
3b095a04 CG |
411 | if (!st->significand[0] && |
412 | !st->significand[1] && | |
413 | !st->significand[2] && | |
44210111 RM |
414 | !st->significand[3]) |
415 | tag = FP_EXP_TAG_ZERO; | |
416 | else | |
417 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
418 | break; |
419 | default: | |
44210111 RM |
420 | if (st->significand[3] & 0x8000) |
421 | tag = FP_EXP_TAG_VALID; | |
422 | else | |
423 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
424 | break; |
425 | } | |
426 | } else { | |
44210111 | 427 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 428 | } |
44210111 | 429 | ret |= tag << (2 * i); |
1da177e4 LT |
430 | } |
431 | return ret; | |
432 | } | |
433 | ||
434 | /* | |
44210111 | 435 | * FXSR floating point environment conversions. |
1da177e4 LT |
436 | */ |
437 | ||
72a671ce | 438 | void |
f668964e | 439 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 440 | { |
86603283 | 441 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
442 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
443 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
444 | int i; | |
1da177e4 | 445 | |
44210111 RM |
446 | env->cwd = fxsave->cwd | 0xffff0000u; |
447 | env->swd = fxsave->swd | 0xffff0000u; | |
448 | env->twd = twd_fxsr_to_i387(fxsave); | |
449 | ||
450 | #ifdef CONFIG_X86_64 | |
451 | env->fip = fxsave->rip; | |
452 | env->foo = fxsave->rdp; | |
10c11f30 BG |
453 | /* |
454 | * should be actually ds/cs at fpu exception time, but | |
455 | * that information is not available in 64bit mode. | |
456 | */ | |
457 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 458 | if (tsk == current) { |
10c11f30 | 459 | savesegment(ds, env->fos); |
1da177e4 | 460 | } else { |
10c11f30 | 461 | env->fos = tsk->thread.ds; |
1da177e4 | 462 | } |
10c11f30 | 463 | env->fos |= 0xffff0000; |
44210111 RM |
464 | #else |
465 | env->fip = fxsave->fip; | |
609b5297 | 466 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
467 | env->foo = fxsave->foo; |
468 | env->fos = fxsave->fos; | |
469 | #endif | |
1da177e4 | 470 | |
44210111 RM |
471 | for (i = 0; i < 8; ++i) |
472 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
473 | } |
474 | ||
72a671ce SS |
475 | void convert_to_fxsr(struct task_struct *tsk, |
476 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 477 | |
1da177e4 | 478 | { |
86603283 | 479 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
480 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
481 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
482 | int i; | |
1da177e4 | 483 | |
44210111 RM |
484 | fxsave->cwd = env->cwd; |
485 | fxsave->swd = env->swd; | |
486 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
487 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
488 | #ifdef CONFIG_X86_64 | |
489 | fxsave->rip = env->fip; | |
490 | fxsave->rdp = env->foo; | |
491 | /* cs and ds ignored */ | |
492 | #else | |
493 | fxsave->fip = env->fip; | |
494 | fxsave->fcs = (env->fcs & 0xffff); | |
495 | fxsave->foo = env->foo; | |
496 | fxsave->fos = env->fos; | |
497 | #endif | |
1da177e4 | 498 | |
44210111 RM |
499 | for (i = 0; i < 8; ++i) |
500 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
501 | } |
502 | ||
44210111 RM |
503 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
504 | unsigned int pos, unsigned int count, | |
505 | void *kbuf, void __user *ubuf) | |
1da177e4 | 506 | { |
44210111 | 507 | struct user_i387_ia32_struct env; |
aa283f49 | 508 | int ret; |
1da177e4 | 509 | |
aa283f49 SS |
510 | ret = init_fpu(target); |
511 | if (ret) | |
512 | return ret; | |
1da177e4 | 513 | |
e8a496ac SS |
514 | if (!HAVE_HWFP) |
515 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
516 | ||
f668964e | 517 | if (!cpu_has_fxsr) { |
44210111 | 518 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 519 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 520 | -1); |
f668964e | 521 | } |
1da177e4 | 522 | |
29104e10 SS |
523 | sanitize_i387_state(target); |
524 | ||
44210111 RM |
525 | if (kbuf && pos == 0 && count == sizeof(env)) { |
526 | convert_from_fxsr(kbuf, target); | |
527 | return 0; | |
1da177e4 | 528 | } |
44210111 RM |
529 | |
530 | convert_from_fxsr(&env, target); | |
f668964e | 531 | |
44210111 | 532 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
533 | } |
534 | ||
44210111 RM |
535 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
536 | unsigned int pos, unsigned int count, | |
537 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 538 | { |
44210111 RM |
539 | struct user_i387_ia32_struct env; |
540 | int ret; | |
1da177e4 | 541 | |
aa283f49 SS |
542 | ret = init_fpu(target); |
543 | if (ret) | |
544 | return ret; | |
545 | ||
29104e10 SS |
546 | sanitize_i387_state(target); |
547 | ||
e8a496ac SS |
548 | if (!HAVE_HWFP) |
549 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
550 | ||
f668964e | 551 | if (!cpu_has_fxsr) { |
44210111 | 552 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 553 | &target->thread.fpu.state->fsave, 0, -1); |
f668964e | 554 | } |
44210111 RM |
555 | |
556 | if (pos > 0 || count < sizeof(env)) | |
557 | convert_from_fxsr(&env, target); | |
558 | ||
559 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
560 | if (!ret) | |
561 | convert_to_fxsr(target, &env); | |
562 | ||
42deec6f SS |
563 | /* |
564 | * update the header bit in the xsave header, indicating the | |
565 | * presence of FP. | |
566 | */ | |
567 | if (cpu_has_xsave) | |
86603283 | 568 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 569 | return ret; |
1da177e4 LT |
570 | } |
571 | ||
1da177e4 LT |
572 | /* |
573 | * FPU state for core dumps. | |
60b3b9af RM |
574 | * This is only used for a.out dumps now. |
575 | * It is declared generically using elf_fpregset_t (which is | |
576 | * struct user_i387_struct) but is in fact only used for 32-bit | |
577 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 578 | */ |
3b095a04 | 579 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 580 | { |
1da177e4 | 581 | struct task_struct *tsk = current; |
f668964e | 582 | int fpvalid; |
1da177e4 LT |
583 | |
584 | fpvalid = !!used_math(); | |
60b3b9af RM |
585 | if (fpvalid) |
586 | fpvalid = !fpregs_get(tsk, NULL, | |
587 | 0, sizeof(struct user_i387_ia32_struct), | |
588 | fpu, NULL); | |
1da177e4 LT |
589 | |
590 | return fpvalid; | |
591 | } | |
129f6946 | 592 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 593 | |
60b3b9af | 594 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |