Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/mc146818rtc.h> |
29 | #include <linux/compiler.h> | |
30 | #include <linux/acpi.h> | |
129f6946 | 31 | #include <linux/module.h> |
1da177e4 | 32 | #include <linux/sysdev.h> |
2d3fcc1c | 33 | #include <linux/pci.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
1d16b53e | 38 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/smp.h> | |
42 | #include <asm/desc.h> | |
43 | #include <asm/timer.h> | |
306e440d | 44 | #include <asm/i8259.h> |
3e4ff115 | 45 | #include <asm/nmi.h> |
2d3fcc1c | 46 | #include <asm/msidef.h> |
8b955b0d | 47 | #include <asm/hypertransport.h> |
1da177e4 LT |
48 | |
49 | #include <mach_apic.h> | |
874c4fe3 | 50 | #include <mach_apicdef.h> |
1da177e4 | 51 | |
1da177e4 LT |
52 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
53 | atomic_t irq_mis_count; | |
54 | ||
fcfd636a EB |
55 | /* Where if anywhere is the i8259 connect in external int mode */ |
56 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
57 | ||
1da177e4 | 58 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 59 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 60 | |
f9262c12 AK |
61 | int timer_over_8254 __initdata = 1; |
62 | ||
1da177e4 LT |
63 | /* |
64 | * Is the SiS APIC rmw bug present ? | |
65 | * -1 = don't know, 0 = no, 1 = yes | |
66 | */ | |
67 | int sis_apic_bug = -1; | |
68 | ||
69 | /* | |
70 | * # of IRQ routing registers | |
71 | */ | |
72 | int nr_ioapic_registers[MAX_IO_APICS]; | |
73 | ||
9f640ccb AS |
74 | /* I/O APIC entries */ |
75 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
76 | int nr_ioapics; | |
77 | ||
584f734d AS |
78 | /* MP IRQ source entries */ |
79 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
80 | ||
81 | /* # of MP IRQ source entries */ | |
82 | int mp_irq_entries; | |
83 | ||
1a3f239d | 84 | static int disable_timer_pin_1 __initdata; |
66759a01 | 85 | |
1da177e4 LT |
86 | /* |
87 | * Rough estimation of how many shared IRQs there are, can | |
88 | * be changed anytime. | |
89 | */ | |
90 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
91 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
92 | ||
93 | /* | |
94 | * This is performance-critical, we want to do it O(1) | |
95 | * | |
96 | * the indexing order of this array favors 1:1 mappings | |
97 | * between pins and IRQs. | |
98 | */ | |
99 | ||
100 | static struct irq_pin_list { | |
101 | int apic, pin, next; | |
102 | } irq_2_pin[PIN_MAP_SIZE]; | |
103 | ||
130fe05d LT |
104 | struct io_apic { |
105 | unsigned int index; | |
106 | unsigned int unused[3]; | |
107 | unsigned int data; | |
108 | }; | |
109 | ||
110 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
111 | { | |
112 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
113 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
114 | } | |
115 | ||
116 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
117 | { | |
118 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
119 | writel(reg, &io_apic->index); | |
120 | return readl(&io_apic->data); | |
121 | } | |
122 | ||
123 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
124 | { | |
125 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
126 | writel(reg, &io_apic->index); | |
127 | writel(value, &io_apic->data); | |
128 | } | |
129 | ||
130 | /* | |
131 | * Re-write a value: to be used for read-modify-write | |
132 | * cycles where the read already set up the index register. | |
133 | * | |
134 | * Older SiS APIC requires we rewrite the index register | |
135 | */ | |
136 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
137 | { | |
cb468984 | 138 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
139 | if (sis_apic_bug) |
140 | writel(reg, &io_apic->index); | |
141 | writel(value, &io_apic->data); | |
142 | } | |
143 | ||
cf4c6a2f AK |
144 | union entry_union { |
145 | struct { u32 w1, w2; }; | |
146 | struct IO_APIC_route_entry entry; | |
147 | }; | |
148 | ||
149 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
150 | { | |
151 | union entry_union eu; | |
152 | unsigned long flags; | |
153 | spin_lock_irqsave(&ioapic_lock, flags); | |
154 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
155 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
156 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
157 | return eu.entry; | |
158 | } | |
159 | ||
f9dadfa7 LT |
160 | /* |
161 | * When we write a new IO APIC routing entry, we need to write the high | |
162 | * word first! If the mask bit in the low word is clear, we will enable | |
163 | * the interrupt, and we need to make sure the entry is fully populated | |
164 | * before that happens. | |
165 | */ | |
d15512f4 AK |
166 | static void |
167 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 168 | { |
cf4c6a2f AK |
169 | union entry_union eu; |
170 | eu.entry = e; | |
f9dadfa7 LT |
171 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
172 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
173 | } |
174 | ||
175 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
176 | { | |
177 | unsigned long flags; | |
178 | spin_lock_irqsave(&ioapic_lock, flags); | |
179 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
180 | spin_unlock_irqrestore(&ioapic_lock, flags); |
181 | } | |
182 | ||
183 | /* | |
184 | * When we mask an IO APIC routing entry, we need to write the low | |
185 | * word first, in order to set the mask bit before we change the | |
186 | * high bits! | |
187 | */ | |
188 | static void ioapic_mask_entry(int apic, int pin) | |
189 | { | |
190 | unsigned long flags; | |
191 | union entry_union eu = { .entry.mask = 1 }; | |
192 | ||
cf4c6a2f AK |
193 | spin_lock_irqsave(&ioapic_lock, flags); |
194 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
195 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
196 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
197 | } | |
198 | ||
1da177e4 LT |
199 | /* |
200 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
201 | * shared ISA-space IRQs, so we have to support them. We are super | |
202 | * fast in the common case, and fast for shared ISA-space IRQs. | |
203 | */ | |
204 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
205 | { | |
206 | static int first_free_entry = NR_IRQS; | |
207 | struct irq_pin_list *entry = irq_2_pin + irq; | |
208 | ||
209 | while (entry->next) | |
210 | entry = irq_2_pin + entry->next; | |
211 | ||
212 | if (entry->pin != -1) { | |
213 | entry->next = first_free_entry; | |
214 | entry = irq_2_pin + entry->next; | |
215 | if (++first_free_entry >= PIN_MAP_SIZE) | |
216 | panic("io_apic.c: whoops"); | |
217 | } | |
218 | entry->apic = apic; | |
219 | entry->pin = pin; | |
220 | } | |
221 | ||
222 | /* | |
223 | * Reroute an IRQ to a different pin. | |
224 | */ | |
225 | static void __init replace_pin_at_irq(unsigned int irq, | |
226 | int oldapic, int oldpin, | |
227 | int newapic, int newpin) | |
228 | { | |
229 | struct irq_pin_list *entry = irq_2_pin + irq; | |
230 | ||
231 | while (1) { | |
232 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
233 | entry->apic = newapic; | |
234 | entry->pin = newpin; | |
235 | } | |
236 | if (!entry->next) | |
237 | break; | |
238 | entry = irq_2_pin + entry->next; | |
239 | } | |
240 | } | |
241 | ||
242 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) | |
243 | { | |
244 | struct irq_pin_list *entry = irq_2_pin + irq; | |
245 | unsigned int pin, reg; | |
246 | ||
247 | for (;;) { | |
248 | pin = entry->pin; | |
249 | if (pin == -1) | |
250 | break; | |
251 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
252 | reg &= ~disable; | |
253 | reg |= enable; | |
254 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
255 | if (!entry->next) | |
256 | break; | |
257 | entry = irq_2_pin + entry->next; | |
258 | } | |
259 | } | |
260 | ||
261 | /* mask = 1 */ | |
262 | static void __mask_IO_APIC_irq (unsigned int irq) | |
263 | { | |
264 | __modify_IO_APIC_irq(irq, 0x00010000, 0); | |
265 | } | |
266 | ||
267 | /* mask = 0 */ | |
268 | static void __unmask_IO_APIC_irq (unsigned int irq) | |
269 | { | |
270 | __modify_IO_APIC_irq(irq, 0, 0x00010000); | |
271 | } | |
272 | ||
273 | /* mask = 1, trigger = 0 */ | |
274 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) | |
275 | { | |
276 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); | |
277 | } | |
278 | ||
279 | /* mask = 0, trigger = 1 */ | |
280 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) | |
281 | { | |
282 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); | |
283 | } | |
284 | ||
285 | static void mask_IO_APIC_irq (unsigned int irq) | |
286 | { | |
287 | unsigned long flags; | |
288 | ||
289 | spin_lock_irqsave(&ioapic_lock, flags); | |
290 | __mask_IO_APIC_irq(irq); | |
291 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
292 | } | |
293 | ||
294 | static void unmask_IO_APIC_irq (unsigned int irq) | |
295 | { | |
296 | unsigned long flags; | |
297 | ||
298 | spin_lock_irqsave(&ioapic_lock, flags); | |
299 | __unmask_IO_APIC_irq(irq); | |
300 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
301 | } | |
302 | ||
303 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
304 | { | |
305 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
306 | |
307 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
cf4c6a2f | 308 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
309 | if (entry.delivery_mode == dest_SMI) |
310 | return; | |
311 | ||
312 | /* | |
313 | * Disable it in the IO-APIC irq-routing table: | |
314 | */ | |
f9dadfa7 | 315 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
316 | } |
317 | ||
318 | static void clear_IO_APIC (void) | |
319 | { | |
320 | int apic, pin; | |
321 | ||
322 | for (apic = 0; apic < nr_ioapics; apic++) | |
323 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
324 | clear_IO_APIC_pin(apic, pin); | |
325 | } | |
326 | ||
54d5d424 | 327 | #ifdef CONFIG_SMP |
1da177e4 LT |
328 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
329 | { | |
330 | unsigned long flags; | |
331 | int pin; | |
332 | struct irq_pin_list *entry = irq_2_pin + irq; | |
333 | unsigned int apicid_value; | |
54d5d424 | 334 | cpumask_t tmp; |
1da177e4 | 335 | |
54d5d424 AR |
336 | cpus_and(tmp, cpumask, cpu_online_map); |
337 | if (cpus_empty(tmp)) | |
338 | tmp = TARGET_CPUS; | |
339 | ||
340 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
341 | ||
1da177e4 LT |
342 | apicid_value = cpu_mask_to_apicid(cpumask); |
343 | /* Prepare to do the io_apic_write */ | |
344 | apicid_value = apicid_value << 24; | |
345 | spin_lock_irqsave(&ioapic_lock, flags); | |
346 | for (;;) { | |
347 | pin = entry->pin; | |
348 | if (pin == -1) | |
349 | break; | |
350 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
351 | if (!entry->next) | |
352 | break; | |
353 | entry = irq_2_pin + entry->next; | |
354 | } | |
9f0a5ba5 | 355 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
356 | spin_unlock_irqrestore(&ioapic_lock, flags); |
357 | } | |
358 | ||
359 | #if defined(CONFIG_IRQBALANCE) | |
360 | # include <asm/processor.h> /* kernel_thread() */ | |
361 | # include <linux/kernel_stat.h> /* kstat */ | |
362 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 363 | # include <linux/timer.h> |
1da177e4 | 364 | |
1da177e4 | 365 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
366 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
367 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
368 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
369 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
370 | ||
371 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
372 | static int physical_balance __read_mostly; | |
373 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
374 | |
375 | static struct irq_cpu_info { | |
376 | unsigned long * last_irq; | |
377 | unsigned long * irq_delta; | |
378 | unsigned long irq; | |
379 | } irq_cpu_data[NR_CPUS]; | |
380 | ||
381 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
382 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) | |
383 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
384 | ||
385 | #define IDLE_ENOUGH(cpu,now) \ | |
386 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
387 | ||
388 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
389 | ||
d5a7430d | 390 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 391 | |
1b61b910 ZY |
392 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
393 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
394 | }; | |
1da177e4 | 395 | |
1b61b910 ZY |
396 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
397 | { | |
398 | balance_irq_affinity[irq] = mask; | |
399 | } | |
1da177e4 LT |
400 | |
401 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
402 | unsigned long now, int direction) | |
403 | { | |
404 | int search_idle = 1; | |
405 | int cpu = curr_cpu; | |
406 | ||
407 | goto inside; | |
408 | ||
409 | do { | |
410 | if (unlikely(cpu == curr_cpu)) | |
411 | search_idle = 0; | |
412 | inside: | |
413 | if (direction == 1) { | |
414 | cpu++; | |
415 | if (cpu >= NR_CPUS) | |
416 | cpu = 0; | |
417 | } else { | |
418 | cpu--; | |
419 | if (cpu == -1) | |
420 | cpu = NR_CPUS-1; | |
421 | } | |
422 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || | |
423 | (search_idle && !IDLE_ENOUGH(cpu,now))); | |
424 | ||
425 | return cpu; | |
426 | } | |
427 | ||
428 | static inline void balance_irq(int cpu, int irq) | |
429 | { | |
430 | unsigned long now = jiffies; | |
431 | cpumask_t allowed_mask; | |
432 | unsigned int new_cpu; | |
433 | ||
434 | if (irqbalance_disabled) | |
435 | return; | |
436 | ||
1b61b910 | 437 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 LT |
438 | new_cpu = move(cpu, allowed_mask, now, 1); |
439 | if (cpu != new_cpu) { | |
54d5d424 | 440 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
441 | } |
442 | } | |
443 | ||
444 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
445 | { | |
446 | int i, j; | |
edc2cbf4 | 447 | |
394e3902 AM |
448 | for_each_online_cpu(i) { |
449 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
450 | if (!irq_desc[j].action) |
451 | continue; | |
452 | /* Is it a significant load ? */ | |
453 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < | |
454 | useful_load_threshold) | |
455 | continue; | |
456 | balance_irq(i, j); | |
457 | } | |
458 | } | |
459 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
460 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
461 | return; | |
462 | } | |
463 | ||
464 | static void do_irq_balance(void) | |
465 | { | |
466 | int i, j; | |
467 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
468 | unsigned long move_this_load = 0; | |
469 | int max_loaded = 0, min_loaded = 0; | |
470 | int load; | |
471 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
472 | int selected_irq; | |
473 | int tmp_loaded, first_attempt = 1; | |
474 | unsigned long tmp_cpu_irq; | |
475 | unsigned long imbalance = 0; | |
476 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
477 | ||
c8912599 | 478 | for_each_possible_cpu(i) { |
1da177e4 LT |
479 | int package_index; |
480 | CPU_IRQ(i) = 0; | |
481 | if (!cpu_online(i)) | |
482 | continue; | |
483 | package_index = CPU_TO_PACKAGEINDEX(i); | |
484 | for (j = 0; j < NR_IRQS; j++) { | |
485 | unsigned long value_now, delta; | |
950f4427 TG |
486 | /* Is this an active IRQ or balancing disabled ? */ |
487 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 LT |
488 | continue; |
489 | if ( package_index == i ) | |
490 | IRQ_DELTA(package_index,j) = 0; | |
491 | /* Determine the total count per processor per IRQ */ | |
492 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
493 | ||
494 | /* Determine the activity per processor per IRQ */ | |
495 | delta = value_now - LAST_CPU_IRQ(i,j); | |
496 | ||
497 | /* Update last_cpu_irq[][] for the next time */ | |
498 | LAST_CPU_IRQ(i,j) = value_now; | |
499 | ||
500 | /* Ignore IRQs whose rate is less than the clock */ | |
501 | if (delta < useful_load_threshold) | |
502 | continue; | |
503 | /* update the load for the processor or package total */ | |
504 | IRQ_DELTA(package_index,j) += delta; | |
505 | ||
506 | /* Keep track of the higher numbered sibling as well */ | |
507 | if (i != package_index) | |
508 | CPU_IRQ(i) += delta; | |
509 | /* | |
510 | * We have sibling A and sibling B in the package | |
511 | * | |
512 | * cpu_irq[A] = load for cpu A + load for cpu B | |
513 | * cpu_irq[B] = load for cpu B | |
514 | */ | |
515 | CPU_IRQ(package_index) += delta; | |
516 | } | |
517 | } | |
518 | /* Find the least loaded processor package */ | |
394e3902 | 519 | for_each_online_cpu(i) { |
1da177e4 LT |
520 | if (i != CPU_TO_PACKAGEINDEX(i)) |
521 | continue; | |
522 | if (min_cpu_irq > CPU_IRQ(i)) { | |
523 | min_cpu_irq = CPU_IRQ(i); | |
524 | min_loaded = i; | |
525 | } | |
526 | } | |
527 | max_cpu_irq = ULONG_MAX; | |
528 | ||
529 | tryanothercpu: | |
530 | /* Look for heaviest loaded processor. | |
531 | * We may come back to get the next heaviest loaded processor. | |
532 | * Skip processors with trivial loads. | |
533 | */ | |
534 | tmp_cpu_irq = 0; | |
535 | tmp_loaded = -1; | |
394e3902 | 536 | for_each_online_cpu(i) { |
1da177e4 LT |
537 | if (i != CPU_TO_PACKAGEINDEX(i)) |
538 | continue; | |
539 | if (max_cpu_irq <= CPU_IRQ(i)) | |
540 | continue; | |
541 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
542 | tmp_cpu_irq = CPU_IRQ(i); | |
543 | tmp_loaded = i; | |
544 | } | |
545 | } | |
546 | ||
547 | if (tmp_loaded == -1) { | |
548 | /* In the case of small number of heavy interrupt sources, | |
549 | * loading some of the cpus too much. We use Ingo's original | |
550 | * approach to rotate them around. | |
551 | */ | |
552 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
553 | rotate_irqs_among_cpus(useful_load_threshold); | |
554 | return; | |
555 | } | |
556 | goto not_worth_the_effort; | |
557 | } | |
558 | ||
559 | first_attempt = 0; /* heaviest search */ | |
560 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
561 | max_loaded = tmp_loaded; /* processor */ | |
562 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
563 | ||
1da177e4 LT |
564 | /* if imbalance is less than approx 10% of max load, then |
565 | * observe diminishing returns action. - quit | |
566 | */ | |
edc2cbf4 | 567 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 568 | goto not_worth_the_effort; |
1da177e4 LT |
569 | |
570 | tryanotherirq: | |
571 | /* if we select an IRQ to move that can't go where we want, then | |
572 | * see if there is another one to try. | |
573 | */ | |
574 | move_this_load = 0; | |
575 | selected_irq = -1; | |
576 | for (j = 0; j < NR_IRQS; j++) { | |
577 | /* Is this an active IRQ? */ | |
578 | if (!irq_desc[j].action) | |
579 | continue; | |
580 | if (imbalance <= IRQ_DELTA(max_loaded,j)) | |
581 | continue; | |
582 | /* Try to find the IRQ that is closest to the imbalance | |
583 | * without going over. | |
584 | */ | |
585 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { | |
586 | move_this_load = IRQ_DELTA(max_loaded,j); | |
587 | selected_irq = j; | |
588 | } | |
589 | } | |
590 | if (selected_irq == -1) { | |
591 | goto tryanothercpu; | |
592 | } | |
593 | ||
594 | imbalance = move_this_load; | |
595 | ||
27b46d76 | 596 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
597 | * values in the one of the siblings cpu_irq[], |
598 | * to use the same code for physical and logical processors | |
599 | * as much as possible. | |
600 | * | |
601 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
602 | * sibling A and sibling B in the slot for the lowest numbered | |
603 | * sibling (A), _AND_ the load for sibling B in the slot for | |
604 | * the higher numbered sibling. | |
605 | * | |
606 | * We seek the least loaded sibling by making the comparison | |
607 | * (A+B)/2 vs B | |
608 | */ | |
609 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 610 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
611 | if (load > CPU_IRQ(j)) { |
612 | /* This won't change cpu_sibling_map[min_loaded] */ | |
613 | load = CPU_IRQ(j); | |
614 | min_loaded = j; | |
615 | } | |
616 | } | |
617 | ||
1b61b910 ZY |
618 | cpus_and(allowed_mask, |
619 | cpu_online_map, | |
620 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
621 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
622 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
623 | ||
624 | if (!cpus_empty(tmp)) { | |
1da177e4 | 625 | /* mark for change destination */ |
54d5d424 AR |
626 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
627 | ||
1da177e4 LT |
628 | /* Since we made a change, come back sooner to |
629 | * check for more variation. | |
630 | */ | |
631 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
632 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
633 | return; | |
634 | } | |
635 | goto tryanotherirq; | |
636 | ||
637 | not_worth_the_effort: | |
638 | /* | |
639 | * if we did not find an IRQ to move, then adjust the time interval | |
640 | * upward | |
641 | */ | |
642 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
643 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); | |
1da177e4 LT |
644 | return; |
645 | } | |
646 | ||
647 | static int balanced_irq(void *unused) | |
648 | { | |
649 | int i; | |
650 | unsigned long prev_balance_time = jiffies; | |
651 | long time_remaining = balanced_irq_interval; | |
652 | ||
1da177e4 LT |
653 | /* push everything to CPU 0 to give us a starting point. */ |
654 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 655 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 656 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
657 | } |
658 | ||
83144186 | 659 | set_freezable(); |
1da177e4 | 660 | for ( ; ; ) { |
52e6e630 | 661 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 662 | try_to_freeze(); |
1da177e4 LT |
663 | if (time_after(jiffies, |
664 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 665 | preempt_disable(); |
1da177e4 LT |
666 | do_irq_balance(); |
667 | prev_balance_time = jiffies; | |
668 | time_remaining = balanced_irq_interval; | |
f3705136 | 669 | preempt_enable(); |
1da177e4 LT |
670 | } |
671 | } | |
672 | return 0; | |
673 | } | |
674 | ||
675 | static int __init balanced_irq_init(void) | |
676 | { | |
677 | int i; | |
678 | struct cpuinfo_x86 *c; | |
679 | cpumask_t tmp; | |
680 | ||
681 | cpus_shift_right(tmp, cpu_online_map, 2); | |
682 | c = &boot_cpu_data; | |
683 | /* When not overwritten by the command line ask subarchitecture. */ | |
684 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
685 | irqbalance_disabled = NO_BALANCE_IRQ; | |
686 | if (irqbalance_disabled) | |
687 | return 0; | |
688 | ||
689 | /* disable irqbalance completely if there is only one processor online */ | |
690 | if (num_online_cpus() < 2) { | |
691 | irqbalance_disabled = 1; | |
692 | return 0; | |
693 | } | |
694 | /* | |
695 | * Enable physical balance only if more than 1 physical processor | |
696 | * is present | |
697 | */ | |
698 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
699 | physical_balance = 1; | |
700 | ||
394e3902 | 701 | for_each_online_cpu(i) { |
1da177e4 LT |
702 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
703 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
704 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { | |
705 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
706 | goto failed; | |
707 | } | |
708 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); | |
709 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); | |
710 | } | |
711 | ||
712 | printk(KERN_INFO "Starting balanced_irq\n"); | |
f26d6a2b | 713 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 714 | return 0; |
f26d6a2b | 715 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 716 | failed: |
c8912599 | 717 | for_each_possible_cpu(i) { |
4ae6673e | 718 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 719 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 720 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 721 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
722 | } |
723 | return 0; | |
724 | } | |
725 | ||
c2481cc4 | 726 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
727 | { |
728 | irqbalance_disabled = 1; | |
9b41046c | 729 | return 1; |
1da177e4 LT |
730 | } |
731 | ||
732 | __setup("noirqbalance", irqbalance_disable); | |
733 | ||
1da177e4 | 734 | late_initcall(balanced_irq_init); |
1da177e4 | 735 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 736 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
737 | |
738 | #ifndef CONFIG_SMP | |
75604d7f | 739 | void send_IPI_self(int vector) |
1da177e4 LT |
740 | { |
741 | unsigned int cfg; | |
742 | ||
743 | /* | |
744 | * Wait for idle. | |
745 | */ | |
746 | apic_wait_icr_idle(); | |
747 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
748 | /* | |
749 | * Send the IPI. The write to APIC_ICR fires this off. | |
750 | */ | |
751 | apic_write_around(APIC_ICR, cfg); | |
752 | } | |
753 | #endif /* !CONFIG_SMP */ | |
754 | ||
755 | ||
756 | /* | |
757 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
758 | * specific CPU-side IRQs. | |
759 | */ | |
760 | ||
761 | #define MAX_PIRQS 8 | |
762 | static int pirq_entries [MAX_PIRQS]; | |
763 | static int pirqs_enabled; | |
764 | int skip_ioapic_setup; | |
765 | ||
1da177e4 LT |
766 | static int __init ioapic_pirq_setup(char *str) |
767 | { | |
768 | int i, max; | |
769 | int ints[MAX_PIRQS+1]; | |
770 | ||
771 | get_options(str, ARRAY_SIZE(ints), ints); | |
772 | ||
773 | for (i = 0; i < MAX_PIRQS; i++) | |
774 | pirq_entries[i] = -1; | |
775 | ||
776 | pirqs_enabled = 1; | |
777 | apic_printk(APIC_VERBOSE, KERN_INFO | |
778 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
779 | max = MAX_PIRQS; | |
780 | if (ints[0] < MAX_PIRQS) | |
781 | max = ints[0]; | |
782 | ||
783 | for (i = 0; i < max; i++) { | |
784 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
785 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
786 | /* | |
787 | * PIRQs are mapped upside down, usually. | |
788 | */ | |
789 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
790 | } | |
791 | return 1; | |
792 | } | |
793 | ||
794 | __setup("pirq=", ioapic_pirq_setup); | |
795 | ||
796 | /* | |
797 | * Find the IRQ entry number of a certain pin. | |
798 | */ | |
799 | static int find_irq_entry(int apic, int pin, int type) | |
800 | { | |
801 | int i; | |
802 | ||
803 | for (i = 0; i < mp_irq_entries; i++) | |
804 | if (mp_irqs[i].mpc_irqtype == type && | |
805 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
806 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
807 | mp_irqs[i].mpc_dstirq == pin) | |
808 | return i; | |
809 | ||
810 | return -1; | |
811 | } | |
812 | ||
813 | /* | |
814 | * Find the pin to which IRQ[irq] (ISA) is connected | |
815 | */ | |
fcfd636a | 816 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
817 | { |
818 | int i; | |
819 | ||
820 | for (i = 0; i < mp_irq_entries; i++) { | |
821 | int lbus = mp_irqs[i].mpc_srcbus; | |
822 | ||
d27e2b8e | 823 | if (test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
824 | (mp_irqs[i].mpc_irqtype == type) && |
825 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
826 | ||
827 | return mp_irqs[i].mpc_dstirq; | |
828 | } | |
829 | return -1; | |
830 | } | |
831 | ||
fcfd636a EB |
832 | static int __init find_isa_irq_apic(int irq, int type) |
833 | { | |
834 | int i; | |
835 | ||
836 | for (i = 0; i < mp_irq_entries; i++) { | |
837 | int lbus = mp_irqs[i].mpc_srcbus; | |
838 | ||
73b2961b | 839 | if (test_bit(lbus, mp_bus_not_pci) && |
fcfd636a EB |
840 | (mp_irqs[i].mpc_irqtype == type) && |
841 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
842 | break; | |
843 | } | |
844 | if (i < mp_irq_entries) { | |
845 | int apic; | |
846 | for(apic = 0; apic < nr_ioapics; apic++) { | |
847 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
848 | return apic; | |
849 | } | |
850 | } | |
851 | ||
852 | return -1; | |
853 | } | |
854 | ||
1da177e4 LT |
855 | /* |
856 | * Find a specific PCI IRQ entry. | |
857 | * Not an __init, possibly needed by modules | |
858 | */ | |
859 | static int pin_2_irq(int idx, int apic, int pin); | |
860 | ||
861 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
862 | { | |
863 | int apic, i, best_guess = -1; | |
864 | ||
865 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
866 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
867 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
868 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
869 | return -1; | |
870 | } | |
871 | for (i = 0; i < mp_irq_entries; i++) { | |
872 | int lbus = mp_irqs[i].mpc_srcbus; | |
873 | ||
874 | for (apic = 0; apic < nr_ioapics; apic++) | |
875 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
876 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
877 | break; | |
878 | ||
47cab822 | 879 | if (!test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
880 | !mp_irqs[i].mpc_irqtype && |
881 | (bus == lbus) && | |
882 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
883 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
884 | ||
885 | if (!(apic || IO_APIC_IRQ(irq))) | |
886 | continue; | |
887 | ||
888 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
889 | return irq; | |
890 | /* | |
891 | * Use the first all-but-pin matching entry as a | |
892 | * best-guess fuzzy result for broken mptables. | |
893 | */ | |
894 | if (best_guess < 0) | |
895 | best_guess = irq; | |
896 | } | |
897 | } | |
898 | return best_guess; | |
899 | } | |
129f6946 | 900 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
901 | |
902 | /* | |
903 | * This function currently is only a helper for the i386 smp boot process where | |
904 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
905 | * so mask in all cases should simply be TARGET_CPUS | |
906 | */ | |
54d5d424 | 907 | #ifdef CONFIG_SMP |
1da177e4 LT |
908 | void __init setup_ioapic_dest(void) |
909 | { | |
910 | int pin, ioapic, irq, irq_entry; | |
911 | ||
912 | if (skip_ioapic_setup == 1) | |
913 | return; | |
914 | ||
915 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
916 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
917 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
918 | if (irq_entry == -1) | |
919 | continue; | |
920 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
921 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
922 | } | |
923 | ||
924 | } | |
925 | } | |
54d5d424 | 926 | #endif |
1da177e4 | 927 | |
c0a282c2 | 928 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
929 | /* |
930 | * EISA Edge/Level control register, ELCR | |
931 | */ | |
932 | static int EISA_ELCR(unsigned int irq) | |
933 | { | |
934 | if (irq < 16) { | |
935 | unsigned int port = 0x4d0 + (irq >> 3); | |
936 | return (inb(port) >> (irq & 7)) & 1; | |
937 | } | |
938 | apic_printk(APIC_VERBOSE, KERN_INFO | |
939 | "Broken MPtable reports ISA irq %d\n", irq); | |
940 | return 0; | |
941 | } | |
c0a282c2 | 942 | #endif |
1da177e4 | 943 | |
6728801d AS |
944 | /* ISA interrupts are always polarity zero edge triggered, |
945 | * when listed as conforming in the MP table. */ | |
946 | ||
947 | #define default_ISA_trigger(idx) (0) | |
948 | #define default_ISA_polarity(idx) (0) | |
949 | ||
1da177e4 LT |
950 | /* EISA interrupts are always polarity zero and can be edge or level |
951 | * trigger depending on the ELCR value. If an interrupt is listed as | |
952 | * EISA conforming in the MP table, that means its trigger type must | |
953 | * be read in from the ELCR */ | |
954 | ||
955 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
6728801d | 956 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
957 | |
958 | /* PCI interrupts are always polarity one level triggered, | |
959 | * when listed as conforming in the MP table. */ | |
960 | ||
961 | #define default_PCI_trigger(idx) (1) | |
962 | #define default_PCI_polarity(idx) (1) | |
963 | ||
964 | /* MCA interrupts are always polarity zero level triggered, | |
965 | * when listed as conforming in the MP table. */ | |
966 | ||
967 | #define default_MCA_trigger(idx) (1) | |
6728801d | 968 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 969 | |
61fd47e0 | 970 | static int MPBIOS_polarity(int idx) |
1da177e4 LT |
971 | { |
972 | int bus = mp_irqs[idx].mpc_srcbus; | |
973 | int polarity; | |
974 | ||
975 | /* | |
976 | * Determine IRQ line polarity (high active or low active): | |
977 | */ | |
978 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
979 | { | |
980 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
981 | { | |
6728801d AS |
982 | polarity = test_bit(bus, mp_bus_not_pci)? |
983 | default_ISA_polarity(idx): | |
984 | default_PCI_polarity(idx); | |
1da177e4 LT |
985 | break; |
986 | } | |
987 | case 1: /* high active */ | |
988 | { | |
989 | polarity = 0; | |
990 | break; | |
991 | } | |
992 | case 2: /* reserved */ | |
993 | { | |
994 | printk(KERN_WARNING "broken BIOS!!\n"); | |
995 | polarity = 1; | |
996 | break; | |
997 | } | |
998 | case 3: /* low active */ | |
999 | { | |
1000 | polarity = 1; | |
1001 | break; | |
1002 | } | |
1003 | default: /* invalid */ | |
1004 | { | |
1005 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1006 | polarity = 1; | |
1007 | break; | |
1008 | } | |
1009 | } | |
1010 | return polarity; | |
1011 | } | |
1012 | ||
1013 | static int MPBIOS_trigger(int idx) | |
1014 | { | |
1015 | int bus = mp_irqs[idx].mpc_srcbus; | |
1016 | int trigger; | |
1017 | ||
1018 | /* | |
1019 | * Determine IRQ trigger mode (edge or level sensitive): | |
1020 | */ | |
1021 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
1022 | { | |
1023 | case 0: /* conforms, ie. bus-type dependent */ | |
1024 | { | |
9c0076cb AS |
1025 | trigger = test_bit(bus, mp_bus_not_pci)? |
1026 | default_ISA_trigger(idx): | |
1027 | default_PCI_trigger(idx); | |
c0a282c2 | 1028 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1029 | switch (mp_bus_id_to_type[bus]) |
1030 | { | |
1031 | case MP_BUS_ISA: /* ISA pin */ | |
1032 | { | |
9c0076cb | 1033 | /* set before the switch */ |
1da177e4 LT |
1034 | break; |
1035 | } | |
1036 | case MP_BUS_EISA: /* EISA pin */ | |
1037 | { | |
1038 | trigger = default_EISA_trigger(idx); | |
1039 | break; | |
1040 | } | |
1041 | case MP_BUS_PCI: /* PCI pin */ | |
1042 | { | |
9c0076cb | 1043 | /* set before the switch */ |
1da177e4 LT |
1044 | break; |
1045 | } | |
1046 | case MP_BUS_MCA: /* MCA pin */ | |
1047 | { | |
1048 | trigger = default_MCA_trigger(idx); | |
1049 | break; | |
1050 | } | |
1da177e4 LT |
1051 | default: |
1052 | { | |
1053 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1054 | trigger = 1; | |
1055 | break; | |
1056 | } | |
1057 | } | |
c0a282c2 | 1058 | #endif |
1da177e4 LT |
1059 | break; |
1060 | } | |
1061 | case 1: /* edge */ | |
1062 | { | |
1063 | trigger = 0; | |
1064 | break; | |
1065 | } | |
1066 | case 2: /* reserved */ | |
1067 | { | |
1068 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1069 | trigger = 1; | |
1070 | break; | |
1071 | } | |
1072 | case 3: /* level */ | |
1073 | { | |
1074 | trigger = 1; | |
1075 | break; | |
1076 | } | |
1077 | default: /* invalid */ | |
1078 | { | |
1079 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1080 | trigger = 0; | |
1081 | break; | |
1082 | } | |
1083 | } | |
1084 | return trigger; | |
1085 | } | |
1086 | ||
1087 | static inline int irq_polarity(int idx) | |
1088 | { | |
1089 | return MPBIOS_polarity(idx); | |
1090 | } | |
1091 | ||
1092 | static inline int irq_trigger(int idx) | |
1093 | { | |
1094 | return MPBIOS_trigger(idx); | |
1095 | } | |
1096 | ||
1097 | static int pin_2_irq(int idx, int apic, int pin) | |
1098 | { | |
1099 | int irq, i; | |
1100 | int bus = mp_irqs[idx].mpc_srcbus; | |
1101 | ||
1102 | /* | |
1103 | * Debugging check, we are in big trouble if this message pops up! | |
1104 | */ | |
1105 | if (mp_irqs[idx].mpc_dstirq != pin) | |
1106 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
1107 | ||
643befed AS |
1108 | if (test_bit(bus, mp_bus_not_pci)) |
1109 | irq = mp_irqs[idx].mpc_srcbusirq; | |
1110 | else { | |
1111 | /* | |
1112 | * PCI IRQs are mapped in order | |
1113 | */ | |
1114 | i = irq = 0; | |
1115 | while (i < apic) | |
1116 | irq += nr_ioapic_registers[i++]; | |
1117 | irq += pin; | |
1da177e4 | 1118 | |
643befed AS |
1119 | /* |
1120 | * For MPS mode, so far only needed by ES7000 platform | |
1121 | */ | |
1122 | if (ioapic_renumber_irq) | |
1123 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1124 | } |
1125 | ||
1126 | /* | |
1127 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1128 | */ | |
1129 | if ((pin >= 16) && (pin <= 23)) { | |
1130 | if (pirq_entries[pin-16] != -1) { | |
1131 | if (!pirq_entries[pin-16]) { | |
1132 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1133 | "disabling PIRQ%d\n", pin-16); | |
1134 | } else { | |
1135 | irq = pirq_entries[pin-16]; | |
1136 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1137 | "using PIRQ%d -> IRQ %d\n", | |
1138 | pin-16, irq); | |
1139 | } | |
1140 | } | |
1141 | } | |
1142 | return irq; | |
1143 | } | |
1144 | ||
1145 | static inline int IO_APIC_irq_trigger(int irq) | |
1146 | { | |
1147 | int apic, idx, pin; | |
1148 | ||
1149 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1150 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1151 | idx = find_irq_entry(apic,pin,mp_INT); | |
1152 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
1153 | return irq_trigger(idx); | |
1154 | } | |
1155 | } | |
1156 | /* | |
1157 | * nonexistent IRQs are edge default | |
1158 | */ | |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
7e95b593 | 1163 | static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1164 | |
ace80ab7 | 1165 | static int __assign_irq_vector(int irq) |
1da177e4 | 1166 | { |
8339f000 | 1167 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dbeb2be2 | 1168 | int vector, offset; |
1da177e4 | 1169 | |
ace80ab7 | 1170 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1171 | |
b940d22d EB |
1172 | if (irq_vector[irq] > 0) |
1173 | return irq_vector[irq]; | |
ace80ab7 | 1174 | |
0a1ad60d | 1175 | vector = current_vector; |
8339f000 EB |
1176 | offset = current_offset; |
1177 | next: | |
1178 | vector += 8; | |
1179 | if (vector >= FIRST_SYSTEM_VECTOR) { | |
1180 | offset = (offset + 1) % 8; | |
1181 | vector = FIRST_DEVICE_VECTOR + offset; | |
1182 | } | |
1183 | if (vector == current_vector) | |
1184 | return -ENOSPC; | |
dbeb2be2 | 1185 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1186 | goto next; |
8339f000 EB |
1187 | |
1188 | current_vector = vector; | |
1189 | current_offset = offset; | |
b940d22d | 1190 | irq_vector[irq] = vector; |
ace80ab7 EB |
1191 | |
1192 | return vector; | |
1193 | } | |
0a1ad60d | 1194 | |
ace80ab7 EB |
1195 | static int assign_irq_vector(int irq) |
1196 | { | |
1197 | unsigned long flags; | |
1198 | int vector; | |
1199 | ||
1200 | spin_lock_irqsave(&vector_lock, flags); | |
1201 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1202 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1203 | |
0a1ad60d | 1204 | return vector; |
1da177e4 | 1205 | } |
f5b9ed7a | 1206 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1207 | |
1208 | #define IOAPIC_AUTO -1 | |
1209 | #define IOAPIC_EDGE 0 | |
1210 | #define IOAPIC_LEVEL 1 | |
1211 | ||
d1bef4ed | 1212 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1213 | { |
6ebcc00e | 1214 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1215 | trigger == IOAPIC_LEVEL) { |
1216 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1217 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1218 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1219 | } else { |
1220 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1221 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1222 | handle_edge_irq, "edge"); | |
cc75b92d | 1223 | } |
ace80ab7 | 1224 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1225 | } |
1226 | ||
1227 | static void __init setup_IO_APIC_irqs(void) | |
1228 | { | |
1229 | struct IO_APIC_route_entry entry; | |
1230 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1231 | |
1232 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1233 | ||
1234 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1235 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1236 | ||
1237 | /* | |
1238 | * add it to the IO-APIC irq-routing table: | |
1239 | */ | |
1240 | memset(&entry,0,sizeof(entry)); | |
1241 | ||
1242 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1243 | entry.dest_mode = INT_DEST_MODE; | |
1244 | entry.mask = 0; /* enable IRQ */ | |
1245 | entry.dest.logical.logical_dest = | |
1246 | cpu_mask_to_apicid(TARGET_CPUS); | |
1247 | ||
1248 | idx = find_irq_entry(apic,pin,mp_INT); | |
1249 | if (idx == -1) { | |
1250 | if (first_notcon) { | |
1251 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1252 | " IO-APIC (apicid-pin) %d-%d", | |
1253 | mp_ioapics[apic].mpc_apicid, | |
1254 | pin); | |
1255 | first_notcon = 0; | |
1256 | } else | |
1257 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
1258 | mp_ioapics[apic].mpc_apicid, pin); | |
1259 | continue; | |
1260 | } | |
1261 | ||
20d225b9 YL |
1262 | if (!first_notcon) { |
1263 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1264 | first_notcon = 1; | |
1265 | } | |
1266 | ||
1da177e4 LT |
1267 | entry.trigger = irq_trigger(idx); |
1268 | entry.polarity = irq_polarity(idx); | |
1269 | ||
1270 | if (irq_trigger(idx)) { | |
1271 | entry.trigger = 1; | |
1272 | entry.mask = 1; | |
1273 | } | |
1274 | ||
1275 | irq = pin_2_irq(idx, apic, pin); | |
1276 | /* | |
1277 | * skip adding the timer int on secondary nodes, which causes | |
1278 | * a small but painful rift in the time-space continuum | |
1279 | */ | |
1280 | if (multi_timer_check(apic, irq)) | |
1281 | continue; | |
1282 | else | |
1283 | add_pin_to_irq(irq, apic, pin); | |
1284 | ||
1285 | if (!apic && !IO_APIC_IRQ(irq)) | |
1286 | continue; | |
1287 | ||
1288 | if (IO_APIC_IRQ(irq)) { | |
1289 | vector = assign_irq_vector(irq); | |
1290 | entry.vector = vector; | |
1291 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
1292 | ||
1293 | if (!apic && (irq < 16)) | |
1294 | disable_8259A_irq(irq); | |
1295 | } | |
a2249cba | 1296 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1297 | } |
1298 | } | |
1299 | ||
1300 | if (!first_notcon) | |
1301 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * Set up the 8259A-master output pin: | |
1306 | */ | |
fcfd636a | 1307 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
1308 | { |
1309 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
1310 | |
1311 | memset(&entry,0,sizeof(entry)); | |
1312 | ||
1313 | disable_8259A_irq(0); | |
1314 | ||
1315 | /* mask LVT0 */ | |
1316 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1317 | ||
1318 | /* | |
1319 | * We use logical delivery to get the timer IRQ | |
1320 | * to the first CPU. | |
1321 | */ | |
1322 | entry.dest_mode = INT_DEST_MODE; | |
1323 | entry.mask = 0; /* unmask IRQ now */ | |
1324 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1325 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1326 | entry.polarity = 0; | |
1327 | entry.trigger = 0; | |
1328 | entry.vector = vector; | |
1329 | ||
1330 | /* | |
1331 | * The timer IRQ doesn't have to know that behind the | |
1332 | * scene we have a 8259A-master in AEOI mode ... | |
1333 | */ | |
f5b9ed7a IM |
1334 | irq_desc[0].chip = &ioapic_chip; |
1335 | set_irq_handler(0, handle_edge_irq); | |
1da177e4 LT |
1336 | |
1337 | /* | |
1338 | * Add it to the IO-APIC irq-routing table: | |
1339 | */ | |
cf4c6a2f | 1340 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1341 | |
1342 | enable_8259A_irq(0); | |
1343 | } | |
1344 | ||
1da177e4 LT |
1345 | void __init print_IO_APIC(void) |
1346 | { | |
1347 | int apic, i; | |
1348 | union IO_APIC_reg_00 reg_00; | |
1349 | union IO_APIC_reg_01 reg_01; | |
1350 | union IO_APIC_reg_02 reg_02; | |
1351 | union IO_APIC_reg_03 reg_03; | |
1352 | unsigned long flags; | |
1353 | ||
1354 | if (apic_verbosity == APIC_QUIET) | |
1355 | return; | |
1356 | ||
1357 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1358 | for (i = 0; i < nr_ioapics; i++) | |
1359 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
1360 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
1361 | ||
1362 | /* | |
1363 | * We are a bit conservative about what we expect. We have to | |
1364 | * know about every hardware change ASAP. | |
1365 | */ | |
1366 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1367 | ||
1368 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1369 | ||
1370 | spin_lock_irqsave(&ioapic_lock, flags); | |
1371 | reg_00.raw = io_apic_read(apic, 0); | |
1372 | reg_01.raw = io_apic_read(apic, 1); | |
1373 | if (reg_01.bits.version >= 0x10) | |
1374 | reg_02.raw = io_apic_read(apic, 2); | |
1375 | if (reg_01.bits.version >= 0x20) | |
1376 | reg_03.raw = io_apic_read(apic, 3); | |
1377 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1378 | ||
1379 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
1380 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
1381 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1382 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1383 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1384 | |
1385 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1386 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1387 | |
1388 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1389 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1390 | |
1391 | /* | |
1392 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1393 | * but the value of reg_02 is read as the previous read register | |
1394 | * value, so ignore it if reg_02 == reg_01. | |
1395 | */ | |
1396 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1397 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1398 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1399 | } |
1400 | ||
1401 | /* | |
1402 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1403 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1404 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1405 | */ | |
1406 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1407 | reg_03.raw != reg_01.raw) { | |
1408 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1409 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1410 | } |
1411 | ||
1412 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1413 | ||
1414 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1415 | " Stat Dest Deli Vect: \n"); | |
1416 | ||
1417 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1418 | struct IO_APIC_route_entry entry; | |
1419 | ||
cf4c6a2f | 1420 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1421 | |
1422 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1423 | i, | |
1424 | entry.dest.logical.logical_dest, | |
1425 | entry.dest.physical.physical_dest | |
1426 | ); | |
1427 | ||
1428 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1429 | entry.mask, | |
1430 | entry.trigger, | |
1431 | entry.irr, | |
1432 | entry.polarity, | |
1433 | entry.delivery_status, | |
1434 | entry.dest_mode, | |
1435 | entry.delivery_mode, | |
1436 | entry.vector | |
1437 | ); | |
1438 | } | |
1439 | } | |
1da177e4 LT |
1440 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1441 | for (i = 0; i < NR_IRQS; i++) { | |
1442 | struct irq_pin_list *entry = irq_2_pin + i; | |
1443 | if (entry->pin < 0) | |
1444 | continue; | |
ace80ab7 | 1445 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1446 | for (;;) { |
1447 | printk("-> %d:%d", entry->apic, entry->pin); | |
1448 | if (!entry->next) | |
1449 | break; | |
1450 | entry = irq_2_pin + entry->next; | |
1451 | } | |
1452 | printk("\n"); | |
1453 | } | |
1454 | ||
1455 | printk(KERN_INFO ".................................... done.\n"); | |
1456 | ||
1457 | return; | |
1458 | } | |
1459 | ||
1460 | #if 0 | |
1461 | ||
1462 | static void print_APIC_bitfield (int base) | |
1463 | { | |
1464 | unsigned int v; | |
1465 | int i, j; | |
1466 | ||
1467 | if (apic_verbosity == APIC_QUIET) | |
1468 | return; | |
1469 | ||
1470 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1471 | for (i = 0; i < 8; i++) { | |
1472 | v = apic_read(base + i*0x10); | |
1473 | for (j = 0; j < 32; j++) { | |
1474 | if (v & (1<<j)) | |
1475 | printk("1"); | |
1476 | else | |
1477 | printk("0"); | |
1478 | } | |
1479 | printk("\n"); | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | void /*__init*/ print_local_APIC(void * dummy) | |
1484 | { | |
1485 | unsigned int v, ver, maxlvt; | |
1486 | ||
1487 | if (apic_verbosity == APIC_QUIET) | |
1488 | return; | |
1489 | ||
1490 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1491 | smp_processor_id(), hard_smp_processor_id()); | |
05f2d12c JS |
1492 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
1493 | GET_APIC_ID(read_apic_id())); | |
1da177e4 LT |
1494 | v = apic_read(APIC_LVR); |
1495 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1496 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1497 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1498 | |
1499 | v = apic_read(APIC_TASKPRI); | |
1500 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1501 | ||
1502 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1503 | v = apic_read(APIC_ARBPRI); | |
1504 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1505 | v & APIC_ARBPRI_MASK); | |
1506 | v = apic_read(APIC_PROCPRI); | |
1507 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1508 | } | |
1509 | ||
1510 | v = apic_read(APIC_EOI); | |
1511 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1512 | v = apic_read(APIC_RRR); | |
1513 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1514 | v = apic_read(APIC_LDR); | |
1515 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1516 | v = apic_read(APIC_DFR); | |
1517 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1518 | v = apic_read(APIC_SPIV); | |
1519 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1520 | ||
1521 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1522 | print_APIC_bitfield(APIC_ISR); | |
1523 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1524 | print_APIC_bitfield(APIC_TMR); | |
1525 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1526 | print_APIC_bitfield(APIC_IRR); | |
1527 | ||
1528 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1529 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1530 | apic_write(APIC_ESR, 0); | |
1531 | v = apic_read(APIC_ESR); | |
1532 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1533 | } | |
1534 | ||
1535 | v = apic_read(APIC_ICR); | |
1536 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1537 | v = apic_read(APIC_ICR2); | |
1538 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1539 | ||
1540 | v = apic_read(APIC_LVTT); | |
1541 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1542 | ||
1543 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1544 | v = apic_read(APIC_LVTPC); | |
1545 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1546 | } | |
1547 | v = apic_read(APIC_LVT0); | |
1548 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1549 | v = apic_read(APIC_LVT1); | |
1550 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1551 | ||
1552 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1553 | v = apic_read(APIC_LVTERR); | |
1554 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1555 | } | |
1556 | ||
1557 | v = apic_read(APIC_TMICT); | |
1558 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1559 | v = apic_read(APIC_TMCCT); | |
1560 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1561 | v = apic_read(APIC_TDCR); | |
1562 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1563 | printk("\n"); | |
1564 | } | |
1565 | ||
1566 | void print_all_local_APICs (void) | |
1567 | { | |
1568 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1569 | } | |
1570 | ||
1571 | void /*__init*/ print_PIC(void) | |
1572 | { | |
1da177e4 LT |
1573 | unsigned int v; |
1574 | unsigned long flags; | |
1575 | ||
1576 | if (apic_verbosity == APIC_QUIET) | |
1577 | return; | |
1578 | ||
1579 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1580 | ||
1581 | spin_lock_irqsave(&i8259A_lock, flags); | |
1582 | ||
1583 | v = inb(0xa1) << 8 | inb(0x21); | |
1584 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1585 | ||
1586 | v = inb(0xa0) << 8 | inb(0x20); | |
1587 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1588 | ||
1589 | outb(0x0b,0xa0); | |
1590 | outb(0x0b,0x20); | |
1591 | v = inb(0xa0) << 8 | inb(0x20); | |
1592 | outb(0x0a,0xa0); | |
1593 | outb(0x0a,0x20); | |
1594 | ||
1595 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1596 | ||
1597 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1598 | ||
1599 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1600 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1601 | } | |
1602 | ||
1603 | #endif /* 0 */ | |
1604 | ||
1605 | static void __init enable_IO_APIC(void) | |
1606 | { | |
1607 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1608 | int i8259_apic, i8259_pin; |
1609 | int i, apic; | |
1da177e4 LT |
1610 | unsigned long flags; |
1611 | ||
1612 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1613 | irq_2_pin[i].pin = -1; | |
1614 | irq_2_pin[i].next = 0; | |
1615 | } | |
1616 | if (!pirqs_enabled) | |
1617 | for (i = 0; i < MAX_PIRQS; i++) | |
1618 | pirq_entries[i] = -1; | |
1619 | ||
1620 | /* | |
1621 | * The number of IO-APIC IRQ registers (== #pins): | |
1622 | */ | |
fcfd636a | 1623 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1624 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1625 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1626 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1627 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1628 | } | |
1629 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1630 | int pin; | |
1631 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1632 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1633 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1634 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1635 | |
1636 | ||
1637 | /* If the interrupt line is enabled and in ExtInt mode | |
1638 | * I have found the pin where the i8259 is connected. | |
1639 | */ | |
1640 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1641 | ioapic_i8259.apic = apic; | |
1642 | ioapic_i8259.pin = pin; | |
1643 | goto found_i8259; | |
1644 | } | |
1645 | } | |
1646 | } | |
1647 | found_i8259: | |
1648 | /* Look to see what if the MP table has reported the ExtINT */ | |
1649 | /* If we could not find the appropriate pin by looking at the ioapic | |
1650 | * the i8259 probably is not connected the ioapic but give the | |
1651 | * mptable a chance anyway. | |
1652 | */ | |
1653 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1654 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1655 | /* Trust the MP table if nothing is setup in the hardware */ | |
1656 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1657 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1658 | ioapic_i8259.pin = i8259_pin; | |
1659 | ioapic_i8259.apic = i8259_apic; | |
1660 | } | |
1661 | /* Complain if the MP table and the hardware disagree */ | |
1662 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1663 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1664 | { | |
1665 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1666 | } |
1667 | ||
1668 | /* | |
1669 | * Do not trust the IO-APIC being empty at bootup | |
1670 | */ | |
1671 | clear_IO_APIC(); | |
1672 | } | |
1673 | ||
1674 | /* | |
1675 | * Not an __init, needed by the reboot code | |
1676 | */ | |
1677 | void disable_IO_APIC(void) | |
1678 | { | |
1679 | /* | |
1680 | * Clear the IO-APIC before rebooting: | |
1681 | */ | |
1682 | clear_IO_APIC(); | |
1683 | ||
650927ef | 1684 | /* |
0b968d23 | 1685 | * If the i8259 is routed through an IOAPIC |
650927ef | 1686 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1687 | * so legacy interrupts can be delivered. |
650927ef | 1688 | */ |
fcfd636a | 1689 | if (ioapic_i8259.pin != -1) { |
650927ef | 1690 | struct IO_APIC_route_entry entry; |
650927ef EB |
1691 | |
1692 | memset(&entry, 0, sizeof(entry)); | |
1693 | entry.mask = 0; /* Enabled */ | |
1694 | entry.trigger = 0; /* Edge */ | |
1695 | entry.irr = 0; | |
1696 | entry.polarity = 0; /* High */ | |
1697 | entry.delivery_status = 0; | |
1698 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1699 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1700 | entry.vector = 0; |
76865c3f | 1701 | entry.dest.physical.physical_dest = |
05f2d12c | 1702 | GET_APIC_ID(read_apic_id()); |
650927ef EB |
1703 | |
1704 | /* | |
1705 | * Add it to the IO-APIC irq-routing table: | |
1706 | */ | |
cf4c6a2f | 1707 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1708 | } |
fcfd636a | 1709 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1710 | } |
1711 | ||
1712 | /* | |
1713 | * function to set the IO-APIC physical IDs based on the | |
1714 | * values stored in the MPC table. | |
1715 | * | |
1716 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1717 | */ | |
1718 | ||
1719 | #ifndef CONFIG_X86_NUMAQ | |
1720 | static void __init setup_ioapic_ids_from_mpc(void) | |
1721 | { | |
1722 | union IO_APIC_reg_00 reg_00; | |
1723 | physid_mask_t phys_id_present_map; | |
1724 | int apic; | |
1725 | int i; | |
1726 | unsigned char old_id; | |
1727 | unsigned long flags; | |
1728 | ||
ca05fea6 NP |
1729 | /* |
1730 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1731 | * no meaning without the serial APIC bus. | |
1732 | */ | |
7c5c1e42 SL |
1733 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1734 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1735 | return; |
1da177e4 LT |
1736 | /* |
1737 | * This is broken; anything with a real cpu count has to | |
1738 | * circumvent this idiocy regardless. | |
1739 | */ | |
1740 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1741 | ||
1742 | /* | |
1743 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1744 | */ | |
1745 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1746 | ||
1747 | /* Read the register 0 value */ | |
1748 | spin_lock_irqsave(&ioapic_lock, flags); | |
1749 | reg_00.raw = io_apic_read(apic, 0); | |
1750 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1751 | ||
1752 | old_id = mp_ioapics[apic].mpc_apicid; | |
1753 | ||
1754 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { | |
1755 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", | |
1756 | apic, mp_ioapics[apic].mpc_apicid); | |
1757 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1758 | reg_00.bits.ID); | |
1759 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; | |
1760 | } | |
1761 | ||
1da177e4 LT |
1762 | /* |
1763 | * Sanity check, is the ID really free? Every APIC in a | |
1764 | * system must have a unique ID or we get lots of nice | |
1765 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1766 | */ | |
1767 | if (check_apicid_used(phys_id_present_map, | |
1768 | mp_ioapics[apic].mpc_apicid)) { | |
1769 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", | |
1770 | apic, mp_ioapics[apic].mpc_apicid); | |
1771 | for (i = 0; i < get_physical_broadcast(); i++) | |
1772 | if (!physid_isset(i, phys_id_present_map)) | |
1773 | break; | |
1774 | if (i >= get_physical_broadcast()) | |
1775 | panic("Max APIC ID exceeded!\n"); | |
1776 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1777 | i); | |
1778 | physid_set(i, phys_id_present_map); | |
1779 | mp_ioapics[apic].mpc_apicid = i; | |
1780 | } else { | |
1781 | physid_mask_t tmp; | |
1782 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); | |
1783 | apic_printk(APIC_VERBOSE, "Setting %d in the " | |
1784 | "phys_id_present_map\n", | |
1785 | mp_ioapics[apic].mpc_apicid); | |
1786 | physids_or(phys_id_present_map, phys_id_present_map, tmp); | |
1787 | } | |
1788 | ||
1789 | ||
1790 | /* | |
1791 | * We need to adjust the IRQ routing table | |
1792 | * if the ID changed. | |
1793 | */ | |
1794 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1795 | for (i = 0; i < mp_irq_entries; i++) | |
1796 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1797 | mp_irqs[i].mpc_dstapic | |
1798 | = mp_ioapics[apic].mpc_apicid; | |
1799 | ||
1800 | /* | |
1801 | * Read the right value from the MPC table and | |
1802 | * write it into the ID register. | |
1803 | */ | |
1804 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1805 | "...changing IO-APIC physical APIC ID to %d ...", | |
1806 | mp_ioapics[apic].mpc_apicid); | |
1807 | ||
1808 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1809 | spin_lock_irqsave(&ioapic_lock, flags); | |
1810 | io_apic_write(apic, 0, reg_00.raw); | |
1811 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1812 | ||
1813 | /* | |
1814 | * Sanity check | |
1815 | */ | |
1816 | spin_lock_irqsave(&ioapic_lock, flags); | |
1817 | reg_00.raw = io_apic_read(apic, 0); | |
1818 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1819 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1820 | printk("could not set ID!\n"); | |
1821 | else | |
1822 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1823 | } | |
1824 | } | |
1825 | #else | |
1826 | static void __init setup_ioapic_ids_from_mpc(void) { } | |
1827 | #endif | |
1828 | ||
7ce0bcfd | 1829 | int no_timer_check __initdata; |
8542b200 ZA |
1830 | |
1831 | static int __init notimercheck(char *s) | |
1832 | { | |
1833 | no_timer_check = 1; | |
1834 | return 1; | |
1835 | } | |
1836 | __setup("no_timer_check", notimercheck); | |
1837 | ||
1da177e4 LT |
1838 | /* |
1839 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1840 | * about the timer IRQ. We do the following to work around the situation: | |
1841 | * | |
1842 | * - timer IRQ defaults to IO-APIC IRQ | |
1843 | * - if this function detects that timer IRQs are defunct, then we fall | |
1844 | * back to ISA timer IRQs | |
1845 | */ | |
f0a7a5c9 | 1846 | static int __init timer_irq_works(void) |
1da177e4 LT |
1847 | { |
1848 | unsigned long t1 = jiffies; | |
4aae0702 | 1849 | unsigned long flags; |
1da177e4 | 1850 | |
8542b200 ZA |
1851 | if (no_timer_check) |
1852 | return 1; | |
1853 | ||
4aae0702 | 1854 | local_save_flags(flags); |
1da177e4 LT |
1855 | local_irq_enable(); |
1856 | /* Let ten ticks pass... */ | |
1857 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1858 | local_irq_restore(flags); |
1da177e4 LT |
1859 | |
1860 | /* | |
1861 | * Expect a few ticks at least, to be sure some possible | |
1862 | * glue logic does not lock up after one or two first | |
1863 | * ticks in a non-ExtINT mode. Also the local APIC | |
1864 | * might have cached one ExtINT interrupt. Finally, at | |
1865 | * least one tick may be lost due to delays. | |
1866 | */ | |
1d16b53e | 1867 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1868 | return 1; |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
1873 | /* | |
1874 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1875 | * number of pending IRQ events unhandled. These cases are very rare, | |
1876 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1877 | * better to do it this way as thus we do not have to be aware of | |
1878 | * 'pending' interrupts in the IRQ path, except at this point. | |
1879 | */ | |
1880 | /* | |
1881 | * Edge triggered needs to resend any interrupt | |
1882 | * that was delayed but this is now handled in the device | |
1883 | * independent code. | |
1884 | */ | |
1885 | ||
1886 | /* | |
f5b9ed7a IM |
1887 | * Startup quirk: |
1888 | * | |
1da177e4 LT |
1889 | * Starting up a edge-triggered IO-APIC interrupt is |
1890 | * nasty - we need to make sure that we get the edge. | |
1891 | * If it is already asserted for some reason, we need | |
1892 | * return 1 to indicate that is was pending. | |
1893 | * | |
1894 | * This is not complete - we should be able to fake | |
1895 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1896 | * |
1897 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1898 | */ |
f5b9ed7a | 1899 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1900 | { |
1901 | int was_pending = 0; | |
1902 | unsigned long flags; | |
1903 | ||
1904 | spin_lock_irqsave(&ioapic_lock, flags); | |
1905 | if (irq < 16) { | |
1906 | disable_8259A_irq(irq); | |
1907 | if (i8259A_irq_pending(irq)) | |
1908 | was_pending = 1; | |
1909 | } | |
1910 | __unmask_IO_APIC_irq(irq); | |
1911 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1912 | ||
1913 | return was_pending; | |
1914 | } | |
1915 | ||
f5b9ed7a | 1916 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1917 | { |
ace80ab7 | 1918 | move_native_irq(irq); |
1da177e4 LT |
1919 | ack_APIC_irq(); |
1920 | } | |
1921 | ||
f5b9ed7a | 1922 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1923 | { |
1924 | unsigned long v; | |
1925 | int i; | |
1926 | ||
ace80ab7 | 1927 | move_native_irq(irq); |
1da177e4 LT |
1928 | /* |
1929 | * It appears there is an erratum which affects at least version 0x11 | |
1930 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1931 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1932 | * erroneously delivered as edge-triggered one but the respective IRR | |
1933 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1934 | * message but it will never arrive and further interrupts are blocked | |
1935 | * from the source. The exact reason is so far unknown, but the | |
1936 | * phenomenon was observed when two consecutive interrupt requests | |
1937 | * from a given source get delivered to the same CPU and the source is | |
1938 | * temporarily disabled in between. | |
1939 | * | |
1940 | * A workaround is to simulate an EOI message manually. We achieve it | |
1941 | * by setting the trigger mode to edge and then to level when the edge | |
1942 | * trigger mode gets detected in the TMR of a local APIC for a | |
1943 | * level-triggered interrupt. We mask the source for the time of the | |
1944 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1945 | * The idea is from Manfred Spraul. --macro | |
1946 | */ | |
b940d22d | 1947 | i = irq_vector[irq]; |
1da177e4 LT |
1948 | |
1949 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1950 | ||
1951 | ack_APIC_irq(); | |
1952 | ||
1953 | if (!(v & (1 << (i & 0x1f)))) { | |
1954 | atomic_inc(&irq_mis_count); | |
1955 | spin_lock(&ioapic_lock); | |
1956 | __mask_and_edge_IO_APIC_irq(irq); | |
1957 | __unmask_and_level_IO_APIC_irq(irq); | |
1958 | spin_unlock(&ioapic_lock); | |
1959 | } | |
1960 | } | |
1961 | ||
ace80ab7 | 1962 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1963 | { |
b940d22d | 1964 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1965 | |
1966 | return 1; | |
1967 | } | |
1968 | ||
f5b9ed7a IM |
1969 | static struct irq_chip ioapic_chip __read_mostly = { |
1970 | .name = "IO-APIC", | |
ace80ab7 EB |
1971 | .startup = startup_ioapic_irq, |
1972 | .mask = mask_IO_APIC_irq, | |
1973 | .unmask = unmask_IO_APIC_irq, | |
1974 | .ack = ack_ioapic_irq, | |
1975 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 1976 | #ifdef CONFIG_SMP |
ace80ab7 | 1977 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1978 | #endif |
ace80ab7 | 1979 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1980 | }; |
1981 | ||
1da177e4 LT |
1982 | |
1983 | static inline void init_IO_APIC_traps(void) | |
1984 | { | |
1985 | int irq; | |
1986 | ||
1987 | /* | |
1988 | * NOTE! The local APIC isn't very good at handling | |
1989 | * multiple interrupts at the same interrupt level. | |
1990 | * As the interrupt level is determined by taking the | |
1991 | * vector number and shifting that right by 4, we | |
1992 | * want to spread these out a bit so that they don't | |
1993 | * all fall in the same interrupt level. | |
1994 | * | |
1995 | * Also, we've got to be careful not to trash gate | |
1996 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1997 | */ | |
1998 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
addfc66b | 1999 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
2000 | /* |
2001 | * Hmm.. We don't have an entry for this, | |
2002 | * so default to an old-fashioned 8259 | |
2003 | * interrupt if we can.. | |
2004 | */ | |
2005 | if (irq < 16) | |
2006 | make_8259A_irq(irq); | |
2007 | else | |
2008 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2009 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2010 | } |
2011 | } | |
2012 | } | |
2013 | ||
f5b9ed7a IM |
2014 | /* |
2015 | * The local APIC irq-chip implementation: | |
2016 | */ | |
1da177e4 | 2017 | |
f5b9ed7a IM |
2018 | static void ack_apic(unsigned int irq) |
2019 | { | |
2020 | ack_APIC_irq(); | |
1da177e4 LT |
2021 | } |
2022 | ||
f5b9ed7a | 2023 | static void mask_lapic_irq (unsigned int irq) |
1da177e4 LT |
2024 | { |
2025 | unsigned long v; | |
2026 | ||
2027 | v = apic_read(APIC_LVT0); | |
2028 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2029 | } | |
2030 | ||
f5b9ed7a | 2031 | static void unmask_lapic_irq (unsigned int irq) |
1da177e4 | 2032 | { |
f5b9ed7a | 2033 | unsigned long v; |
1da177e4 | 2034 | |
f5b9ed7a IM |
2035 | v = apic_read(APIC_LVT0); |
2036 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2037 | } | |
1da177e4 | 2038 | |
f5b9ed7a IM |
2039 | static struct irq_chip lapic_chip __read_mostly = { |
2040 | .name = "local-APIC-edge", | |
2041 | .mask = mask_lapic_irq, | |
2042 | .unmask = unmask_lapic_irq, | |
2043 | .eoi = ack_apic, | |
1da177e4 LT |
2044 | }; |
2045 | ||
e9427101 | 2046 | static void __init setup_nmi(void) |
1da177e4 LT |
2047 | { |
2048 | /* | |
2049 | * Dirty trick to enable the NMI watchdog ... | |
2050 | * We put the 8259A master into AEOI mode and | |
2051 | * unmask on all local APICs LVT0 as NMI. | |
2052 | * | |
2053 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2054 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2055 | * the NMI handler or the timer interrupt. | |
2056 | */ | |
2057 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); | |
2058 | ||
e9427101 | 2059 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2060 | |
2061 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * This looks a bit hackish but it's about the only one way of sending | |
2066 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2067 | * not support the ExtINT mode, unfortunately. We need to send these | |
2068 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2069 | * 8259A interrupt line asserted until INTA. --macro | |
2070 | */ | |
28acf285 | 2071 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2072 | { |
fcfd636a | 2073 | int apic, pin, i; |
1da177e4 LT |
2074 | struct IO_APIC_route_entry entry0, entry1; |
2075 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2076 | |
fcfd636a | 2077 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2078 | if (pin == -1) { |
2079 | WARN_ON_ONCE(1); | |
2080 | return; | |
2081 | } | |
fcfd636a | 2082 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2083 | if (apic == -1) { |
2084 | WARN_ON_ONCE(1); | |
1da177e4 | 2085 | return; |
956fb531 | 2086 | } |
1da177e4 | 2087 | |
cf4c6a2f | 2088 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2089 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2090 | |
2091 | memset(&entry1, 0, sizeof(entry1)); | |
2092 | ||
2093 | entry1.dest_mode = 0; /* physical delivery */ | |
2094 | entry1.mask = 0; /* unmask IRQ now */ | |
2095 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2096 | entry1.delivery_mode = dest_ExtINT; | |
2097 | entry1.polarity = entry0.polarity; | |
2098 | entry1.trigger = 0; | |
2099 | entry1.vector = 0; | |
2100 | ||
cf4c6a2f | 2101 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2102 | |
2103 | save_control = CMOS_READ(RTC_CONTROL); | |
2104 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2105 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2106 | RTC_FREQ_SELECT); | |
2107 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2108 | ||
2109 | i = 100; | |
2110 | while (i-- > 0) { | |
2111 | mdelay(10); | |
2112 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2113 | i -= 10; | |
2114 | } | |
2115 | ||
2116 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2117 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2118 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2119 | |
cf4c6a2f | 2120 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2121 | } |
2122 | ||
2123 | /* | |
2124 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2125 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2126 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2127 | * fanatically on his truly buggy board. | |
2128 | */ | |
8542b200 | 2129 | static inline void __init check_timer(void) |
1da177e4 | 2130 | { |
fcfd636a | 2131 | int apic1, pin1, apic2, pin2; |
1da177e4 | 2132 | int vector; |
6e908947 | 2133 | unsigned int ver; |
4aae0702 IM |
2134 | unsigned long flags; |
2135 | ||
2136 | local_irq_save(flags); | |
d4d25dec | 2137 | |
6e908947 IM |
2138 | ver = apic_read(APIC_LVR); |
2139 | ver = GET_APIC_VERSION(ver); | |
2140 | ||
1da177e4 LT |
2141 | /* |
2142 | * get/set the timer IRQ vector: | |
2143 | */ | |
2144 | disable_8259A_irq(0); | |
2145 | vector = assign_irq_vector(0); | |
2146 | set_intr_gate(vector, interrupt[0]); | |
2147 | ||
2148 | /* | |
2149 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
2150 | * mode for the 8259A whenever interrupts are routed | |
2151 | * through I/O APICs. Also IRQ0 has to be enabled in | |
2152 | * the 8259A which implies the virtual wire has to be | |
6e908947 IM |
2153 | * disabled in the local APIC. Finally timer interrupts |
2154 | * need to be acknowledged manually in the 8259A for | |
2155 | * timer_interrupt() and for the i82489DX when using | |
2156 | * the NMI watchdog. | |
1da177e4 LT |
2157 | */ |
2158 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2159 | init_8259A(1); | |
6e908947 IM |
2160 | timer_ack = !cpu_has_tsc; |
2161 | timer_ack |= (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
f9262c12 AK |
2162 | if (timer_over_8254 > 0) |
2163 | enable_8259A_irq(0); | |
1da177e4 | 2164 | |
fcfd636a EB |
2165 | pin1 = find_isa_irq_pin(0, mp_INT); |
2166 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2167 | pin2 = ioapic_i8259.pin; | |
2168 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2169 | |
fcfd636a EB |
2170 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2171 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
2172 | |
2173 | if (pin1 != -1) { | |
2174 | /* | |
2175 | * Ok, does IRQ0 through the IOAPIC work? | |
2176 | */ | |
2177 | unmask_IO_APIC_irq(0); | |
2178 | if (timer_irq_works()) { | |
2179 | if (nmi_watchdog == NMI_IO_APIC) { | |
2180 | disable_8259A_irq(0); | |
2181 | setup_nmi(); | |
2182 | enable_8259A_irq(0); | |
1da177e4 | 2183 | } |
66759a01 CE |
2184 | if (disable_timer_pin_1 > 0) |
2185 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2186 | goto out; |
1da177e4 | 2187 | } |
fcfd636a EB |
2188 | clear_IO_APIC_pin(apic1, pin1); |
2189 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " | |
2190 | "IO-APIC\n"); | |
1da177e4 LT |
2191 | } |
2192 | ||
2193 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
2194 | if (pin2 != -1) { | |
2195 | printk("\n..... (found pin %d) ...", pin2); | |
2196 | /* | |
2197 | * legacy devices should be connected to IO APIC #0 | |
2198 | */ | |
fcfd636a | 2199 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
1da177e4 LT |
2200 | if (timer_irq_works()) { |
2201 | printk("works.\n"); | |
2202 | if (pin1 != -1) | |
fcfd636a | 2203 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
1da177e4 | 2204 | else |
fcfd636a | 2205 | add_pin_to_irq(0, apic2, pin2); |
1da177e4 LT |
2206 | if (nmi_watchdog == NMI_IO_APIC) { |
2207 | setup_nmi(); | |
1da177e4 | 2208 | } |
4aae0702 | 2209 | goto out; |
1da177e4 LT |
2210 | } |
2211 | /* | |
2212 | * Cleanup, just in case ... | |
2213 | */ | |
fcfd636a | 2214 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 LT |
2215 | } |
2216 | printk(" failed.\n"); | |
2217 | ||
2218 | if (nmi_watchdog == NMI_IO_APIC) { | |
2219 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
2220 | nmi_watchdog = 0; | |
2221 | } | |
2222 | ||
2223 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2224 | ||
2225 | disable_8259A_irq(0); | |
a460e745 | 2226 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2e188938 | 2227 | "fasteoi"); |
1da177e4 LT |
2228 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2229 | enable_8259A_irq(0); | |
2230 | ||
2231 | if (timer_irq_works()) { | |
2232 | printk(" works.\n"); | |
4aae0702 | 2233 | goto out; |
1da177e4 LT |
2234 | } |
2235 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); | |
2236 | printk(" failed.\n"); | |
2237 | ||
2238 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2239 | ||
2240 | timer_ack = 0; | |
2241 | init_8259A(0); | |
2242 | make_8259A_irq(0); | |
2243 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2244 | ||
2245 | unlock_ExtINT_logic(); | |
2246 | ||
2247 | if (timer_irq_works()) { | |
2248 | printk(" works.\n"); | |
4aae0702 | 2249 | goto out; |
1da177e4 LT |
2250 | } |
2251 | printk(" failed :(.\n"); | |
2252 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2253 | "report. Then try booting with the 'noapic' option"); | |
4aae0702 IM |
2254 | out: |
2255 | local_irq_restore(flags); | |
1da177e4 LT |
2256 | } |
2257 | ||
2258 | /* | |
2259 | * | |
2260 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2261 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2262 | * Linux doesn't really care, as it's not actually used | |
2263 | * for any interrupt handling anyway. | |
2264 | */ | |
2265 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2266 | ||
2267 | void __init setup_IO_APIC(void) | |
2268 | { | |
dbeb2be2 RR |
2269 | int i; |
2270 | ||
2271 | /* Reserve all the system vectors. */ | |
2272 | for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++) | |
2273 | set_bit(i, used_vectors); | |
2274 | ||
1da177e4 LT |
2275 | enable_IO_APIC(); |
2276 | ||
2277 | if (acpi_ioapic) | |
2278 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2279 | else | |
2280 | io_apic_irqs = ~PIC_IRQS; | |
2281 | ||
2282 | printk("ENABLING IO-APIC IRQs\n"); | |
2283 | ||
2284 | /* | |
2285 | * Set up IO-APIC IRQ routing. | |
2286 | */ | |
2287 | if (!acpi_ioapic) | |
2288 | setup_ioapic_ids_from_mpc(); | |
2289 | sync_Arb_IDs(); | |
2290 | setup_IO_APIC_irqs(); | |
2291 | init_IO_APIC_traps(); | |
1e4c85f9 | 2292 | check_timer(); |
1da177e4 LT |
2293 | if (!acpi_ioapic) |
2294 | print_IO_APIC(); | |
2295 | } | |
2296 | ||
f9262c12 AK |
2297 | static int __init setup_disable_8254_timer(char *s) |
2298 | { | |
2299 | timer_over_8254 = -1; | |
2300 | return 1; | |
2301 | } | |
2302 | static int __init setup_enable_8254_timer(char *s) | |
2303 | { | |
2304 | timer_over_8254 = 2; | |
2305 | return 1; | |
2306 | } | |
2307 | ||
2308 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
2309 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
2310 | ||
1da177e4 LT |
2311 | /* |
2312 | * Called after all the initialization is done. If we didnt find any | |
2313 | * APIC bugs then we can allow the modify fast path | |
2314 | */ | |
2315 | ||
2316 | static int __init io_apic_bug_finalize(void) | |
2317 | { | |
2318 | if(sis_apic_bug == -1) | |
2319 | sis_apic_bug = 0; | |
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | late_initcall(io_apic_bug_finalize); | |
2324 | ||
2325 | struct sysfs_ioapic_data { | |
2326 | struct sys_device dev; | |
2327 | struct IO_APIC_route_entry entry[0]; | |
2328 | }; | |
2329 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2330 | ||
438510f6 | 2331 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2332 | { |
2333 | struct IO_APIC_route_entry *entry; | |
2334 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2335 | int i; |
2336 | ||
2337 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2338 | entry = data->entry; | |
cf4c6a2f AK |
2339 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2340 | entry[i] = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2341 | |
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | static int ioapic_resume(struct sys_device *dev) | |
2346 | { | |
2347 | struct IO_APIC_route_entry *entry; | |
2348 | struct sysfs_ioapic_data *data; | |
2349 | unsigned long flags; | |
2350 | union IO_APIC_reg_00 reg_00; | |
2351 | int i; | |
2352 | ||
2353 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2354 | entry = data->entry; | |
2355 | ||
2356 | spin_lock_irqsave(&ioapic_lock, flags); | |
2357 | reg_00.raw = io_apic_read(dev->id, 0); | |
2358 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
2359 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
2360 | io_apic_write(dev->id, 0, reg_00.raw); | |
2361 | } | |
1da177e4 | 2362 | spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
2363 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2364 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2365 | |
2366 | return 0; | |
2367 | } | |
2368 | ||
2369 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2370 | .name = "ioapic", |
1da177e4 LT |
2371 | .suspend = ioapic_suspend, |
2372 | .resume = ioapic_resume, | |
2373 | }; | |
2374 | ||
2375 | static int __init ioapic_init_sysfs(void) | |
2376 | { | |
2377 | struct sys_device * dev; | |
2378 | int i, size, error = 0; | |
2379 | ||
2380 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2381 | if (error) | |
2382 | return error; | |
2383 | ||
2384 | for (i = 0; i < nr_ioapics; i++ ) { | |
2385 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2386 | * sizeof(struct IO_APIC_route_entry); | |
2387 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
2388 | if (!mp_ioapic_data[i]) { | |
2389 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2390 | continue; | |
2391 | } | |
2392 | memset(mp_ioapic_data[i], 0, size); | |
2393 | dev = &mp_ioapic_data[i]->dev; | |
2394 | dev->id = i; | |
2395 | dev->cls = &ioapic_sysdev_class; | |
2396 | error = sysdev_register(dev); | |
2397 | if (error) { | |
2398 | kfree(mp_ioapic_data[i]); | |
2399 | mp_ioapic_data[i] = NULL; | |
2400 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2401 | continue; | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | return 0; | |
2406 | } | |
2407 | ||
2408 | device_initcall(ioapic_init_sysfs); | |
2409 | ||
3fc471ed | 2410 | /* |
95d77884 | 2411 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2412 | */ |
2413 | int create_irq(void) | |
2414 | { | |
ace80ab7 | 2415 | /* Allocate an unused irq */ |
306a22c2 | 2416 | int irq, new, vector = 0; |
3fc471ed | 2417 | unsigned long flags; |
3fc471ed | 2418 | |
ace80ab7 EB |
2419 | irq = -ENOSPC; |
2420 | spin_lock_irqsave(&vector_lock, flags); | |
2421 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2422 | if (platform_legacy_irq(new)) | |
2423 | continue; | |
2424 | if (irq_vector[new] != 0) | |
2425 | continue; | |
2426 | vector = __assign_irq_vector(new); | |
2427 | if (likely(vector > 0)) | |
2428 | irq = new; | |
2429 | break; | |
2430 | } | |
2431 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2432 | |
ace80ab7 | 2433 | if (irq >= 0) { |
3fc471ed | 2434 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2435 | dynamic_irq_init(irq); |
2436 | } | |
2437 | return irq; | |
2438 | } | |
2439 | ||
2440 | void destroy_irq(unsigned int irq) | |
2441 | { | |
2442 | unsigned long flags; | |
3fc471ed EB |
2443 | |
2444 | dynamic_irq_cleanup(irq); | |
2445 | ||
2446 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2447 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2448 | irq_vector[irq] = 0; |
2449 | spin_unlock_irqrestore(&vector_lock, flags); | |
2450 | } | |
3fc471ed | 2451 | |
2d3fcc1c | 2452 | /* |
27b46d76 | 2453 | * MSI message composition |
2d3fcc1c EB |
2454 | */ |
2455 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2456 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2457 | { |
2d3fcc1c EB |
2458 | int vector; |
2459 | unsigned dest; | |
2460 | ||
2461 | vector = assign_irq_vector(irq); | |
2462 | if (vector >= 0) { | |
2463 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2464 | ||
2465 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2466 | msg->address_lo = | |
2467 | MSI_ADDR_BASE_LO | | |
2468 | ((INT_DEST_MODE == 0) ? | |
2469 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2470 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2471 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2472 | MSI_ADDR_REDIRECTION_CPU: | |
2473 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2474 | MSI_ADDR_DEST_ID(dest); | |
2475 | ||
2476 | msg->data = | |
2477 | MSI_DATA_TRIGGER_EDGE | | |
2478 | MSI_DATA_LEVEL_ASSERT | | |
2479 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2480 | MSI_DATA_DELIVERY_FIXED: | |
2481 | MSI_DATA_DELIVERY_LOWPRI) | | |
2482 | MSI_DATA_VECTOR(vector); | |
2483 | } | |
2484 | return vector; | |
2485 | } | |
2486 | ||
3b7d1921 EB |
2487 | #ifdef CONFIG_SMP |
2488 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2489 | { |
3b7d1921 EB |
2490 | struct msi_msg msg; |
2491 | unsigned int dest; | |
2492 | cpumask_t tmp; | |
2d3fcc1c | 2493 | int vector; |
3b7d1921 EB |
2494 | |
2495 | cpus_and(tmp, mask, cpu_online_map); | |
2496 | if (cpus_empty(tmp)) | |
2497 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2498 | |
2499 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2500 | if (vector < 0) |
2501 | return; | |
2d3fcc1c | 2502 | |
3b7d1921 EB |
2503 | dest = cpu_mask_to_apicid(mask); |
2504 | ||
2505 | read_msi_msg(irq, &msg); | |
2506 | ||
2507 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2508 | msg.data |= MSI_DATA_VECTOR(vector); | |
2509 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2510 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2511 | ||
2512 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2513 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2514 | } |
3b7d1921 | 2515 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2516 | |
3b7d1921 EB |
2517 | /* |
2518 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2519 | * which implement the MSI or MSI-X Capability Structure. | |
2520 | */ | |
2521 | static struct irq_chip msi_chip = { | |
2522 | .name = "PCI-MSI", | |
2523 | .unmask = unmask_msi_irq, | |
2524 | .mask = mask_msi_irq, | |
2525 | .ack = ack_ioapic_irq, | |
2526 | #ifdef CONFIG_SMP | |
2527 | .set_affinity = set_msi_irq_affinity, | |
2528 | #endif | |
2529 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2530 | }; |
2531 | ||
f7feaca7 | 2532 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2533 | { |
2534 | struct msi_msg msg; | |
f7feaca7 EB |
2535 | int irq, ret; |
2536 | irq = create_irq(); | |
2537 | if (irq < 0) | |
2538 | return irq; | |
2539 | ||
3b7d1921 | 2540 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2541 | if (ret < 0) { |
2542 | destroy_irq(irq); | |
3b7d1921 | 2543 | return ret; |
f7feaca7 | 2544 | } |
3b7d1921 | 2545 | |
7fe3730d | 2546 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2547 | write_msi_msg(irq, &msg); |
2548 | ||
a460e745 IM |
2549 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2550 | "edge"); | |
3b7d1921 | 2551 | |
7fe3730d | 2552 | return 0; |
3b7d1921 EB |
2553 | } |
2554 | ||
2555 | void arch_teardown_msi_irq(unsigned int irq) | |
2556 | { | |
f7feaca7 | 2557 | destroy_irq(irq); |
3b7d1921 EB |
2558 | } |
2559 | ||
2d3fcc1c EB |
2560 | #endif /* CONFIG_PCI_MSI */ |
2561 | ||
8b955b0d EB |
2562 | /* |
2563 | * Hypertransport interrupt support | |
2564 | */ | |
2565 | #ifdef CONFIG_HT_IRQ | |
2566 | ||
2567 | #ifdef CONFIG_SMP | |
2568 | ||
2569 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2570 | { | |
ec68307c EB |
2571 | struct ht_irq_msg msg; |
2572 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2573 | |
ec68307c EB |
2574 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2575 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2576 | |
ec68307c EB |
2577 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2578 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2579 | |
ec68307c | 2580 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2581 | } |
2582 | ||
2583 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2584 | { | |
2585 | unsigned int dest; | |
2586 | cpumask_t tmp; | |
2587 | ||
2588 | cpus_and(tmp, mask, cpu_online_map); | |
2589 | if (cpus_empty(tmp)) | |
2590 | tmp = TARGET_CPUS; | |
2591 | ||
2592 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2593 | ||
2594 | dest = cpu_mask_to_apicid(mask); | |
2595 | ||
2596 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2597 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2598 | } |
2599 | #endif | |
2600 | ||
c37e108d | 2601 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2602 | .name = "PCI-HT", |
2603 | .mask = mask_ht_irq, | |
2604 | .unmask = unmask_ht_irq, | |
2605 | .ack = ack_ioapic_irq, | |
2606 | #ifdef CONFIG_SMP | |
2607 | .set_affinity = set_ht_irq_affinity, | |
2608 | #endif | |
2609 | .retrigger = ioapic_retrigger_irq, | |
2610 | }; | |
2611 | ||
2612 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2613 | { | |
2614 | int vector; | |
2615 | ||
2616 | vector = assign_irq_vector(irq); | |
2617 | if (vector >= 0) { | |
ec68307c | 2618 | struct ht_irq_msg msg; |
8b955b0d EB |
2619 | unsigned dest; |
2620 | cpumask_t tmp; | |
2621 | ||
2622 | cpus_clear(tmp); | |
2623 | cpu_set(vector >> 8, tmp); | |
2624 | dest = cpu_mask_to_apicid(tmp); | |
2625 | ||
ec68307c | 2626 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2627 | |
ec68307c EB |
2628 | msg.address_lo = |
2629 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2630 | HT_IRQ_LOW_DEST_ID(dest) | |
2631 | HT_IRQ_LOW_VECTOR(vector) | | |
2632 | ((INT_DEST_MODE == 0) ? | |
2633 | HT_IRQ_LOW_DM_PHYSICAL : | |
2634 | HT_IRQ_LOW_DM_LOGICAL) | | |
2635 | HT_IRQ_LOW_RQEOI_EDGE | | |
2636 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2637 | HT_IRQ_LOW_MT_FIXED : | |
2638 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2639 | HT_IRQ_LOW_IRQ_MASKED; | |
2640 | ||
ec68307c | 2641 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2642 | |
a460e745 IM |
2643 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2644 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2645 | } |
2646 | return vector; | |
2647 | } | |
2648 | #endif /* CONFIG_HT_IRQ */ | |
2649 | ||
1da177e4 LT |
2650 | /* -------------------------------------------------------------------------- |
2651 | ACPI-based IOAPIC Configuration | |
2652 | -------------------------------------------------------------------------- */ | |
2653 | ||
888ba6c6 | 2654 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2655 | |
2656 | int __init io_apic_get_unique_id (int ioapic, int apic_id) | |
2657 | { | |
2658 | union IO_APIC_reg_00 reg_00; | |
2659 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2660 | physid_mask_t tmp; | |
2661 | unsigned long flags; | |
2662 | int i = 0; | |
2663 | ||
2664 | /* | |
2665 | * The P4 platform supports up to 256 APIC IDs on two separate APIC | |
2666 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
2667 | * supports up to 16 on one shared APIC bus. | |
2668 | * | |
2669 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full | |
2670 | * advantage of new APIC bus architecture. | |
2671 | */ | |
2672 | ||
2673 | if (physids_empty(apic_id_map)) | |
2674 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2675 | ||
2676 | spin_lock_irqsave(&ioapic_lock, flags); | |
2677 | reg_00.raw = io_apic_read(ioapic, 0); | |
2678 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2679 | ||
2680 | if (apic_id >= get_physical_broadcast()) { | |
2681 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2682 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2683 | apic_id = reg_00.bits.ID; | |
2684 | } | |
2685 | ||
2686 | /* | |
2687 | * Every APIC in a system must have a unique ID or we get lots of nice | |
2688 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2689 | */ | |
2690 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2691 | ||
2692 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2693 | if (!check_apicid_used(apic_id_map, i)) | |
2694 | break; | |
2695 | } | |
2696 | ||
2697 | if (i == get_physical_broadcast()) | |
2698 | panic("Max apic_id exceeded!\n"); | |
2699 | ||
2700 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2701 | "trying %d\n", ioapic, apic_id, i); | |
2702 | ||
2703 | apic_id = i; | |
2704 | } | |
2705 | ||
2706 | tmp = apicid_to_cpu_present(apic_id); | |
2707 | physids_or(apic_id_map, apic_id_map, tmp); | |
2708 | ||
2709 | if (reg_00.bits.ID != apic_id) { | |
2710 | reg_00.bits.ID = apic_id; | |
2711 | ||
2712 | spin_lock_irqsave(&ioapic_lock, flags); | |
2713 | io_apic_write(ioapic, 0, reg_00.raw); | |
2714 | reg_00.raw = io_apic_read(ioapic, 0); | |
2715 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2716 | ||
2717 | /* Sanity check */ | |
6070f9ec AD |
2718 | if (reg_00.bits.ID != apic_id) { |
2719 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2720 | return -1; | |
2721 | } | |
1da177e4 LT |
2722 | } |
2723 | ||
2724 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2725 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2726 | ||
2727 | return apic_id; | |
2728 | } | |
2729 | ||
2730 | ||
2731 | int __init io_apic_get_version (int ioapic) | |
2732 | { | |
2733 | union IO_APIC_reg_01 reg_01; | |
2734 | unsigned long flags; | |
2735 | ||
2736 | spin_lock_irqsave(&ioapic_lock, flags); | |
2737 | reg_01.raw = io_apic_read(ioapic, 1); | |
2738 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2739 | ||
2740 | return reg_01.bits.version; | |
2741 | } | |
2742 | ||
2743 | ||
2744 | int __init io_apic_get_redir_entries (int ioapic) | |
2745 | { | |
2746 | union IO_APIC_reg_01 reg_01; | |
2747 | unsigned long flags; | |
2748 | ||
2749 | spin_lock_irqsave(&ioapic_lock, flags); | |
2750 | reg_01.raw = io_apic_read(ioapic, 1); | |
2751 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2752 | ||
2753 | return reg_01.bits.entries; | |
2754 | } | |
2755 | ||
2756 | ||
2757 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
2758 | { | |
2759 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2760 | |
2761 | if (!IO_APIC_IRQ(irq)) { | |
2762 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2763 | ioapic); | |
2764 | return -EINVAL; | |
2765 | } | |
2766 | ||
2767 | /* | |
2768 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2769 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2770 | * corresponding device driver registers for this IRQ. | |
2771 | */ | |
2772 | ||
2773 | memset(&entry,0,sizeof(entry)); | |
2774 | ||
2775 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2776 | entry.dest_mode = INT_DEST_MODE; | |
2777 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2778 | entry.trigger = edge_level; | |
2779 | entry.polarity = active_high_low; | |
2780 | entry.mask = 1; | |
2781 | ||
2782 | /* | |
2783 | * IRQs < 16 are already in the irq_2_pin[] map | |
2784 | */ | |
2785 | if (irq >= 16) | |
2786 | add_pin_to_irq(irq, ioapic, pin); | |
2787 | ||
2788 | entry.vector = assign_irq_vector(irq); | |
2789 | ||
2790 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2791 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
2792 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
2793 | edge_level, active_high_low); | |
2794 | ||
2795 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2796 | ||
2797 | if (!ioapic && (irq < 16)) | |
2798 | disable_8259A_irq(irq); | |
2799 | ||
a2249cba | 2800 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2801 | |
2802 | return 0; | |
2803 | } | |
2804 | ||
61fd47e0 SL |
2805 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2806 | { | |
2807 | int i; | |
2808 | ||
2809 | if (skip_ioapic_setup) | |
2810 | return -1; | |
2811 | ||
2812 | for (i = 0; i < mp_irq_entries; i++) | |
2813 | if (mp_irqs[i].mpc_irqtype == mp_INT && | |
2814 | mp_irqs[i].mpc_srcbusirq == bus_irq) | |
2815 | break; | |
2816 | if (i >= mp_irq_entries) | |
2817 | return -1; | |
2818 | ||
2819 | *trigger = irq_trigger(i); | |
2820 | *polarity = irq_polarity(i); | |
2821 | return 0; | |
2822 | } | |
2823 | ||
888ba6c6 | 2824 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2825 | |
2826 | static int __init parse_disable_timer_pin_1(char *arg) | |
2827 | { | |
2828 | disable_timer_pin_1 = 1; | |
2829 | return 0; | |
2830 | } | |
2831 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2832 | ||
2833 | static int __init parse_enable_timer_pin_1(char *arg) | |
2834 | { | |
2835 | disable_timer_pin_1 = -1; | |
2836 | return 0; | |
2837 | } | |
2838 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2839 | ||
2840 | static int __init parse_noapic(char *arg) | |
2841 | { | |
2842 | /* disable IO-APIC */ | |
2843 | disable_ioapic_setup(); | |
2844 | return 0; | |
2845 | } | |
2846 | early_param("noapic", parse_noapic); |