[deliverable/linux.git] / arch / x86 / kernel / iosf_mbi.c

/*
 * IOSF-SB MailBox Interface Driver
 * Copyright (c) 2013, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 *
 * The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
 * mailbox interface (MBI) to communicate with mutiple devices. This
 * driver implements access to this interface for those platforms that can
 * enumerate the device using PCI.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/debugfs.h>
#include <linux/capability.h>

#include <asm/iosf_mbi.h>

#define PCI_DEVICE_ID_BAYTRAIL		0x0F00
#define PCI_DEVICE_ID_QUARK_X1000	0x0958

static DEFINE_SPINLOCK(iosf_mbi_lock);

static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
{
	return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
}

static struct pci_dev *mbi_pdev;	/* one mbi device */

static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
{
	int result;

	if (!mbi_pdev)
		return -ENODEV;

	if (mcrx) {
		result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
						mcrx);
		if (result < 0)
			goto fail_read;
	}

	result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
	if (result < 0)
		goto fail_read;

	result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
	if (result < 0)
		goto fail_read;

	return 0;

fail_read:
	dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
	return result;
}

static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
{
	int result;

	if (!mbi_pdev)
		return -ENODEV;

	result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
	if (result < 0)
		goto fail_write;

	if (mcrx) {
		result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
						mcrx);
		if (result < 0)
			goto fail_write;
	}

	result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
	if (result < 0)
		goto fail_write;

	return 0;

fail_write:
	dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
	return result;
}

int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
{
	u32 mcr, mcrx;
	unsigned long flags;
	int ret;

	/*Access to the GFX unit is handled by GPU code */
	if (port == BT_MBI_UNIT_GFX) {
		WARN_ON(1);
		return -EPERM;
	}

	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
	mcrx = offset & MBI_MASK_HI;

	spin_lock_irqsave(&iosf_mbi_lock, flags);
	ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
	spin_unlock_irqrestore(&iosf_mbi_lock, flags);

	return ret;
}
EXPORT_SYMBOL(iosf_mbi_read);

int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
{
	u32 mcr, mcrx;
	unsigned long flags;
	int ret;

	/*Access to the GFX unit is handled by GPU code */
	if (port == BT_MBI_UNIT_GFX) {
		WARN_ON(1);
		return -EPERM;
	}

	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
	mcrx = offset & MBI_MASK_HI;

	spin_lock_irqsave(&iosf_mbi_lock, flags);
	ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
	spin_unlock_irqrestore(&iosf_mbi_lock, flags);

	return ret;
}
EXPORT_SYMBOL(iosf_mbi_write);

int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
{
	u32 mcr, mcrx;
	u32 value;
	unsigned long flags;
	int ret;

	/*Access to the GFX unit is handled by GPU code */
	if (port == BT_MBI_UNIT_GFX) {
		WARN_ON(1);
		return -EPERM;
	}

	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
	mcrx = offset & MBI_MASK_HI;

	spin_lock_irqsave(&iosf_mbi_lock, flags);

	/* Read current mdr value */
	ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
	if (ret < 0) {
		spin_unlock_irqrestore(&iosf_mbi_lock, flags);
		return ret;
	}

	/* Apply mask */
	value &= ~mask;
	mdr &= mask;
	value |= mdr;

	/* Write back */
	ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value);

	spin_unlock_irqrestore(&iosf_mbi_lock, flags);

	return ret;
}
EXPORT_SYMBOL(iosf_mbi_modify);

bool iosf_mbi_available(void)
{
	/* Mbi isn't hot-pluggable. No remove routine is provided */
	return mbi_pdev;
}
EXPORT_SYMBOL(iosf_mbi_available);

/********************** debugfs begin ****************************/
static u32	dbg_mdr;
static u32	dbg_mcr;
static u32	dbg_mcrx;

static int mcr_get(void *data, u64 *val)
{
	*val = *(u32 *)data;
	return 0;
}

static int mcr_set(void *data, u64 val)
{
	u8 command = ((u32)val & 0xFF000000) >> 24,
	   port	   = ((u32)val & 0x00FF0000) >> 16,
	   offset  = ((u32)val & 0x0000FF00) >> 8;
	int err;

	*(u32 *)data = val;

	if (!capable(CAP_SYS_RAWIO))
		return -EACCES;

	if (command & 1u)
		err = iosf_mbi_write(port,
			       command,
			       dbg_mcrx | offset,
			       dbg_mdr);
	else
		err = iosf_mbi_read(port,
			      command,
			      dbg_mcrx | offset,
			      &dbg_mdr);

	return err;
}
DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");

static struct dentry *iosf_dbg;
static void iosf_sideband_debug_init(void)
{
	struct dentry *d;

	iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
	if (IS_ERR_OR_NULL(iosf_dbg))
		return;

	/* mdr */
	d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
	if (IS_ERR_OR_NULL(d))
		goto cleanup;

	/* mcrx */
	debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
	if (IS_ERR_OR_NULL(d))
		goto cleanup;

	/* mcr - initiates mailbox tranaction */
	debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
	if (IS_ERR_OR_NULL(d))
		goto cleanup;

	return;

cleanup:
	debugfs_remove_recursive(d);
}
/********************** debugfs end ****************************/

static int iosf_mbi_probe(struct pci_dev *pdev,
			  const struct pci_device_id *unused)
{
	int ret;

	ret = pci_enable_device(pdev);
	if (ret < 0) {
		dev_err(&pdev->dev, "error: could not enable device\n");
		return ret;
	}

	mbi_pdev = pci_dev_get(pdev);
	return 0;
}

static const struct pci_device_id iosf_mbi_pci_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);

static struct pci_driver iosf_mbi_pci_driver = {
	.name		= "iosf_mbi_pci",
	.probe		= iosf_mbi_probe,
	.id_table	= iosf_mbi_pci_ids,
};

static int __init iosf_mbi_init(void)
{
	iosf_sideband_debug_init();
	return pci_register_driver(&iosf_mbi_pci_driver);
}

static void __exit iosf_mbi_exit(void)
{
	debugfs_remove_recursive(iosf_dbg);

	pci_unregister_driver(&iosf_mbi_pci_driver);
	if (mbi_pdev) {
		pci_dev_put(mbi_pdev);
		mbi_pdev = NULL;
	}
}

module_init(iosf_mbi_init);
module_exit(iosf_mbi_exit);

MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
46184415 DB	1	/*
	2	* IOSF-SB MailBox Interface Driver
	3	* Copyright (c) 2013, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	*
	15	* The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
	16	* mailbox interface (MBI) to communicate with mutiple devices. This
	17	* driver implements access to this interface for those platforms that can
	18	* enumerate the device using PCI.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/init.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/pci.h>
8dc12f93 DB	25	#include <linux/debugfs.h>
8dc12f93 DB	26	#include <linux/capability.h>
46184415 DB	27
	28	#include <asm/iosf_mbi.h>
	29
04725ad5 OBL	30	#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
	31	#define PCI_DEVICE_ID_QUARK_X1000 0x0958
	32
46184415 DB	33	static DEFINE_SPINLOCK(iosf_mbi_lock);
	34
	35	static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
	36	{
	37	return (op << 24) \| (port << 16) \| (offset << 8) \| MBI_ENABLE;
	38	}
	39
	40	static struct pci_dev mbi_pdev; / one mbi device */
	41
	42	static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
	43	{
	44	int result;
	45
	46	if (!mbi_pdev)
	47	return -ENODEV;
	48
	49	if (mcrx) {
	50	result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
	51	mcrx);
	52	if (result < 0)
	53	goto fail_read;
	54	}
	55
	56	result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
	57	if (result < 0)
	58	goto fail_read;
	59
	60	result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
	61	if (result < 0)
	62	goto fail_read;
	63
	64	return 0;
	65
	66	fail_read:
	67	dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
	68	return result;
	69	}
	70
	71	static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
	72	{
	73	int result;
	74
	75	if (!mbi_pdev)
	76	return -ENODEV;
	77
	78	result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
	79	if (result < 0)
	80	goto fail_write;
	81
	82	if (mcrx) {
	83	result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
	84	mcrx);
	85	if (result < 0)
	86	goto fail_write;
	87	}
	88
	89	result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
	90	if (result < 0)
	91	goto fail_write;
	92
	93	return 0;
	94
	95	fail_write:
	96	dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
97	return result;
98	}
99
100	int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
101	{
102	u32 mcr, mcrx;
103	unsigned long flags;
104	int ret;
105
106	/Access to the GFX unit is handled by GPU code /
107	if (port == BT_MBI_UNIT_GFX) {
108	WARN_ON(1);
109	return -EPERM;
110	}
111
112	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
113	mcrx = offset & MBI_MASK_HI;
114
115	spin_lock_irqsave(&iosf_mbi_lock, flags);
116	ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
117	spin_unlock_irqrestore(&iosf_mbi_lock, flags);
118
119	return ret;
120	}
121	EXPORT_SYMBOL(iosf_mbi_read);
122
123	int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
124	{
125	u32 mcr, mcrx;
126	unsigned long flags;
127	int ret;
128
129	/Access to the GFX unit is handled by GPU code /
130	if (port == BT_MBI_UNIT_GFX) {
131	WARN_ON(1);
132	return -EPERM;
133	}
134
135	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
136	mcrx = offset & MBI_MASK_HI;
137
138	spin_lock_irqsave(&iosf_mbi_lock, flags);
139	ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
140	spin_unlock_irqrestore(&iosf_mbi_lock, flags);
141
142	return ret;
143	}
144	EXPORT_SYMBOL(iosf_mbi_write);
145
146	int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
147	{
148	u32 mcr, mcrx;
149	u32 value;
150	unsigned long flags;
151	int ret;
152
153	/Access to the GFX unit is handled by GPU code /
154	if (port == BT_MBI_UNIT_GFX) {
155	WARN_ON(1);
156	return -EPERM;
157	}
158
159	mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
160	mcrx = offset & MBI_MASK_HI;
161
162	spin_lock_irqsave(&iosf_mbi_lock, flags);
163
164	/* Read current mdr value */
165	ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
166	if (ret < 0) {
167	spin_unlock_irqrestore(&iosf_mbi_lock, flags);
168	return ret;
169	}
170
171	/* Apply mask */
172	value &= ~mask;
173	mdr &= mask;
174	value \|= mdr;
175
176	/* Write back */
177	ret = iosf_mbi_pci_write_mdr(mcrx, mcr \| MBI_WR_MASK, value);
178
179	spin_unlock_irqrestore(&iosf_mbi_lock, flags);
180
181	return ret;
182	}
183	EXPORT_SYMBOL(iosf_mbi_modify);
184
6b8f0c87 DB	185	bool iosf_mbi_available(void)
	186	{
	187	/* Mbi isn't hot-pluggable. No remove routine is provided */
	188	return mbi_pdev;
	189	}
	190	EXPORT_SYMBOL(iosf_mbi_available);
	191
8dc12f93 DB	192	/******************** debugfs begin **************************/
	193	static u32 dbg_mdr;
	194	static u32 dbg_mcr;
	195	static u32 dbg_mcrx;
	196
	197	static int mcr_get(void data, u64 val)
	198	{
	199	val = (u32 *)data;
	200	return 0;
	201	}
	202
	203	static int mcr_set(void *data, u64 val)
	204	{
	205	u8 command = ((u32)val & 0xFF000000) >> 24,
	206	port = ((u32)val & 0x00FF0000) >> 16,
	207	offset = ((u32)val & 0x0000FF00) >> 8;
	208	int err;
	209
	210	(u32 )data = val;
	211
	212	if (!capable(CAP_SYS_RAWIO))
	213	return -EACCES;
	214
	215	if (command & 1u)
	216	err = iosf_mbi_write(port,
	217	command,
	218	dbg_mcrx \| offset,
	219	dbg_mdr);
	220	else
	221	err = iosf_mbi_read(port,
	222	command,
	223	dbg_mcrx \| offset,
	224	&dbg_mdr);
	225
	226	return err;
	227	}
	228	DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
	229
	230	static struct dentry *iosf_dbg;
	231	static void iosf_sideband_debug_init(void)
	232	{
	233	struct dentry *d;
	234
	235	iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
	236	if (IS_ERR_OR_NULL(iosf_dbg))
	237	return;
	238
	239	/* mdr */
	240	d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
	241	if (IS_ERR_OR_NULL(d))
	242	goto cleanup;
	243
	244	/* mcrx */
	245	debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
	246	if (IS_ERR_OR_NULL(d))
	247	goto cleanup;
	248
	249	/* mcr - initiates mailbox tranaction */
	250	debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
	251	if (IS_ERR_OR_NULL(d))
	252	goto cleanup;
	253
	254	return;
	255
256	cleanup:
257	debugfs_remove_recursive(d);
258	}
259	/******************** debugfs end **************************/
260
46184415 DB	261	static int iosf_mbi_probe(struct pci_dev *pdev,
	262	const struct pci_device_id *unused)
	263	{
	264	int ret;
	265
	266	ret = pci_enable_device(pdev);
	267	if (ret < 0) {
	268	dev_err(&pdev->dev, "error: could not enable device\n");
	269	return ret;
	270	}
	271
	272	mbi_pdev = pci_dev_get(pdev);
	273	return 0;
	274	}
	275
9baa3c34	276	static const struct pci_device_id iosf_mbi_pci_ids[] = {
04725ad5 OBL	277	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
04725ad5 OBL	278	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
46184415 DB	279	{ 0, },
	280	};
	281	MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
	282
	283	static struct pci_driver iosf_mbi_pci_driver = {
	284	.name = "iosf_mbi_pci",
	285	.probe = iosf_mbi_probe,
	286	.id_table = iosf_mbi_pci_ids,
	287	};
	288
	289	static int __init iosf_mbi_init(void)
	290	{
8dc12f93	291	iosf_sideband_debug_init();
46184415 DB	292	return pci_register_driver(&iosf_mbi_pci_driver);
	293	}
	294
	295	static void __exit iosf_mbi_exit(void)
	296	{
8dc12f93 DB	297	debugfs_remove_recursive(iosf_dbg);
8dc12f93 DB	298
46184415 DB	299	pci_unregister_driver(&iosf_mbi_pci_driver);
	300	if (mbi_pdev) {
	301	pci_dev_put(mbi_pdev);
	302	mbi_pdev = NULL;
	303	}
	304	}
	305
	306	module_init(iosf_mbi_init);
	307	module_exit(iosf_mbi_exit);
	308
	309	MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
	310	MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
	311	MODULE_LICENSE("GPL v2");