Commit | Line | Data |
---|---|---|
6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
7 | #include <linux/seq_file.h> | |
6a02e710 | 8 | #include <linux/smp.h> |
7c1d7cdc | 9 | #include <linux/ftrace.h> |
6b39ba77 | 10 | |
7b6aa335 | 11 | #include <asm/apic.h> |
6b39ba77 | 12 | #include <asm/io_apic.h> |
c3d80000 | 13 | #include <asm/irq.h> |
7c1d7cdc | 14 | #include <asm/idle.h> |
6b39ba77 TG |
15 | |
16 | atomic_t irq_err_count; | |
17 | ||
acaabe79 DS |
18 | /* Function pointer for generic interrupt vector handling */ |
19 | void (*generic_interrupt_extension)(void) = NULL; | |
20 | ||
249f6d9e TG |
21 | /* |
22 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
23 | * each architecture has to answer this themselves. | |
24 | */ | |
25 | void ack_bad_irq(unsigned int irq) | |
26 | { | |
edea7148 CG |
27 | if (printk_ratelimit()) |
28 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 29 | |
249f6d9e TG |
30 | /* |
31 | * Currently unexpected vectors happen only on SMP and APIC. | |
32 | * We _must_ ack these because every local APIC has only N | |
33 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
34 | * holds up an irq slot - in excessive cases (when multiple | |
35 | * unexpected vectors occur) that might lock up the APIC | |
36 | * completely. | |
37 | * But only ack when the APIC is enabled -AK | |
38 | */ | |
08306ce6 | 39 | ack_APIC_irq(); |
249f6d9e TG |
40 | } |
41 | ||
1b437c8c | 42 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 TG |
43 | /* |
44 | * /proc/interrupts printing: | |
45 | */ | |
7a81d9a7 | 46 | static int show_other_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
47 | { |
48 | int j; | |
49 | ||
7a81d9a7 | 50 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
51 | for_each_online_cpu(j) |
52 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
53 | seq_printf(p, " Non-maskable interrupts\n"); | |
54 | #ifdef CONFIG_X86_LOCAL_APIC | |
7a81d9a7 | 55 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
56 | for_each_online_cpu(j) |
57 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
58 | seq_printf(p, " Local timer interrupts\n"); | |
474e56b8 JSR |
59 | |
60 | seq_printf(p, "%*s: ", prec, "SPU"); | |
61 | for_each_online_cpu(j) | |
62 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
63 | seq_printf(p, " Spurious interrupts\n"); | |
6b39ba77 | 64 | #endif |
acaabe79 | 65 | if (generic_interrupt_extension) { |
59d13812 | 66 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 DS |
67 | for_each_online_cpu(j) |
68 | seq_printf(p, "%10u ", irq_stats(j)->generic_irqs); | |
69 | seq_printf(p, " Platform interrupts\n"); | |
70 | } | |
6b39ba77 | 71 | #ifdef CONFIG_SMP |
7a81d9a7 | 72 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
73 | for_each_online_cpu(j) |
74 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
75 | seq_printf(p, " Rescheduling interrupts\n"); | |
7a81d9a7 | 76 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 TG |
77 | for_each_online_cpu(j) |
78 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); | |
79 | seq_printf(p, " Function call interrupts\n"); | |
7a81d9a7 | 80 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
81 | for_each_online_cpu(j) |
82 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
83 | seq_printf(p, " TLB shootdowns\n"); | |
84 | #endif | |
85 | #ifdef CONFIG_X86_MCE | |
7a81d9a7 | 86 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
87 | for_each_online_cpu(j) |
88 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
89 | seq_printf(p, " Thermal event interrupts\n"); | |
4efc0670 | 90 | # ifdef CONFIG_X86_MCE_THRESHOLD |
7a81d9a7 | 91 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
92 | for_each_online_cpu(j) |
93 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
94 | seq_printf(p, " Threshold APIC interrupts\n"); | |
95 | # endif | |
6b39ba77 | 96 | #endif |
7a81d9a7 | 97 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 98 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 99 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
6b39ba77 TG |
100 | #endif |
101 | return 0; | |
102 | } | |
103 | ||
104 | int show_interrupts(struct seq_file *p, void *v) | |
105 | { | |
106 | unsigned long flags, any_count = 0; | |
7a81d9a7 | 107 | int i = *(loff_t *) v, j, prec; |
6b39ba77 TG |
108 | struct irqaction *action; |
109 | struct irq_desc *desc; | |
110 | ||
111 | if (i > nr_irqs) | |
112 | return 0; | |
113 | ||
7a81d9a7 JB |
114 | for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) |
115 | j *= 10; | |
116 | ||
6b39ba77 | 117 | if (i == nr_irqs) |
7a81d9a7 | 118 | return show_other_interrupts(p, prec); |
6b39ba77 TG |
119 | |
120 | /* print header */ | |
121 | if (i == 0) { | |
7a81d9a7 | 122 | seq_printf(p, "%*s", prec + 8, ""); |
6b39ba77 | 123 | for_each_online_cpu(j) |
e9f95e63 | 124 | seq_printf(p, "CPU%-8d", j); |
6b39ba77 TG |
125 | seq_putc(p, '\n'); |
126 | } | |
127 | ||
128 | desc = irq_to_desc(i); | |
0b8f1efa YL |
129 | if (!desc) |
130 | return 0; | |
131 | ||
6b39ba77 | 132 | spin_lock_irqsave(&desc->lock, flags); |
6b39ba77 TG |
133 | for_each_online_cpu(j) |
134 | any_count |= kstat_irqs_cpu(i, j); | |
6b39ba77 TG |
135 | action = desc->action; |
136 | if (!action && !any_count) | |
137 | goto out; | |
138 | ||
7a81d9a7 | 139 | seq_printf(p, "%*d: ", prec, i); |
6b39ba77 TG |
140 | for_each_online_cpu(j) |
141 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | |
6b39ba77 TG |
142 | seq_printf(p, " %8s", desc->chip->name); |
143 | seq_printf(p, "-%-8s", desc->name); | |
144 | ||
145 | if (action) { | |
146 | seq_printf(p, " %s", action->name); | |
147 | while ((action = action->next) != NULL) | |
148 | seq_printf(p, ", %s", action->name); | |
149 | } | |
150 | ||
151 | seq_putc(p, '\n'); | |
152 | out: | |
153 | spin_unlock_irqrestore(&desc->lock, flags); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | /* | |
158 | * /proc/stat helpers | |
159 | */ | |
160 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
161 | { | |
162 | u64 sum = irq_stats(cpu)->__nmi_count; | |
163 | ||
164 | #ifdef CONFIG_X86_LOCAL_APIC | |
165 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 166 | sum += irq_stats(cpu)->irq_spurious_count; |
6b39ba77 | 167 | #endif |
acaabe79 DS |
168 | if (generic_interrupt_extension) |
169 | sum += irq_stats(cpu)->generic_irqs; | |
6b39ba77 TG |
170 | #ifdef CONFIG_SMP |
171 | sum += irq_stats(cpu)->irq_resched_count; | |
172 | sum += irq_stats(cpu)->irq_call_count; | |
173 | sum += irq_stats(cpu)->irq_tlb_count; | |
174 | #endif | |
175 | #ifdef CONFIG_X86_MCE | |
176 | sum += irq_stats(cpu)->irq_thermal_count; | |
4efc0670 | 177 | # ifdef CONFIG_X86_MCE_THRESHOLD |
6b39ba77 | 178 | sum += irq_stats(cpu)->irq_threshold_count; |
edea7148 | 179 | # endif |
6b39ba77 TG |
180 | #endif |
181 | return sum; | |
182 | } | |
183 | ||
184 | u64 arch_irq_stat(void) | |
185 | { | |
186 | u64 sum = atomic_read(&irq_err_count); | |
187 | ||
188 | #ifdef CONFIG_X86_IO_APIC | |
189 | sum += atomic_read(&irq_mis_count); | |
190 | #endif | |
191 | return sum; | |
192 | } | |
c3d80000 | 193 | |
7c1d7cdc JF |
194 | |
195 | /* | |
196 | * do_IRQ handles all normal device IRQ's (the special | |
197 | * SMP cross-CPU interrupts have their own specific | |
198 | * handlers). | |
199 | */ | |
200 | unsigned int __irq_entry do_IRQ(struct pt_regs *regs) | |
201 | { | |
202 | struct pt_regs *old_regs = set_irq_regs(regs); | |
203 | ||
204 | /* high bit used in ret_from_ code */ | |
205 | unsigned vector = ~regs->orig_ax; | |
206 | unsigned irq; | |
207 | ||
208 | exit_idle(); | |
209 | irq_enter(); | |
210 | ||
211 | irq = __get_cpu_var(vector_irq)[vector]; | |
212 | ||
213 | if (!handle_irq(irq, regs)) { | |
08306ce6 | 214 | ack_APIC_irq(); |
7c1d7cdc JF |
215 | |
216 | if (printk_ratelimit()) | |
edea7148 CG |
217 | pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", |
218 | __func__, smp_processor_id(), vector, irq); | |
7c1d7cdc JF |
219 | } |
220 | ||
221 | irq_exit(); | |
222 | ||
223 | set_irq_regs(old_regs); | |
224 | return 1; | |
225 | } | |
226 | ||
acaabe79 DS |
227 | /* |
228 | * Handler for GENERIC_INTERRUPT_VECTOR. | |
229 | */ | |
230 | void smp_generic_interrupt(struct pt_regs *regs) | |
231 | { | |
232 | struct pt_regs *old_regs = set_irq_regs(regs); | |
233 | ||
234 | ack_APIC_irq(); | |
235 | ||
236 | exit_idle(); | |
237 | ||
238 | irq_enter(); | |
239 | ||
240 | inc_irq_stat(generic_irqs); | |
241 | ||
242 | if (generic_interrupt_extension) | |
243 | generic_interrupt_extension(); | |
244 | ||
245 | irq_exit(); | |
246 | ||
247 | set_irq_regs(old_regs); | |
248 | } | |
249 | ||
c3d80000 | 250 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |