Commit | Line | Data |
---|---|---|
6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
4722d194 | 7 | #include <linux/of.h> |
6b39ba77 | 8 | #include <linux/seq_file.h> |
6a02e710 | 9 | #include <linux/smp.h> |
7c1d7cdc | 10 | #include <linux/ftrace.h> |
ca444564 | 11 | #include <linux/delay.h> |
69c60c88 | 12 | #include <linux/export.h> |
6b39ba77 | 13 | |
7b6aa335 | 14 | #include <asm/apic.h> |
6b39ba77 | 15 | #include <asm/io_apic.h> |
c3d80000 | 16 | #include <asm/irq.h> |
7c1d7cdc | 17 | #include <asm/idle.h> |
01ca79f1 | 18 | #include <asm/mce.h> |
2c1b284e | 19 | #include <asm/hw_irq.h> |
ac2a5539 | 20 | #include <asm/desc.h> |
83ab8514 SRRH |
21 | |
22 | #define CREATE_TRACE_POINTS | |
cf910e83 | 23 | #include <asm/trace/irq_vectors.h> |
6b39ba77 | 24 | |
c5bde906 BG |
25 | DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); |
26 | EXPORT_PER_CPU_SYMBOL(irq_stat); | |
27 | ||
28 | DEFINE_PER_CPU(struct pt_regs *, irq_regs); | |
29 | EXPORT_PER_CPU_SYMBOL(irq_regs); | |
30 | ||
6b39ba77 TG |
31 | atomic_t irq_err_count; |
32 | ||
acaabe79 | 33 | /* Function pointer for generic interrupt vector handling */ |
4a4de9c7 | 34 | void (*x86_platform_ipi_callback)(void) = NULL; |
acaabe79 | 35 | |
249f6d9e TG |
36 | /* |
37 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
38 | * each architecture has to answer this themselves. | |
39 | */ | |
40 | void ack_bad_irq(unsigned int irq) | |
41 | { | |
edea7148 CG |
42 | if (printk_ratelimit()) |
43 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 44 | |
249f6d9e TG |
45 | /* |
46 | * Currently unexpected vectors happen only on SMP and APIC. | |
47 | * We _must_ ack these because every local APIC has only N | |
48 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
49 | * holds up an irq slot - in excessive cases (when multiple | |
50 | * unexpected vectors occur) that might lock up the APIC | |
51 | * completely. | |
52 | * But only ack when the APIC is enabled -AK | |
53 | */ | |
08306ce6 | 54 | ack_APIC_irq(); |
249f6d9e TG |
55 | } |
56 | ||
1b437c8c | 57 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 | 58 | /* |
517e4981 | 59 | * /proc/interrupts printing for arch specific interrupts |
6b39ba77 | 60 | */ |
517e4981 | 61 | int arch_show_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
62 | { |
63 | int j; | |
64 | ||
7a81d9a7 | 65 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
66 | for_each_online_cpu(j) |
67 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
3736708f | 68 | seq_puts(p, " Non-maskable interrupts\n"); |
6b39ba77 | 69 | #ifdef CONFIG_X86_LOCAL_APIC |
7a81d9a7 | 70 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
71 | for_each_online_cpu(j) |
72 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
3736708f | 73 | seq_puts(p, " Local timer interrupts\n"); |
474e56b8 JSR |
74 | |
75 | seq_printf(p, "%*s: ", prec, "SPU"); | |
76 | for_each_online_cpu(j) | |
77 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
3736708f | 78 | seq_puts(p, " Spurious interrupts\n"); |
89ccf465 | 79 | seq_printf(p, "%*s: ", prec, "PMI"); |
241771ef IM |
80 | for_each_online_cpu(j) |
81 | seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); | |
3736708f | 82 | seq_puts(p, " Performance monitoring interrupts\n"); |
e360adbe | 83 | seq_printf(p, "%*s: ", prec, "IWI"); |
b6276f35 | 84 | for_each_online_cpu(j) |
e360adbe | 85 | seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); |
3736708f | 86 | seq_puts(p, " IRQ work interrupts\n"); |
346b46be FLVC |
87 | seq_printf(p, "%*s: ", prec, "RTR"); |
88 | for_each_online_cpu(j) | |
b49d7d87 | 89 | seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count); |
3736708f | 90 | seq_puts(p, " APIC ICR read retries\n"); |
6b39ba77 | 91 | #endif |
4a4de9c7 | 92 | if (x86_platform_ipi_callback) { |
59d13812 | 93 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 | 94 | for_each_online_cpu(j) |
4a4de9c7 | 95 | seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); |
3736708f | 96 | seq_puts(p, " Platform interrupts\n"); |
acaabe79 | 97 | } |
6b39ba77 | 98 | #ifdef CONFIG_SMP |
7a81d9a7 | 99 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
100 | for_each_online_cpu(j) |
101 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
3736708f | 102 | seq_puts(p, " Rescheduling interrupts\n"); |
7a81d9a7 | 103 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 | 104 | for_each_online_cpu(j) |
fd0f5869 TS |
105 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count - |
106 | irq_stats(j)->irq_tlb_count); | |
3736708f | 107 | seq_puts(p, " Function call interrupts\n"); |
7a81d9a7 | 108 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
109 | for_each_online_cpu(j) |
110 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
3736708f | 111 | seq_puts(p, " TLB shootdowns\n"); |
6b39ba77 | 112 | #endif |
0444c9bd | 113 | #ifdef CONFIG_X86_THERMAL_VECTOR |
7a81d9a7 | 114 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
115 | for_each_online_cpu(j) |
116 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
3736708f | 117 | seq_puts(p, " Thermal event interrupts\n"); |
0444c9bd JB |
118 | #endif |
119 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
7a81d9a7 | 120 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
121 | for_each_online_cpu(j) |
122 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
3736708f | 123 | seq_puts(p, " Threshold APIC interrupts\n"); |
01ca79f1 | 124 | #endif |
24fd78a8 AG |
125 | #ifdef CONFIG_X86_MCE_AMD |
126 | seq_printf(p, "%*s: ", prec, "DFR"); | |
127 | for_each_online_cpu(j) | |
128 | seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count); | |
129 | seq_puts(p, " Deferred Error APIC interrupts\n"); | |
130 | #endif | |
c1ebf835 | 131 | #ifdef CONFIG_X86_MCE |
01ca79f1 AK |
132 | seq_printf(p, "%*s: ", prec, "MCE"); |
133 | for_each_online_cpu(j) | |
134 | seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); | |
3736708f | 135 | seq_puts(p, " Machine check exceptions\n"); |
ca84f696 AK |
136 | seq_printf(p, "%*s: ", prec, "MCP"); |
137 | for_each_online_cpu(j) | |
138 | seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); | |
3736708f | 139 | seq_puts(p, " Machine check polls\n"); |
6b39ba77 | 140 | #endif |
f704a7d7 | 141 | #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN) |
4a0d3107 | 142 | seq_printf(p, "%*s: ", prec, "HYP"); |
929320e4 TG |
143 | for_each_online_cpu(j) |
144 | seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count); | |
3736708f | 145 | seq_puts(p, " Hypervisor callback interrupts\n"); |
929320e4 | 146 | #endif |
7a81d9a7 | 147 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 148 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 149 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
501b3265 FW |
150 | #endif |
151 | #ifdef CONFIG_HAVE_KVM | |
152 | seq_printf(p, "%*s: ", prec, "PIN"); | |
153 | for_each_online_cpu(j) | |
154 | seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis); | |
155 | seq_puts(p, " Posted-interrupt notification event\n"); | |
156 | ||
157 | seq_printf(p, "%*s: ", prec, "PIW"); | |
158 | for_each_online_cpu(j) | |
159 | seq_printf(p, "%10u ", | |
160 | irq_stats(j)->kvm_posted_intr_wakeup_ipis); | |
161 | seq_puts(p, " Posted-interrupt wakeup event\n"); | |
6b39ba77 TG |
162 | #endif |
163 | return 0; | |
164 | } | |
165 | ||
6b39ba77 TG |
166 | /* |
167 | * /proc/stat helpers | |
168 | */ | |
169 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
170 | { | |
171 | u64 sum = irq_stats(cpu)->__nmi_count; | |
172 | ||
173 | #ifdef CONFIG_X86_LOCAL_APIC | |
174 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 175 | sum += irq_stats(cpu)->irq_spurious_count; |
241771ef | 176 | sum += irq_stats(cpu)->apic_perf_irqs; |
e360adbe | 177 | sum += irq_stats(cpu)->apic_irq_work_irqs; |
b49d7d87 | 178 | sum += irq_stats(cpu)->icr_read_retry_count; |
6b39ba77 | 179 | #endif |
4a4de9c7 DS |
180 | if (x86_platform_ipi_callback) |
181 | sum += irq_stats(cpu)->x86_platform_ipis; | |
6b39ba77 TG |
182 | #ifdef CONFIG_SMP |
183 | sum += irq_stats(cpu)->irq_resched_count; | |
184 | sum += irq_stats(cpu)->irq_call_count; | |
6b39ba77 | 185 | #endif |
0444c9bd | 186 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6b39ba77 | 187 | sum += irq_stats(cpu)->irq_thermal_count; |
0444c9bd JB |
188 | #endif |
189 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
6b39ba77 | 190 | sum += irq_stats(cpu)->irq_threshold_count; |
8051dbd2 | 191 | #endif |
c1ebf835 | 192 | #ifdef CONFIG_X86_MCE |
8051dbd2 HS |
193 | sum += per_cpu(mce_exception_count, cpu); |
194 | sum += per_cpu(mce_poll_count, cpu); | |
6b39ba77 TG |
195 | #endif |
196 | return sum; | |
197 | } | |
198 | ||
199 | u64 arch_irq_stat(void) | |
200 | { | |
201 | u64 sum = atomic_read(&irq_err_count); | |
6b39ba77 TG |
202 | return sum; |
203 | } | |
c3d80000 | 204 | |
7c1d7cdc JF |
205 | |
206 | /* | |
207 | * do_IRQ handles all normal device IRQ's (the special | |
208 | * SMP cross-CPU interrupts have their own specific | |
209 | * handlers). | |
210 | */ | |
1d9090e2 | 211 | __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs) |
7c1d7cdc JF |
212 | { |
213 | struct pt_regs *old_regs = set_irq_regs(regs); | |
214 | ||
215 | /* high bit used in ret_from_ code */ | |
216 | unsigned vector = ~regs->orig_ax; | |
217 | unsigned irq; | |
218 | ||
6af7faf6 | 219 | entering_irq(); |
7c1d7cdc | 220 | |
0a3aee0d | 221 | irq = __this_cpu_read(vector_irq[vector]); |
7c1d7cdc JF |
222 | |
223 | if (!handle_irq(irq, regs)) { | |
08306ce6 | 224 | ack_APIC_irq(); |
7c1d7cdc | 225 | |
9345005f PB |
226 | if (irq != VECTOR_RETRIGGERED) { |
227 | pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n", | |
228 | __func__, smp_processor_id(), | |
229 | vector, irq); | |
230 | } else { | |
7276c6a2 | 231 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
9345005f | 232 | } |
7c1d7cdc JF |
233 | } |
234 | ||
6af7faf6 | 235 | exiting_irq(); |
7c1d7cdc JF |
236 | |
237 | set_irq_regs(old_regs); | |
238 | return 1; | |
239 | } | |
240 | ||
acaabe79 | 241 | /* |
4a4de9c7 | 242 | * Handler for X86_PLATFORM_IPI_VECTOR. |
acaabe79 | 243 | */ |
eddc0e92 | 244 | void __smp_x86_platform_ipi(void) |
acaabe79 | 245 | { |
4a4de9c7 | 246 | inc_irq_stat(x86_platform_ipis); |
acaabe79 | 247 | |
4a4de9c7 DS |
248 | if (x86_platform_ipi_callback) |
249 | x86_platform_ipi_callback(); | |
eddc0e92 | 250 | } |
acaabe79 | 251 | |
1d9090e2 | 252 | __visible void smp_x86_platform_ipi(struct pt_regs *regs) |
eddc0e92 SA |
253 | { |
254 | struct pt_regs *old_regs = set_irq_regs(regs); | |
acaabe79 | 255 | |
eddc0e92 SA |
256 | entering_ack_irq(); |
257 | __smp_x86_platform_ipi(); | |
258 | exiting_irq(); | |
acaabe79 DS |
259 | set_irq_regs(old_regs); |
260 | } | |
261 | ||
d78f2664 | 262 | #ifdef CONFIG_HAVE_KVM |
f6b3c72c FW |
263 | static void dummy_handler(void) {} |
264 | static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler; | |
265 | ||
266 | void kvm_set_posted_intr_wakeup_handler(void (*handler)(void)) | |
267 | { | |
268 | if (handler) | |
269 | kvm_posted_intr_wakeup_handler = handler; | |
270 | else | |
271 | kvm_posted_intr_wakeup_handler = dummy_handler; | |
272 | } | |
273 | EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler); | |
274 | ||
d78f2664 YZ |
275 | /* |
276 | * Handler for POSTED_INTERRUPT_VECTOR. | |
277 | */ | |
1d9090e2 | 278 | __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs) |
d78f2664 YZ |
279 | { |
280 | struct pt_regs *old_regs = set_irq_regs(regs); | |
281 | ||
6af7faf6 | 282 | entering_ack_irq(); |
d78f2664 | 283 | inc_irq_stat(kvm_posted_intr_ipis); |
f6b3c72c FW |
284 | exiting_irq(); |
285 | set_irq_regs(old_regs); | |
286 | } | |
287 | ||
288 | /* | |
289 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
290 | */ | |
291 | __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs) | |
292 | { | |
293 | struct pt_regs *old_regs = set_irq_regs(regs); | |
294 | ||
295 | entering_ack_irq(); | |
296 | inc_irq_stat(kvm_posted_intr_wakeup_ipis); | |
297 | kvm_posted_intr_wakeup_handler(); | |
6af7faf6 | 298 | exiting_irq(); |
d78f2664 YZ |
299 | set_irq_regs(old_regs); |
300 | } | |
301 | #endif | |
302 | ||
1d9090e2 | 303 | __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs) |
cf910e83 SA |
304 | { |
305 | struct pt_regs *old_regs = set_irq_regs(regs); | |
306 | ||
307 | entering_ack_irq(); | |
308 | trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR); | |
309 | __smp_x86_platform_ipi(); | |
310 | trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR); | |
311 | exiting_irq(); | |
312 | set_irq_regs(old_regs); | |
313 | } | |
314 | ||
c3d80000 | 315 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |
7a7732bc SS |
316 | |
317 | #ifdef CONFIG_HOTPLUG_CPU | |
39424e89 PB |
318 | |
319 | /* These two declarations are only used in check_irq_vectors_for_cpu_disable() | |
320 | * below, which is protected by stop_machine(). Putting them on the stack | |
321 | * results in a stack frame overflow. Dynamically allocating could result in a | |
322 | * failure so declare these two cpumasks as global. | |
323 | */ | |
324 | static struct cpumask affinity_new, online_new; | |
325 | ||
da6139e4 PB |
326 | /* |
327 | * This cpu is going to be removed and its vectors migrated to the remaining | |
328 | * online cpus. Check to see if there are enough vectors in the remaining cpus. | |
329 | * This function is protected by stop_machine(). | |
330 | */ | |
331 | int check_irq_vectors_for_cpu_disable(void) | |
332 | { | |
333 | int irq, cpu; | |
334 | unsigned int this_cpu, vector, this_count, count; | |
335 | struct irq_desc *desc; | |
336 | struct irq_data *data; | |
da6139e4 PB |
337 | |
338 | this_cpu = smp_processor_id(); | |
339 | cpumask_copy(&online_new, cpu_online_mask); | |
020b37ac | 340 | cpumask_clear_cpu(this_cpu, &online_new); |
da6139e4 PB |
341 | |
342 | this_count = 0; | |
343 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
344 | irq = __this_cpu_read(vector_irq[vector]); | |
44825757 TG |
345 | if (irq < 0) |
346 | continue; | |
347 | desc = irq_to_desc(irq); | |
348 | if (!desc) | |
349 | continue; | |
350 | ||
351 | /* | |
352 | * Protect against concurrent action removal, affinity | |
353 | * changes etc. | |
354 | */ | |
355 | raw_spin_lock(&desc->lock); | |
356 | data = irq_desc_get_irq_data(desc); | |
357 | cpumask_copy(&affinity_new, irq_data_get_affinity_mask(data)); | |
358 | cpumask_clear_cpu(this_cpu, &affinity_new); | |
da6139e4 | 359 | |
44825757 TG |
360 | /* Do not count inactive or per-cpu irqs. */ |
361 | if (!irq_has_action(irq) || irqd_is_per_cpu(data)) { | |
cbb24dc7 | 362 | raw_spin_unlock(&desc->lock); |
44825757 | 363 | continue; |
da6139e4 | 364 | } |
44825757 TG |
365 | |
366 | raw_spin_unlock(&desc->lock); | |
367 | /* | |
368 | * A single irq may be mapped to multiple cpu's | |
369 | * vector_irq[] (for example IOAPIC cluster mode). In | |
370 | * this case we have two possibilities: | |
371 | * | |
372 | * 1) the resulting affinity mask is empty; that is | |
373 | * this the down'd cpu is the last cpu in the irq's | |
374 | * affinity mask, or | |
375 | * | |
376 | * 2) the resulting affinity mask is no longer a | |
377 | * subset of the online cpus but the affinity mask is | |
378 | * not zero; that is the down'd cpu is the last online | |
379 | * cpu in a user set affinity mask. | |
380 | */ | |
381 | if (cpumask_empty(&affinity_new) || | |
382 | !cpumask_subset(&affinity_new, &online_new)) | |
383 | this_count++; | |
da6139e4 PB |
384 | } |
385 | ||
386 | count = 0; | |
387 | for_each_online_cpu(cpu) { | |
388 | if (cpu == this_cpu) | |
389 | continue; | |
ac2a5539 YL |
390 | /* |
391 | * We scan from FIRST_EXTERNAL_VECTOR to first system | |
392 | * vector. If the vector is marked in the used vectors | |
393 | * bitmap or an irq is assigned to it, we don't count | |
394 | * it as available. | |
cbb24dc7 TG |
395 | * |
396 | * As this is an inaccurate snapshot anyway, we can do | |
397 | * this w/o holding vector_lock. | |
ac2a5539 YL |
398 | */ |
399 | for (vector = FIRST_EXTERNAL_VECTOR; | |
400 | vector < first_system_vector; vector++) { | |
401 | if (!test_bit(vector, used_vectors) && | |
7276c6a2 | 402 | per_cpu(vector_irq, cpu)[vector] <= VECTOR_UNUSED) |
24c70e07 | 403 | count++; |
da6139e4 PB |
404 | } |
405 | } | |
406 | ||
407 | if (count < this_count) { | |
408 | pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n", | |
409 | this_cpu, this_count, count); | |
410 | return -ERANGE; | |
411 | } | |
412 | return 0; | |
413 | } | |
414 | ||
7a7732bc SS |
415 | /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ |
416 | void fixup_irqs(void) | |
417 | { | |
5231a686 | 418 | unsigned int irq, vector; |
7a7732bc SS |
419 | static int warned; |
420 | struct irq_desc *desc; | |
a3c08e5d | 421 | struct irq_data *data; |
51c43ac6 | 422 | struct irq_chip *chip; |
fb24da80 | 423 | int ret; |
7a7732bc SS |
424 | |
425 | for_each_irq_desc(irq, desc) { | |
426 | int break_affinity = 0; | |
427 | int set_affinity = 1; | |
428 | const struct cpumask *affinity; | |
429 | ||
430 | if (!desc) | |
431 | continue; | |
432 | if (irq == 2) | |
433 | continue; | |
434 | ||
435 | /* interrupt's are disabled at this point */ | |
239007b8 | 436 | raw_spin_lock(&desc->lock); |
7a7732bc | 437 | |
51c43ac6 | 438 | data = irq_desc_get_irq_data(desc); |
c149e4cd | 439 | affinity = irq_data_get_affinity_mask(data); |
b87ba87c | 440 | if (!irq_has_action(irq) || irqd_is_per_cpu(data) || |
58bff947 | 441 | cpumask_subset(affinity, cpu_online_mask)) { |
239007b8 | 442 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
443 | continue; |
444 | } | |
445 | ||
a5e74b84 SS |
446 | /* |
447 | * Complete the irq move. This cpu is going down and for | |
448 | * non intr-remapping case, we can't wait till this interrupt | |
449 | * arrives at this cpu before completing the irq move. | |
450 | */ | |
451 | irq_force_complete_move(irq); | |
452 | ||
7a7732bc SS |
453 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
454 | break_affinity = 1; | |
2530cd4f | 455 | affinity = cpu_online_mask; |
7a7732bc SS |
456 | } |
457 | ||
51c43ac6 TG |
458 | chip = irq_data_get_irq_chip(data); |
459 | if (!irqd_can_move_in_process_context(data) && chip->irq_mask) | |
460 | chip->irq_mask(data); | |
7a7732bc | 461 | |
fb24da80 PB |
462 | if (chip->irq_set_affinity) { |
463 | ret = chip->irq_set_affinity(data, affinity, true); | |
464 | if (ret == -ENOSPC) | |
465 | pr_crit("IRQ %d set affinity failed because there are no available vectors. The device assigned to this IRQ is unstable.\n", irq); | |
466 | } else { | |
467 | if (!(warned++)) | |
468 | set_affinity = 0; | |
469 | } | |
7a7732bc | 470 | |
99dd5497 LC |
471 | /* |
472 | * We unmask if the irq was not marked masked by the | |
473 | * core code. That respects the lazy irq disable | |
474 | * behaviour. | |
475 | */ | |
983bbf1a | 476 | if (!irqd_can_move_in_process_context(data) && |
99dd5497 | 477 | !irqd_irq_masked(data) && chip->irq_unmask) |
51c43ac6 | 478 | chip->irq_unmask(data); |
7a7732bc | 479 | |
239007b8 | 480 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
481 | |
482 | if (break_affinity && set_affinity) | |
c767a54b | 483 | pr_notice("Broke affinity for irq %i\n", irq); |
7a7732bc | 484 | else if (!set_affinity) |
c767a54b | 485 | pr_notice("Cannot set affinity for irq %i\n", irq); |
7a7732bc SS |
486 | } |
487 | ||
5231a686 SS |
488 | /* |
489 | * We can remove mdelay() and then send spuriuous interrupts to | |
490 | * new cpu targets for all the irqs that were handled previously by | |
491 | * this cpu. While it works, I have seen spurious interrupt messages | |
492 | * (nothing wrong but still...). | |
493 | * | |
494 | * So for now, retain mdelay(1) and check the IRR and then send those | |
495 | * interrupts to new targets as this cpu is already offlined... | |
496 | */ | |
7a7732bc | 497 | mdelay(1); |
5231a686 | 498 | |
09cf92b7 TG |
499 | /* |
500 | * We can walk the vector array of this cpu without holding | |
501 | * vector_lock because the cpu is already marked !online, so | |
502 | * nothing else will touch it. | |
503 | */ | |
5231a686 SS |
504 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
505 | unsigned int irr; | |
506 | ||
7276c6a2 | 507 | if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNUSED) |
5231a686 SS |
508 | continue; |
509 | ||
510 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
511 | if (irr & (1 << (vector % 32))) { | |
0a3aee0d | 512 | irq = __this_cpu_read(vector_irq[vector]); |
5231a686 | 513 | |
5117348d | 514 | desc = irq_to_desc(irq); |
09cf92b7 | 515 | raw_spin_lock(&desc->lock); |
51c43ac6 TG |
516 | data = irq_desc_get_irq_data(desc); |
517 | chip = irq_data_get_irq_chip(data); | |
9345005f | 518 | if (chip->irq_retrigger) { |
51c43ac6 | 519 | chip->irq_retrigger(data); |
9345005f PB |
520 | __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED); |
521 | } | |
239007b8 | 522 | raw_spin_unlock(&desc->lock); |
5231a686 | 523 | } |
9345005f | 524 | if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED) |
7276c6a2 | 525 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
5231a686 | 526 | } |
7a7732bc SS |
527 | } |
528 | #endif |