Commit | Line | Data |
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1da177e4 | 1 | #include <linux/linkage.h> |
1da177e4 LT |
2 | #include <linux/errno.h> |
3 | #include <linux/signal.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/ioport.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/timex.h> | |
8 | #include <linux/slab.h> | |
9 | #include <linux/random.h> | |
1da177e4 LT |
10 | #include <linux/init.h> |
11 | #include <linux/kernel_stat.h> | |
12 | #include <linux/sysdev.h> | |
13 | #include <linux/bitops.h> | |
14 | ||
15 | #include <asm/acpi.h> | |
16 | #include <asm/atomic.h> | |
17 | #include <asm/system.h> | |
18 | #include <asm/io.h> | |
1da177e4 LT |
19 | #include <asm/hw_irq.h> |
20 | #include <asm/pgtable.h> | |
21 | #include <asm/delay.h> | |
22 | #include <asm/desc.h> | |
23 | #include <asm/apic.h> | |
2b8e05b5 | 24 | #include <asm/i8259.h> |
1da177e4 | 25 | |
1da177e4 LT |
26 | /* |
27 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | |
c97beb47 | 28 | * (these are usually mapped to vectors 0x30-0x3f) |
1da177e4 | 29 | */ |
1da177e4 | 30 | |
1da177e4 | 31 | /* |
2b8e05b5 | 32 | * The IO-APIC gives us many more interrupt sources. Most of these |
1da177e4 LT |
33 | * are unused but an SMP system is supposed to have enough memory ... |
34 | * sometimes (mostly wrt. hw bugs) we get corrupted vectors all | |
35 | * across the spectrum, so we really want to be prepared to get all | |
36 | * of these. Plus, more powerful systems might have more than 64 | |
37 | * IO-APIC registers. | |
38 | * | |
39 | * (these are usually mapped into the 0x30-0xff vector range) | |
40 | */ | |
2b8e05b5 | 41 | |
1da177e4 LT |
42 | /* |
43 | * IRQ2 is cascade interrupt to second interrupt controller | |
44 | */ | |
45 | ||
df5ddf62 TG |
46 | static struct irqaction irq2 = { |
47 | .handler = no_action, | |
48 | .mask = CPU_MASK_NONE, | |
49 | .name = "cascade", | |
50 | }; | |
550f2299 | 51 | DEFINE_PER_CPU(vector_irq_t, vector_irq) = { |
bc5e81a1 EB |
52 | [0 ... IRQ0_VECTOR - 1] = -1, |
53 | [IRQ0_VECTOR] = 0, | |
54 | [IRQ1_VECTOR] = 1, | |
55 | [IRQ2_VECTOR] = 2, | |
56 | [IRQ3_VECTOR] = 3, | |
57 | [IRQ4_VECTOR] = 4, | |
58 | [IRQ5_VECTOR] = 5, | |
59 | [IRQ6_VECTOR] = 6, | |
60 | [IRQ7_VECTOR] = 7, | |
61 | [IRQ8_VECTOR] = 8, | |
62 | [IRQ9_VECTOR] = 9, | |
63 | [IRQ10_VECTOR] = 10, | |
64 | [IRQ11_VECTOR] = 11, | |
65 | [IRQ12_VECTOR] = 12, | |
66 | [IRQ13_VECTOR] = 13, | |
67 | [IRQ14_VECTOR] = 14, | |
68 | [IRQ15_VECTOR] = 15, | |
69 | [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1 | |
e500f574 | 70 | }; |
1da177e4 | 71 | |
b77b881f YL |
72 | int vector_used_by_percpu_irq(unsigned int vector) |
73 | { | |
74 | int cpu; | |
75 | ||
76 | for_each_online_cpu(cpu) { | |
77 | if (per_cpu(vector_irq, cpu)[vector] != -1) | |
78 | return 1; | |
79 | } | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
780209af | 84 | void __init init_ISA_irqs(void) |
1da177e4 LT |
85 | { |
86 | int i; | |
87 | ||
1da177e4 | 88 | init_bsp_APIC(); |
1da177e4 LT |
89 | init_8259A(0); |
90 | ||
99d093d1 | 91 | for (i = 0; i < NR_IRQS_LEGACY; i++) { |
ee32c973 | 92 | struct irq_desc *desc = irq_to_desc(i); |
08678b08 YL |
93 | |
94 | desc->status = IRQ_DISABLED; | |
95 | desc->action = NULL; | |
96 | desc->depth = 1; | |
1da177e4 | 97 | |
2c6927a3 YL |
98 | /* |
99 | * 16 old-style INTA-cycle interrupts: | |
100 | */ | |
101 | set_irq_chip_and_handler_name(i, &i8259A_chip, | |
a460e745 | 102 | handle_level_irq, "XT"); |
1da177e4 LT |
103 | } |
104 | } | |
105 | ||
b0387830 GOC |
106 | void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); |
107 | ||
9b658f6f | 108 | static void __init smp_intr_init(void) |
1da177e4 | 109 | { |
1da177e4 | 110 | #ifdef CONFIG_SMP |
1da177e4 LT |
111 | /* |
112 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
113 | * IPI, driven by wakeup. | |
114 | */ | |
305b92a2 | 115 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); |
1da177e4 | 116 | |
e5bc8b6b | 117 | /* IPIs for invalidation */ |
305b92a2 AM |
118 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); |
119 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); | |
120 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); | |
121 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); | |
122 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); | |
123 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); | |
124 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); | |
125 | alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); | |
1da177e4 LT |
126 | |
127 | /* IPI for generic function call */ | |
305b92a2 | 128 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); |
61014292 | 129 | |
1a781a77 IM |
130 | /* IPI for generic single function call */ |
131 | alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, | |
132 | call_function_single_interrupt); | |
133 | ||
61014292 EB |
134 | /* Low priority IPI to cleanup after moving an irq */ |
135 | set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt); | |
b77b881f | 136 | set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors); |
61014292 | 137 | #endif |
2f97435e GC |
138 | } |
139 | ||
9b658f6f | 140 | static void __init apic_intr_init(void) |
2f97435e | 141 | { |
2f97435e | 142 | smp_intr_init(); |
2f97435e | 143 | |
305b92a2 AM |
144 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
145 | alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); | |
1da177e4 | 146 | |
1da177e4 | 147 | /* self generated IPI for local APIC timer */ |
305b92a2 | 148 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
1da177e4 LT |
149 | |
150 | /* IPI vectors for APIC spurious and error interrupts */ | |
305b92a2 AM |
151 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
152 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
2f97435e GC |
153 | } |
154 | ||
155 | void __init native_init_IRQ(void) | |
156 | { | |
157 | int i; | |
158 | ||
159 | init_ISA_irqs(); | |
160 | /* | |
161 | * Cover the whole vector space, no vector can escape | |
162 | * us. (some of these will be overridden and become | |
163 | * 'special' SMP interrupts) | |
164 | */ | |
165 | for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) { | |
166 | int vector = FIRST_EXTERNAL_VECTOR + i; | |
167 | if (vector != IA32_SYSCALL_VECTOR) | |
168 | set_intr_gate(vector, interrupt[i]); | |
169 | } | |
170 | ||
171 | apic_intr_init(); | |
1da177e4 | 172 | |
1da177e4 LT |
173 | if (!acpi_ioapic) |
174 | setup_irq(2, &irq2); | |
175 | } |