Commit | Line | Data |
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83d7384f AS |
1 | /* |
2 | * Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT) | |
3 | * | |
4 | * Copyright (C) 2006, Advanced Micro Devices, Inc. | |
5 | * Copyright (C) 2007, Andres Salomon <dilinger@debian.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of version 2 of the GNU General Public License | |
9 | * as published by the Free Software Foundation. | |
10 | * | |
11 | * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. | |
12 | */ | |
13 | ||
14 | /* | |
36445cf3 | 15 | * We are using the 32.768kHz input clock - it's the only one that has the |
83d7384f | 16 | * ranges we find desirable. The following table lists the suitable |
36445cf3 | 17 | * divisors and the associated Hz, minimum interval and the maximum interval: |
83d7384f | 18 | * |
36445cf3 WT |
19 | * Divisor Hz Min Delta (s) Max Delta (s) |
20 | * 1 32768 .00048828125 2.000 | |
21 | * 2 16384 .0009765625 4.000 | |
22 | * 4 8192 .001953125 8.000 | |
23 | * 8 4096 .00390625 16.000 | |
24 | * 16 2048 .0078125 32.000 | |
25 | * 32 1024 .015625 64.000 | |
26 | * 64 512 .03125 128.000 | |
27 | * 128 256 .0625 256.000 | |
28 | * 256 128 .125 512.000 | |
83d7384f AS |
29 | */ |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/interrupt.h> | |
923a0cf8 | 33 | #include <linux/module.h> |
83d7384f AS |
34 | #include <asm/geode.h> |
35 | ||
0d5cdc97 JR |
36 | #define MFGPT_DEFAULT_IRQ 7 |
37 | ||
83d7384f | 38 | static struct mfgpt_timer_t { |
9501b2ef | 39 | unsigned int avail:1; |
83d7384f AS |
40 | } mfgpt_timers[MFGPT_MAX_TIMERS]; |
41 | ||
42 | /* Selected from the table above */ | |
43 | ||
44 | #define MFGPT_DIVISOR 16 | |
45 | #define MFGPT_SCALE 4 /* divisor = 2^(scale) */ | |
36445cf3 | 46 | #define MFGPT_HZ (32768 / MFGPT_DIVISOR) |
83d7384f AS |
47 | #define MFGPT_PERIODIC (MFGPT_HZ / HZ) |
48 | ||
49 | /* Allow for disabling of MFGPTs */ | |
50 | static int disable; | |
51 | static int __init mfgpt_disable(char *s) | |
52 | { | |
53 | disable = 1; | |
54 | return 1; | |
55 | } | |
56 | __setup("nomfgpt", mfgpt_disable); | |
57 | ||
e6c4dc6c WT |
58 | /* Reset the MFGPT timers. This is required by some broken BIOSes which already |
59 | * do the same and leave the system in an unstable state. TinyBIOS 0.98 is | |
60 | * affected at least (0.99 is OK with MFGPT workaround left to off). | |
61 | */ | |
62 | static int __init mfgpt_fix(char *s) | |
63 | { | |
64 | u32 val, dummy; | |
65 | ||
66 | /* The following udocumented bit resets the MFGPT timers */ | |
67 | val = 0xFF; dummy = 0; | |
32bf87e3 | 68 | wrmsr(MSR_MFGPT_SETUP, val, dummy); |
e6c4dc6c WT |
69 | return 1; |
70 | } | |
71 | __setup("mfgptfix", mfgpt_fix); | |
72 | ||
83d7384f AS |
73 | /* |
74 | * Check whether any MFGPTs are available for the kernel to use. In most | |
75 | * cases, firmware that uses AMD's VSA code will claim all timers during | |
76 | * bootup; we certainly don't want to take them if they're already in use. | |
77 | * In other cases (such as with VSAless OpenFirmware), the system firmware | |
78 | * leaves timers available for us to use. | |
79 | */ | |
f087515c JC |
80 | |
81 | ||
82 | static int timers = -1; | |
83 | ||
84 | static void geode_mfgpt_detect(void) | |
83d7384f | 85 | { |
f087515c | 86 | int i; |
83d7384f AS |
87 | u16 val; |
88 | ||
f087515c JC |
89 | timers = 0; |
90 | ||
83d7384f | 91 | if (disable) { |
f087515c JC |
92 | printk(KERN_INFO "geode-mfgpt: MFGPT support is disabled\n"); |
93 | goto done; | |
94 | } | |
95 | ||
96 | if (!geode_get_dev_base(GEODE_DEV_MFGPT)) { | |
97 | printk(KERN_INFO "geode-mfgpt: MFGPT LBAR is not set up\n"); | |
98 | goto done; | |
83d7384f AS |
99 | } |
100 | ||
101 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
102 | val = geode_mfgpt_read(i, MFGPT_REG_SETUP); | |
103 | if (!(val & MFGPT_SETUP_SETUP)) { | |
9501b2ef | 104 | mfgpt_timers[i].avail = 1; |
f087515c | 105 | timers++; |
83d7384f AS |
106 | } |
107 | } | |
108 | ||
f087515c JC |
109 | done: |
110 | printk(KERN_INFO "geode-mfgpt: %d MFGPT timers available.\n", timers); | |
83d7384f AS |
111 | } |
112 | ||
113 | int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable) | |
114 | { | |
115 | u32 msr, mask, value, dummy; | |
116 | int shift = (cmp == MFGPT_CMP1) ? 0 : 8; | |
117 | ||
118 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
119 | return -EIO; | |
120 | ||
121 | /* | |
122 | * The register maps for these are described in sections 6.17.1.x of | |
123 | * the AMD Geode CS5536 Companion Device Data Book. | |
124 | */ | |
125 | switch (event) { | |
126 | case MFGPT_EVENT_RESET: | |
127 | /* | |
128 | * XXX: According to the docs, we cannot reset timers above | |
129 | * 6; that is, resets for 7 and 8 will be ignored. Is this | |
130 | * a problem? -dilinger | |
131 | */ | |
32bf87e3 | 132 | msr = MSR_MFGPT_NR; |
83d7384f AS |
133 | mask = 1 << (timer + 24); |
134 | break; | |
135 | ||
136 | case MFGPT_EVENT_NMI: | |
32bf87e3 | 137 | msr = MSR_MFGPT_NR; |
83d7384f AS |
138 | mask = 1 << (timer + shift); |
139 | break; | |
140 | ||
141 | case MFGPT_EVENT_IRQ: | |
32bf87e3 | 142 | msr = MSR_MFGPT_IRQ; |
83d7384f AS |
143 | mask = 1 << (timer + shift); |
144 | break; | |
145 | ||
146 | default: | |
147 | return -EIO; | |
148 | } | |
149 | ||
150 | rdmsr(msr, value, dummy); | |
151 | ||
152 | if (enable) | |
153 | value |= mask; | |
154 | else | |
155 | value &= ~mask; | |
156 | ||
157 | wrmsr(msr, value, dummy); | |
158 | return 0; | |
159 | } | |
3703f399 | 160 | EXPORT_SYMBOL_GPL(geode_mfgpt_toggle_event); |
83d7384f | 161 | |
0d5cdc97 | 162 | int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable) |
83d7384f | 163 | { |
0d5cdc97 JR |
164 | u32 zsel, lpc, dummy; |
165 | int shift; | |
83d7384f AS |
166 | |
167 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
168 | return -EIO; | |
169 | ||
0d5cdc97 JR |
170 | /* |
171 | * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA | |
172 | * is using the same CMP of the timer's Siamese twin, the IRQ is set to | |
173 | * 2, and we mustn't use nor change it. | |
174 | * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the | |
175 | * IRQ of the 1st. This can only happen if forcing an IRQ, calling this | |
176 | * with *irq==0 is safe. Currently there _are_ no 2 drivers. | |
177 | */ | |
178 | rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); | |
179 | shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer % 4) * 4; | |
180 | if (((zsel >> shift) & 0xF) == 2) | |
83d7384f AS |
181 | return -EIO; |
182 | ||
0d5cdc97 JR |
183 | /* Choose IRQ: if none supplied, keep IRQ already set or use default */ |
184 | if (!*irq) | |
185 | *irq = (zsel >> shift) & 0xF; | |
186 | if (!*irq) | |
187 | *irq = MFGPT_DEFAULT_IRQ; | |
83d7384f | 188 | |
0d5cdc97 JR |
189 | /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */ |
190 | if (*irq < 1 || *irq == 2 || *irq > 15) | |
191 | return -EIO; | |
192 | rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy); | |
193 | if (lpc & (1 << *irq)) | |
194 | return -EIO; | |
83d7384f | 195 | |
0d5cdc97 JR |
196 | /* All chosen and checked - go for it */ |
197 | if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) | |
198 | return -EIO; | |
83d7384f | 199 | if (enable) { |
0d5cdc97 JR |
200 | zsel = (zsel & ~(0xF << shift)) | (*irq << shift); |
201 | wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); | |
83d7384f AS |
202 | } |
203 | ||
83d7384f AS |
204 | return 0; |
205 | } | |
206 | ||
fa28e067 | 207 | static int mfgpt_get(int timer) |
83d7384f | 208 | { |
9501b2ef | 209 | mfgpt_timers[timer].avail = 0; |
83d7384f AS |
210 | printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer); |
211 | return timer; | |
212 | } | |
213 | ||
fa28e067 | 214 | int geode_mfgpt_alloc_timer(int timer, int domain) |
83d7384f AS |
215 | { |
216 | int i; | |
217 | ||
f087515c JC |
218 | if (timers == -1) { |
219 | /* timers haven't been detected yet */ | |
220 | geode_mfgpt_detect(); | |
221 | } | |
222 | ||
223 | if (!timers) | |
224 | return -1; | |
225 | ||
83d7384f | 226 | if (timer >= MFGPT_MAX_TIMERS) |
f087515c | 227 | return -1; |
83d7384f AS |
228 | |
229 | if (timer < 0) { | |
230 | /* Try to find an available timer */ | |
231 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
9501b2ef | 232 | if (mfgpt_timers[i].avail) |
fa28e067 | 233 | return mfgpt_get(i); |
83d7384f AS |
234 | |
235 | if (i == 5 && domain == MFGPT_DOMAIN_WORKING) | |
236 | break; | |
237 | } | |
238 | } else { | |
239 | /* If they requested a specific timer, try to honor that */ | |
9501b2ef | 240 | if (mfgpt_timers[timer].avail) |
fa28e067 | 241 | return mfgpt_get(timer); |
83d7384f AS |
242 | } |
243 | ||
244 | /* No timers available - too bad */ | |
245 | return -1; | |
246 | } | |
3703f399 | 247 | EXPORT_SYMBOL_GPL(geode_mfgpt_alloc_timer); |
83d7384f | 248 | |
8f36881b AS |
249 | |
250 | #ifdef CONFIG_GEODE_MFGPT_TIMER | |
251 | ||
252 | /* | |
253 | * The MFPGT timers on the CS5536 provide us with suitable timers to use | |
254 | * as clock event sources - not as good as a HPET or APIC, but certainly | |
025dfdaf | 255 | * better than the PIT. This isn't a general purpose MFGPT driver, but |
8f36881b AS |
256 | * a simplified one designed specifically to act as a clock event source. |
257 | * For full details about the MFGPT, please consult the CS5536 data sheet. | |
258 | */ | |
259 | ||
260 | #include <linux/clocksource.h> | |
261 | #include <linux/clockchips.h> | |
262 | ||
263 | static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN; | |
264 | static u16 mfgpt_event_clock; | |
265 | ||
0d5cdc97 | 266 | static int irq; |
8f36881b AS |
267 | static int __init mfgpt_setup(char *str) |
268 | { | |
269 | get_option(&str, &irq); | |
270 | return 1; | |
271 | } | |
272 | __setup("mfgpt_irq=", mfgpt_setup); | |
273 | ||
e78a77c3 | 274 | static void mfgpt_disable_timer(u16 clock) |
8f36881b | 275 | { |
f54ae69b AS |
276 | /* avoid races by clearing CMP1 and CMP2 unconditionally */ |
277 | geode_mfgpt_write(clock, MFGPT_REG_SETUP, (u16) ~MFGPT_SETUP_CNTEN | | |
278 | MFGPT_SETUP_CMP1 | MFGPT_SETUP_CMP2); | |
8f36881b AS |
279 | } |
280 | ||
281 | static int mfgpt_next_event(unsigned long, struct clock_event_device *); | |
282 | static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *); | |
283 | ||
284 | static struct clock_event_device mfgpt_clockevent = { | |
285 | .name = "mfgpt-timer", | |
286 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
287 | .set_mode = mfgpt_set_mode, | |
288 | .set_next_event = mfgpt_next_event, | |
289 | .rating = 250, | |
320ab2b0 | 290 | .cpumask = cpu_all_mask, |
8f36881b AS |
291 | .shift = 32 |
292 | }; | |
293 | ||
e78a77c3 | 294 | static void mfgpt_start_timer(u16 delta) |
8f36881b AS |
295 | { |
296 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta); | |
297 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
298 | ||
299 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
300 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
301 | } | |
302 | ||
303 | static void mfgpt_set_mode(enum clock_event_mode mode, | |
304 | struct clock_event_device *evt) | |
305 | { | |
306 | mfgpt_disable_timer(mfgpt_event_clock); | |
307 | ||
308 | if (mode == CLOCK_EVT_MODE_PERIODIC) | |
e78a77c3 | 309 | mfgpt_start_timer(MFGPT_PERIODIC); |
8f36881b AS |
310 | |
311 | mfgpt_tick_mode = mode; | |
312 | } | |
313 | ||
314 | static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) | |
315 | { | |
e78a77c3 | 316 | mfgpt_start_timer(delta); |
8f36881b AS |
317 | return 0; |
318 | } | |
319 | ||
8f36881b AS |
320 | static irqreturn_t mfgpt_tick(int irq, void *dev_id) |
321 | { | |
dcee77be JC |
322 | u16 val = geode_mfgpt_read(mfgpt_event_clock, MFGPT_REG_SETUP); |
323 | ||
324 | /* See if the interrupt was for us */ | |
325 | if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1))) | |
326 | return IRQ_NONE; | |
327 | ||
667984d9 JC |
328 | /* Turn off the clock (and clear the event) */ |
329 | mfgpt_disable_timer(mfgpt_event_clock); | |
330 | ||
8f36881b AS |
331 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN) |
332 | return IRQ_HANDLED; | |
333 | ||
8f36881b AS |
334 | /* Clear the counter */ |
335 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
336 | ||
337 | /* Restart the clock in periodic mode */ | |
338 | ||
339 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) { | |
340 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
341 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
342 | } | |
343 | ||
344 | mfgpt_clockevent.event_handler(&mfgpt_clockevent); | |
345 | return IRQ_HANDLED; | |
346 | } | |
347 | ||
348 | static struct irqaction mfgptirq = { | |
349 | .handler = mfgpt_tick, | |
350 | .flags = IRQF_DISABLED | IRQF_NOBALANCING, | |
8f36881b AS |
351 | .name = "mfgpt-timer" |
352 | }; | |
353 | ||
b0e6bf25 | 354 | int __init mfgpt_timer_setup(void) |
8f36881b AS |
355 | { |
356 | int timer, ret; | |
357 | u16 val; | |
358 | ||
fa28e067 | 359 | timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING); |
8f36881b AS |
360 | if (timer < 0) { |
361 | printk(KERN_ERR | |
362 | "mfgpt-timer: Could not allocate a MFPGT timer\n"); | |
363 | return -ENODEV; | |
364 | } | |
365 | ||
366 | mfgpt_event_clock = timer; | |
8f36881b AS |
367 | |
368 | /* Set up the IRQ on the MFGPT side */ | |
0d5cdc97 | 369 | if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, &irq)) { |
8f36881b AS |
370 | printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq); |
371 | return -EIO; | |
372 | } | |
373 | ||
374 | /* And register it with the kernel */ | |
375 | ret = setup_irq(irq, &mfgptirq); | |
376 | ||
377 | if (ret) { | |
378 | printk(KERN_ERR | |
379 | "mfgpt-timer: Unable to set up the interrupt.\n"); | |
380 | goto err; | |
381 | } | |
382 | ||
667984d9 JC |
383 | /* Set the clock scale and enable the event mode for CMP2 */ |
384 | val = MFGPT_SCALE | (3 << 8); | |
385 | ||
386 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val); | |
387 | ||
8f36881b | 388 | /* Set up the clock event */ |
877084fb AM |
389 | mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, |
390 | mfgpt_clockevent.shift); | |
8f36881b AS |
391 | mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, |
392 | &mfgpt_clockevent); | |
393 | mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, | |
394 | &mfgpt_clockevent); | |
395 | ||
396 | printk(KERN_INFO | |
0d5cdc97 JR |
397 | "mfgpt-timer: Registering MFGPT timer %d as a clock event, using IRQ %d\n", |
398 | timer, irq); | |
8f36881b AS |
399 | clockevents_register_device(&mfgpt_clockevent); |
400 | ||
401 | return 0; | |
402 | ||
403 | err: | |
0d5cdc97 | 404 | geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, &irq); |
8f36881b AS |
405 | printk(KERN_ERR |
406 | "mfgpt-timer: Unable to set up the MFGPT clock source\n"); | |
407 | return -EIO; | |
408 | } | |
409 | ||
410 | #endif |