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83d7384f AS |
1 | /* |
2 | * Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT) | |
3 | * | |
4 | * Copyright (C) 2006, Advanced Micro Devices, Inc. | |
5 | * Copyright (C) 2007, Andres Salomon <dilinger@debian.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of version 2 of the GNU General Public License | |
9 | * as published by the Free Software Foundation. | |
10 | * | |
11 | * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. | |
12 | */ | |
13 | ||
14 | /* | |
36445cf3 | 15 | * We are using the 32.768kHz input clock - it's the only one that has the |
83d7384f | 16 | * ranges we find desirable. The following table lists the suitable |
36445cf3 | 17 | * divisors and the associated Hz, minimum interval and the maximum interval: |
83d7384f | 18 | * |
36445cf3 WT |
19 | * Divisor Hz Min Delta (s) Max Delta (s) |
20 | * 1 32768 .00048828125 2.000 | |
21 | * 2 16384 .0009765625 4.000 | |
22 | * 4 8192 .001953125 8.000 | |
23 | * 8 4096 .00390625 16.000 | |
24 | * 16 2048 .0078125 32.000 | |
25 | * 32 1024 .015625 64.000 | |
26 | * 64 512 .03125 128.000 | |
27 | * 128 256 .0625 256.000 | |
28 | * 256 128 .125 512.000 | |
83d7384f AS |
29 | */ |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/interrupt.h> | |
83d7384f AS |
33 | #include <asm/geode.h> |
34 | ||
35 | #define F_AVAIL 0x01 | |
36 | ||
37 | static struct mfgpt_timer_t { | |
38 | int flags; | |
83d7384f AS |
39 | } mfgpt_timers[MFGPT_MAX_TIMERS]; |
40 | ||
41 | /* Selected from the table above */ | |
42 | ||
43 | #define MFGPT_DIVISOR 16 | |
44 | #define MFGPT_SCALE 4 /* divisor = 2^(scale) */ | |
36445cf3 | 45 | #define MFGPT_HZ (32768 / MFGPT_DIVISOR) |
83d7384f AS |
46 | #define MFGPT_PERIODIC (MFGPT_HZ / HZ) |
47 | ||
8f36881b AS |
48 | #ifdef CONFIG_GEODE_MFGPT_TIMER |
49 | static int __init mfgpt_timer_setup(void); | |
50 | #else | |
51 | #define mfgpt_timer_setup() (0) | |
52 | #endif | |
53 | ||
83d7384f AS |
54 | /* Allow for disabling of MFGPTs */ |
55 | static int disable; | |
56 | static int __init mfgpt_disable(char *s) | |
57 | { | |
58 | disable = 1; | |
59 | return 1; | |
60 | } | |
61 | __setup("nomfgpt", mfgpt_disable); | |
62 | ||
e6c4dc6c WT |
63 | /* Reset the MFGPT timers. This is required by some broken BIOSes which already |
64 | * do the same and leave the system in an unstable state. TinyBIOS 0.98 is | |
65 | * affected at least (0.99 is OK with MFGPT workaround left to off). | |
66 | */ | |
67 | static int __init mfgpt_fix(char *s) | |
68 | { | |
69 | u32 val, dummy; | |
70 | ||
71 | /* The following udocumented bit resets the MFGPT timers */ | |
72 | val = 0xFF; dummy = 0; | |
73 | wrmsr(0x5140002B, val, dummy); | |
74 | return 1; | |
75 | } | |
76 | __setup("mfgptfix", mfgpt_fix); | |
77 | ||
83d7384f AS |
78 | /* |
79 | * Check whether any MFGPTs are available for the kernel to use. In most | |
80 | * cases, firmware that uses AMD's VSA code will claim all timers during | |
81 | * bootup; we certainly don't want to take them if they're already in use. | |
82 | * In other cases (such as with VSAless OpenFirmware), the system firmware | |
83 | * leaves timers available for us to use. | |
84 | */ | |
85 | int __init geode_mfgpt_detect(void) | |
86 | { | |
87 | int count = 0, i; | |
88 | u16 val; | |
89 | ||
90 | if (disable) { | |
91 | printk(KERN_INFO "geode-mfgpt: Skipping MFGPT setup\n"); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
96 | val = geode_mfgpt_read(i, MFGPT_REG_SETUP); | |
97 | if (!(val & MFGPT_SETUP_SETUP)) { | |
98 | mfgpt_timers[i].flags = F_AVAIL; | |
99 | count++; | |
100 | } | |
101 | } | |
102 | ||
8f36881b AS |
103 | /* set up clock event device, if desired */ |
104 | i = mfgpt_timer_setup(); | |
105 | ||
83d7384f AS |
106 | return count; |
107 | } | |
108 | ||
109 | int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable) | |
110 | { | |
111 | u32 msr, mask, value, dummy; | |
112 | int shift = (cmp == MFGPT_CMP1) ? 0 : 8; | |
113 | ||
114 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
115 | return -EIO; | |
116 | ||
117 | /* | |
118 | * The register maps for these are described in sections 6.17.1.x of | |
119 | * the AMD Geode CS5536 Companion Device Data Book. | |
120 | */ | |
121 | switch (event) { | |
122 | case MFGPT_EVENT_RESET: | |
123 | /* | |
124 | * XXX: According to the docs, we cannot reset timers above | |
125 | * 6; that is, resets for 7 and 8 will be ignored. Is this | |
126 | * a problem? -dilinger | |
127 | */ | |
128 | msr = MFGPT_NR_MSR; | |
129 | mask = 1 << (timer + 24); | |
130 | break; | |
131 | ||
132 | case MFGPT_EVENT_NMI: | |
133 | msr = MFGPT_NR_MSR; | |
134 | mask = 1 << (timer + shift); | |
135 | break; | |
136 | ||
137 | case MFGPT_EVENT_IRQ: | |
138 | msr = MFGPT_IRQ_MSR; | |
139 | mask = 1 << (timer + shift); | |
140 | break; | |
141 | ||
142 | default: | |
143 | return -EIO; | |
144 | } | |
145 | ||
146 | rdmsr(msr, value, dummy); | |
147 | ||
148 | if (enable) | |
149 | value |= mask; | |
150 | else | |
151 | value &= ~mask; | |
152 | ||
153 | wrmsr(msr, value, dummy); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable) | |
158 | { | |
159 | u32 val, dummy; | |
160 | int offset; | |
161 | ||
162 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
163 | return -EIO; | |
164 | ||
165 | if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) | |
166 | return -EIO; | |
167 | ||
168 | rdmsr(MSR_PIC_ZSEL_LOW, val, dummy); | |
169 | ||
170 | offset = (timer % 4) * 4; | |
171 | ||
172 | val &= ~((0xF << offset) | (0xF << (offset + 16))); | |
173 | ||
174 | if (enable) { | |
175 | val |= (irq & 0x0F) << (offset); | |
176 | val |= (irq & 0x0F) << (offset + 16); | |
177 | } | |
178 | ||
179 | wrmsr(MSR_PIC_ZSEL_LOW, val, dummy); | |
180 | return 0; | |
181 | } | |
182 | ||
fa28e067 | 183 | static int mfgpt_get(int timer) |
83d7384f AS |
184 | { |
185 | mfgpt_timers[timer].flags &= ~F_AVAIL; | |
83d7384f AS |
186 | printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer); |
187 | return timer; | |
188 | } | |
189 | ||
fa28e067 | 190 | int geode_mfgpt_alloc_timer(int timer, int domain) |
83d7384f AS |
191 | { |
192 | int i; | |
193 | ||
194 | if (!geode_get_dev_base(GEODE_DEV_MFGPT)) | |
195 | return -ENODEV; | |
196 | if (timer >= MFGPT_MAX_TIMERS) | |
197 | return -EIO; | |
198 | ||
199 | if (timer < 0) { | |
200 | /* Try to find an available timer */ | |
201 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
202 | if (mfgpt_timers[i].flags & F_AVAIL) | |
fa28e067 | 203 | return mfgpt_get(i); |
83d7384f AS |
204 | |
205 | if (i == 5 && domain == MFGPT_DOMAIN_WORKING) | |
206 | break; | |
207 | } | |
208 | } else { | |
209 | /* If they requested a specific timer, try to honor that */ | |
210 | if (mfgpt_timers[timer].flags & F_AVAIL) | |
fa28e067 | 211 | return mfgpt_get(timer); |
83d7384f AS |
212 | } |
213 | ||
214 | /* No timers available - too bad */ | |
215 | return -1; | |
216 | } | |
217 | ||
8f36881b AS |
218 | |
219 | #ifdef CONFIG_GEODE_MFGPT_TIMER | |
220 | ||
221 | /* | |
222 | * The MFPGT timers on the CS5536 provide us with suitable timers to use | |
223 | * as clock event sources - not as good as a HPET or APIC, but certainly | |
224 | * better then the PIT. This isn't a general purpose MFGPT driver, but | |
225 | * a simplified one designed specifically to act as a clock event source. | |
226 | * For full details about the MFGPT, please consult the CS5536 data sheet. | |
227 | */ | |
228 | ||
229 | #include <linux/clocksource.h> | |
230 | #include <linux/clockchips.h> | |
231 | ||
232 | static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN; | |
233 | static u16 mfgpt_event_clock; | |
234 | ||
235 | static int irq = 7; | |
236 | static int __init mfgpt_setup(char *str) | |
237 | { | |
238 | get_option(&str, &irq); | |
239 | return 1; | |
240 | } | |
241 | __setup("mfgpt_irq=", mfgpt_setup); | |
242 | ||
e78a77c3 | 243 | static void mfgpt_disable_timer(u16 clock) |
8f36881b AS |
244 | { |
245 | u16 val = geode_mfgpt_read(clock, MFGPT_REG_SETUP); | |
246 | geode_mfgpt_write(clock, MFGPT_REG_SETUP, val & ~MFGPT_SETUP_CNTEN); | |
247 | } | |
248 | ||
249 | static int mfgpt_next_event(unsigned long, struct clock_event_device *); | |
250 | static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *); | |
251 | ||
252 | static struct clock_event_device mfgpt_clockevent = { | |
253 | .name = "mfgpt-timer", | |
254 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
255 | .set_mode = mfgpt_set_mode, | |
256 | .set_next_event = mfgpt_next_event, | |
257 | .rating = 250, | |
258 | .cpumask = CPU_MASK_ALL, | |
259 | .shift = 32 | |
260 | }; | |
261 | ||
e78a77c3 | 262 | static void mfgpt_start_timer(u16 delta) |
8f36881b AS |
263 | { |
264 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta); | |
265 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
266 | ||
267 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
268 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
269 | } | |
270 | ||
271 | static void mfgpt_set_mode(enum clock_event_mode mode, | |
272 | struct clock_event_device *evt) | |
273 | { | |
274 | mfgpt_disable_timer(mfgpt_event_clock); | |
275 | ||
276 | if (mode == CLOCK_EVT_MODE_PERIODIC) | |
e78a77c3 | 277 | mfgpt_start_timer(MFGPT_PERIODIC); |
8f36881b AS |
278 | |
279 | mfgpt_tick_mode = mode; | |
280 | } | |
281 | ||
282 | static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) | |
283 | { | |
e78a77c3 | 284 | mfgpt_start_timer(delta); |
8f36881b AS |
285 | return 0; |
286 | } | |
287 | ||
288 | /* Assume (foolishly?), that this interrupt was due to our tick */ | |
289 | ||
290 | static irqreturn_t mfgpt_tick(int irq, void *dev_id) | |
291 | { | |
667984d9 JC |
292 | /* Turn off the clock (and clear the event) */ |
293 | mfgpt_disable_timer(mfgpt_event_clock); | |
294 | ||
8f36881b AS |
295 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN) |
296 | return IRQ_HANDLED; | |
297 | ||
8f36881b AS |
298 | /* Clear the counter */ |
299 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
300 | ||
301 | /* Restart the clock in periodic mode */ | |
302 | ||
303 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) { | |
304 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
305 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
306 | } | |
307 | ||
308 | mfgpt_clockevent.event_handler(&mfgpt_clockevent); | |
309 | return IRQ_HANDLED; | |
310 | } | |
311 | ||
312 | static struct irqaction mfgptirq = { | |
313 | .handler = mfgpt_tick, | |
314 | .flags = IRQF_DISABLED | IRQF_NOBALANCING, | |
315 | .mask = CPU_MASK_NONE, | |
316 | .name = "mfgpt-timer" | |
317 | }; | |
318 | ||
319 | static int __init mfgpt_timer_setup(void) | |
320 | { | |
321 | int timer, ret; | |
322 | u16 val; | |
323 | ||
fa28e067 | 324 | timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING); |
8f36881b AS |
325 | if (timer < 0) { |
326 | printk(KERN_ERR | |
327 | "mfgpt-timer: Could not allocate a MFPGT timer\n"); | |
328 | return -ENODEV; | |
329 | } | |
330 | ||
331 | mfgpt_event_clock = timer; | |
8f36881b AS |
332 | |
333 | /* Set up the IRQ on the MFGPT side */ | |
334 | if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) { | |
335 | printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq); | |
336 | return -EIO; | |
337 | } | |
338 | ||
339 | /* And register it with the kernel */ | |
340 | ret = setup_irq(irq, &mfgptirq); | |
341 | ||
342 | if (ret) { | |
343 | printk(KERN_ERR | |
344 | "mfgpt-timer: Unable to set up the interrupt.\n"); | |
345 | goto err; | |
346 | } | |
347 | ||
667984d9 JC |
348 | /* Set the clock scale and enable the event mode for CMP2 */ |
349 | val = MFGPT_SCALE | (3 << 8); | |
350 | ||
351 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val); | |
352 | ||
8f36881b AS |
353 | /* Set up the clock event */ |
354 | mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, 32); | |
355 | mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, | |
356 | &mfgpt_clockevent); | |
357 | mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, | |
358 | &mfgpt_clockevent); | |
359 | ||
360 | printk(KERN_INFO | |
361 | "mfgpt-timer: registering the MFGT timer as a clock event.\n"); | |
362 | clockevents_register_device(&mfgpt_clockevent); | |
363 | ||
364 | return 0; | |
365 | ||
366 | err: | |
367 | geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq); | |
368 | printk(KERN_ERR | |
369 | "mfgpt-timer: Unable to set up the MFGPT clock source\n"); | |
370 | return -EIO; | |
371 | } | |
372 | ||
373 | #endif |