Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
597e11a3 | 3 | * Copyright (C) 2008-2011 Advanced Micro Devices Inc. |
80cc9f10 PO |
4 | * |
5 | * Author: Peter Oruba <peter.oruba@amd.com> | |
6 | * | |
7 | * Based on work by: | |
8 | * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> | |
9 | * | |
597e11a3 | 10 | * Maintainers: |
943482d0 AH |
11 | * Andreas Herrmann <herrmann.der.user@googlemail.com> |
12 | * Borislav Petkov <bp@alien8.de> | |
597e11a3 BP |
13 | * |
14 | * This driver allows to upgrade microcode on F10h AMD | |
15 | * CPUs and later. | |
80cc9f10 | 16 | * |
2a3282a7 | 17 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 18 | * License version 2. See file COPYING for details. |
4bae1967 | 19 | */ |
f58e1f53 JP |
20 | |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
22 | ||
4bae1967 | 23 | #include <linux/firmware.h> |
4bae1967 IM |
24 | #include <linux/pci_ids.h> |
25 | #include <linux/uaccess.h> | |
26 | #include <linux/vmalloc.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
80cc9f10 | 29 | #include <linux/pci.h> |
80cc9f10 | 30 | |
80cc9f10 | 31 | #include <asm/microcode.h> |
4bae1967 IM |
32 | #include <asm/processor.h> |
33 | #include <asm/msr.h> | |
a76096a6 | 34 | #include <asm/microcode_amd.h> |
80cc9f10 PO |
35 | |
36 | MODULE_DESCRIPTION("AMD Microcode Update Driver"); | |
3c52204b | 37 | MODULE_AUTHOR("Peter Oruba"); |
5d7b6052 | 38 | MODULE_LICENSE("GPL v2"); |
80cc9f10 | 39 | |
a0a29b62 | 40 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 41 | |
a3eb3b4d BP |
42 | struct ucode_patch { |
43 | struct list_head plist; | |
44 | void *data; | |
45 | u32 patch_id; | |
46 | u16 equiv_cpu; | |
47 | }; | |
48 | ||
49 | static LIST_HEAD(pcache); | |
50 | ||
a76096a6 | 51 | static u16 __find_equiv_id(unsigned int cpu) |
c96d2c09 BP |
52 | { |
53 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
a76096a6 | 54 | return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig); |
c96d2c09 BP |
55 | } |
56 | ||
57 | static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu) | |
58 | { | |
59 | int i = 0; | |
60 | ||
61 | BUG_ON(!equiv_cpu_table); | |
62 | ||
63 | while (equiv_cpu_table[i].equiv_cpu != 0) { | |
64 | if (equiv_cpu == equiv_cpu_table[i].equiv_cpu) | |
65 | return equiv_cpu_table[i].installed_cpu; | |
66 | i++; | |
67 | } | |
68 | return 0; | |
69 | } | |
70 | ||
a3eb3b4d BP |
71 | /* |
72 | * a small, trivial cache of per-family ucode patches | |
73 | */ | |
74 | static struct ucode_patch *cache_find_patch(u16 equiv_cpu) | |
75 | { | |
76 | struct ucode_patch *p; | |
77 | ||
78 | list_for_each_entry(p, &pcache, plist) | |
79 | if (p->equiv_cpu == equiv_cpu) | |
80 | return p; | |
81 | return NULL; | |
82 | } | |
83 | ||
84 | static void update_cache(struct ucode_patch *new_patch) | |
85 | { | |
86 | struct ucode_patch *p; | |
87 | ||
88 | list_for_each_entry(p, &pcache, plist) { | |
89 | if (p->equiv_cpu == new_patch->equiv_cpu) { | |
90 | if (p->patch_id >= new_patch->patch_id) | |
91 | /* we already have the latest patch */ | |
92 | return; | |
93 | ||
94 | list_replace(&p->plist, &new_patch->plist); | |
95 | kfree(p->data); | |
96 | kfree(p); | |
97 | return; | |
98 | } | |
99 | } | |
100 | /* no patch found, add it */ | |
101 | list_add_tail(&new_patch->plist, &pcache); | |
102 | } | |
103 | ||
104 | static void free_cache(void) | |
105 | { | |
2d297480 | 106 | struct ucode_patch *p, *tmp; |
a3eb3b4d | 107 | |
2d297480 | 108 | list_for_each_entry_safe(p, tmp, &pcache, plist) { |
a3eb3b4d BP |
109 | __list_del(p->plist.prev, p->plist.next); |
110 | kfree(p->data); | |
111 | kfree(p); | |
112 | } | |
113 | } | |
114 | ||
115 | static struct ucode_patch *find_patch(unsigned int cpu) | |
116 | { | |
117 | u16 equiv_id; | |
118 | ||
a76096a6 | 119 | equiv_id = __find_equiv_id(cpu); |
a3eb3b4d BP |
120 | if (!equiv_id) |
121 | return NULL; | |
122 | ||
123 | return cache_find_patch(equiv_id); | |
124 | } | |
125 | ||
d45de409 | 126 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 | 127 | { |
3b2e3d85 | 128 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
80cc9f10 | 129 | |
5f5b7472 | 130 | csig->sig = cpuid_eax(0x00000001); |
bcb80e53 | 131 | csig->rev = c->microcode; |
258721ef BP |
132 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); |
133 | ||
d45de409 | 134 | return 0; |
80cc9f10 PO |
135 | } |
136 | ||
2efb05e8 | 137 | static unsigned int verify_patch_size(int cpu, u32 patch_size, |
be62adb4 | 138 | unsigned int size) |
80cc9f10 | 139 | { |
be62adb4 BP |
140 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
141 | u32 max_size; | |
142 | ||
143 | #define F1XH_MPB_MAX_SIZE 2048 | |
144 | #define F14H_MPB_MAX_SIZE 1824 | |
145 | #define F15H_MPB_MAX_SIZE 4096 | |
36c46ca4 | 146 | #define F16H_MPB_MAX_SIZE 3458 |
be62adb4 BP |
147 | |
148 | switch (c->x86) { | |
149 | case 0x14: | |
150 | max_size = F14H_MPB_MAX_SIZE; | |
151 | break; | |
152 | case 0x15: | |
153 | max_size = F15H_MPB_MAX_SIZE; | |
154 | break; | |
36c46ca4 BO |
155 | case 0x16: |
156 | max_size = F16H_MPB_MAX_SIZE; | |
157 | break; | |
be62adb4 BP |
158 | default: |
159 | max_size = F1XH_MPB_MAX_SIZE; | |
160 | break; | |
161 | } | |
162 | ||
163 | if (patch_size > min_t(u32, size, max_size)) { | |
164 | pr_err("patch size mismatch\n"); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | return patch_size; | |
169 | } | |
170 | ||
a76096a6 JS |
171 | int __apply_microcode_amd(struct microcode_amd *mc_amd) |
172 | { | |
173 | u32 rev, dummy; | |
174 | ||
175 | wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); | |
176 | ||
177 | /* verify patch application was successful */ | |
178 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); | |
179 | if (rev != mc_amd->hdr.patch_id) | |
180 | return -1; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | int apply_microcode_amd(int cpu) | |
80cc9f10 | 186 | { |
bcb80e53 | 187 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
2efb05e8 BP |
188 | struct microcode_amd *mc_amd; |
189 | struct ucode_cpu_info *uci; | |
190 | struct ucode_patch *p; | |
191 | u32 rev, dummy; | |
192 | ||
193 | BUG_ON(raw_smp_processor_id() != cpu); | |
80cc9f10 | 194 | |
2efb05e8 | 195 | uci = ucode_cpu_info + cpu; |
80cc9f10 | 196 | |
2efb05e8 BP |
197 | p = find_patch(cpu); |
198 | if (!p) | |
871b72dd | 199 | return 0; |
80cc9f10 | 200 | |
2efb05e8 BP |
201 | mc_amd = p->data; |
202 | uci->mc = p->data; | |
203 | ||
29d0887f | 204 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 | 205 | |
685ca6d7 BP |
206 | /* need to apply patch? */ |
207 | if (rev >= mc_amd->hdr.patch_id) { | |
208 | c->microcode = rev; | |
209 | return 0; | |
210 | } | |
211 | ||
a76096a6 | 212 | if (__apply_microcode_amd(mc_amd)) |
258721ef | 213 | pr_err("CPU%d: update failed for patch_level=0x%08x\n", |
a76096a6 JS |
214 | cpu, mc_amd->hdr.patch_id); |
215 | else | |
216 | pr_info("CPU%d: new patch_level=0x%08x\n", cpu, | |
217 | mc_amd->hdr.patch_id); | |
80cc9f10 | 218 | |
a76096a6 JS |
219 | uci->cpu_sig.rev = mc_amd->hdr.patch_id; |
220 | c->microcode = mc_amd->hdr.patch_id; | |
871b72dd DA |
221 | |
222 | return 0; | |
80cc9f10 PO |
223 | } |
224 | ||
0657d9eb | 225 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 226 | { |
10de52d6 BP |
227 | unsigned int *ibuf = (unsigned int *)buf; |
228 | unsigned int type = ibuf[1]; | |
229 | unsigned int size = ibuf[2]; | |
80cc9f10 | 230 | |
10de52d6 | 231 | if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
258721ef BP |
232 | pr_err("empty section/" |
233 | "invalid type field in container file section header\n"); | |
10de52d6 | 234 | return -EINVAL; |
80cc9f10 PO |
235 | } |
236 | ||
8e5e9521 | 237 | equiv_cpu_table = vmalloc(size); |
80cc9f10 | 238 | if (!equiv_cpu_table) { |
f58e1f53 | 239 | pr_err("failed to allocate equivalent CPU table\n"); |
10de52d6 | 240 | return -ENOMEM; |
80cc9f10 PO |
241 | } |
242 | ||
e7e632f5 | 243 | memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size); |
80cc9f10 | 244 | |
40b7f3df BP |
245 | /* add header length */ |
246 | return size + CONTAINER_HDR_SZ; | |
80cc9f10 PO |
247 | } |
248 | ||
a0a29b62 | 249 | static void free_equiv_cpu_table(void) |
80cc9f10 | 250 | { |
aeef50bc F |
251 | vfree(equiv_cpu_table); |
252 | equiv_cpu_table = NULL; | |
a0a29b62 | 253 | } |
80cc9f10 | 254 | |
2efb05e8 | 255 | static void cleanup(void) |
a0a29b62 | 256 | { |
2efb05e8 BP |
257 | free_equiv_cpu_table(); |
258 | free_cache(); | |
259 | } | |
260 | ||
261 | /* | |
262 | * We return the current size even if some of the checks failed so that | |
263 | * we can skip over the next patch. If we return a negative value, we | |
264 | * signal a grave error like a memory allocation has failed and the | |
265 | * driver cannot continue functioning normally. In such cases, we tear | |
266 | * down everything we've used up so far and exit. | |
267 | */ | |
268 | static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover) | |
269 | { | |
270 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
271 | struct microcode_header_amd *mc_hdr; | |
272 | struct ucode_patch *patch; | |
273 | unsigned int patch_size, crnt_size, ret; | |
274 | u32 proc_fam; | |
275 | u16 proc_id; | |
276 | ||
277 | patch_size = *(u32 *)(fw + 4); | |
278 | crnt_size = patch_size + SECTION_HDR_SIZE; | |
279 | mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE); | |
280 | proc_id = mc_hdr->processor_rev_id; | |
281 | ||
282 | proc_fam = find_cpu_family_by_equiv_cpu(proc_id); | |
283 | if (!proc_fam) { | |
284 | pr_err("No patch family for equiv ID: 0x%04x\n", proc_id); | |
285 | return crnt_size; | |
286 | } | |
287 | ||
288 | /* check if patch is for the current family */ | |
289 | proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff); | |
290 | if (proc_fam != c->x86) | |
291 | return crnt_size; | |
292 | ||
293 | if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { | |
294 | pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", | |
295 | mc_hdr->patch_id); | |
296 | return crnt_size; | |
297 | } | |
298 | ||
299 | ret = verify_patch_size(cpu, patch_size, leftover); | |
300 | if (!ret) { | |
301 | pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id); | |
302 | return crnt_size; | |
303 | } | |
304 | ||
305 | patch = kzalloc(sizeof(*patch), GFP_KERNEL); | |
306 | if (!patch) { | |
307 | pr_err("Patch allocation failure.\n"); | |
308 | return -EINVAL; | |
309 | } | |
310 | ||
311 | patch->data = kzalloc(patch_size, GFP_KERNEL); | |
312 | if (!patch->data) { | |
313 | pr_err("Patch data allocation failure.\n"); | |
314 | kfree(patch); | |
315 | return -EINVAL; | |
316 | } | |
317 | ||
318 | /* All looks ok, copy patch... */ | |
319 | memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size); | |
320 | INIT_LIST_HEAD(&patch->plist); | |
321 | patch->patch_id = mc_hdr->patch_id; | |
322 | patch->equiv_cpu = proc_id; | |
323 | ||
324 | /* ... and add to cache. */ | |
325 | update_cache(patch); | |
326 | ||
327 | return crnt_size; | |
328 | } | |
329 | ||
a76096a6 | 330 | static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t size) |
2efb05e8 BP |
331 | { |
332 | enum ucode_state ret = UCODE_ERROR; | |
333 | unsigned int leftover; | |
334 | u8 *fw = (u8 *)data; | |
335 | int crnt_size = 0; | |
1396fa9c | 336 | int offset; |
80cc9f10 | 337 | |
2efb05e8 | 338 | offset = install_equiv_cpu_table(data); |
10de52d6 | 339 | if (offset < 0) { |
f58e1f53 | 340 | pr_err("failed to create equivalent cpu table\n"); |
2efb05e8 | 341 | return ret; |
80cc9f10 | 342 | } |
2efb05e8 | 343 | fw += offset; |
a0a29b62 DA |
344 | leftover = size - offset; |
345 | ||
2efb05e8 | 346 | if (*(u32 *)fw != UCODE_UCODE_TYPE) { |
be62adb4 | 347 | pr_err("invalid type field in container file section header\n"); |
2efb05e8 BP |
348 | free_equiv_cpu_table(); |
349 | return ret; | |
be62adb4 | 350 | } |
a0a29b62 | 351 | |
be62adb4 | 352 | while (leftover) { |
2efb05e8 BP |
353 | crnt_size = verify_and_add_patch(cpu, fw, leftover); |
354 | if (crnt_size < 0) | |
355 | return ret; | |
d733689a | 356 | |
2efb05e8 BP |
357 | fw += crnt_size; |
358 | leftover -= crnt_size; | |
80cc9f10 | 359 | } |
a0a29b62 | 360 | |
2efb05e8 | 361 | return UCODE_OK; |
a0a29b62 DA |
362 | } |
363 | ||
a76096a6 JS |
364 | enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size) |
365 | { | |
366 | enum ucode_state ret; | |
367 | ||
368 | /* free old equiv table */ | |
369 | free_equiv_cpu_table(); | |
370 | ||
371 | ret = __load_microcode_amd(cpu, data, size); | |
372 | ||
373 | if (ret != UCODE_OK) | |
374 | cleanup(); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
5b68edc9 AH |
379 | /* |
380 | * AMD microcode firmware naming convention, up to family 15h they are in | |
381 | * the legacy file: | |
382 | * | |
383 | * amd-ucode/microcode_amd.bin | |
384 | * | |
385 | * This legacy file is always smaller than 2K in size. | |
386 | * | |
2efb05e8 | 387 | * Beginning with family 15h, they are in family-specific firmware files: |
5b68edc9 AH |
388 | * |
389 | * amd-ucode/microcode_amd_fam15h.bin | |
390 | * amd-ucode/microcode_amd_fam16h.bin | |
391 | * ... | |
392 | * | |
393 | * These might be larger than 2K. | |
394 | */ | |
48e30685 BP |
395 | static enum ucode_state request_microcode_amd(int cpu, struct device *device, |
396 | bool refresh_fw) | |
a0a29b62 | 397 | { |
5b68edc9 | 398 | char fw_name[36] = "amd-ucode/microcode_amd.bin"; |
5b68edc9 | 399 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
2efb05e8 BP |
400 | enum ucode_state ret = UCODE_NFOUND; |
401 | const struct firmware *fw; | |
402 | ||
403 | /* reload ucode container only on the boot cpu */ | |
404 | if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index) | |
405 | return UCODE_OK; | |
5b68edc9 AH |
406 | |
407 | if (c->x86 >= 0x15) | |
408 | snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); | |
a0a29b62 | 409 | |
5b68edc9 | 410 | if (request_firmware(&fw, (const char *)fw_name, device)) { |
258721ef | 411 | pr_err("failed to load file %s\n", fw_name); |
ffc7e8ac | 412 | goto out; |
3b2e3d85 | 413 | } |
a0a29b62 | 414 | |
ffc7e8ac BP |
415 | ret = UCODE_ERROR; |
416 | if (*(u32 *)fw->data != UCODE_MAGIC) { | |
258721ef | 417 | pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); |
ffc7e8ac | 418 | goto fw_release; |
506f90ee BP |
419 | } |
420 | ||
2efb05e8 | 421 | ret = load_microcode_amd(cpu, fw->data, fw->size); |
a0a29b62 | 422 | |
2efb05e8 | 423 | fw_release: |
ffc7e8ac | 424 | release_firmware(fw); |
3b2e3d85 | 425 | |
2efb05e8 | 426 | out: |
a0a29b62 DA |
427 | return ret; |
428 | } | |
429 | ||
871b72dd DA |
430 | static enum ucode_state |
431 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 432 | { |
871b72dd | 433 | return UCODE_ERROR; |
80cc9f10 PO |
434 | } |
435 | ||
80cc9f10 PO |
436 | static void microcode_fini_cpu_amd(int cpu) |
437 | { | |
438 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
439 | ||
18dbc916 | 440 | uci->mc = NULL; |
80cc9f10 PO |
441 | } |
442 | ||
443 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 | 444 | .request_microcode_user = request_microcode_user, |
ffc7e8ac | 445 | .request_microcode_fw = request_microcode_amd, |
80cc9f10 PO |
446 | .collect_cpu_info = collect_cpu_info_amd, |
447 | .apply_microcode = apply_microcode_amd, | |
448 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
449 | }; | |
450 | ||
18dbc916 | 451 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 452 | { |
283c1f25 AH |
453 | struct cpuinfo_x86 *c = &cpu_data(0); |
454 | ||
455 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { | |
456 | pr_warning("AMD CPU family 0x%x not supported\n", c->x86); | |
457 | return NULL; | |
458 | } | |
459 | ||
18dbc916 | 460 | return µcode_amd_ops; |
80cc9f10 | 461 | } |
f72c1a57 BP |
462 | |
463 | void __exit exit_amd_microcode(void) | |
464 | { | |
2efb05e8 | 465 | cleanup(); |
f72c1a57 | 466 | } |