[deliverable/linux.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  Maintainers:
 *  Andreas Herrmann <andreas.herrmann3@amd.com>
 *  Borislav Petkov <borislav.petkov@amd.com>
 *
 *  This driver allows to upgrade microcode on F10h AMD
 *  CPUs and later.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	u32	installed_cpu;
	u32	fixed_errata_mask;
	u32	fixed_errata_compare;
	u16	equiv_cpu;
	u16	res;
} __attribute__((packed));

struct microcode_header_amd {
	u32	data_code;
	u32	patch_id;
	u16	mc_patch_data_id;
	u8	mc_patch_data_len;
	u8	init_flag;
	u32	mc_patch_data_checksum;
	u32	nb_dev_id;
	u32	sb_dev_id;
	u16	processor_rev_id;
	u8	nb_rev_id;
	u8	sb_rev_id;
	u8	bios_api_rev;
	u8	reserved1[3];
	u32	match_reg[8];
} __attribute__((packed));

struct microcode_amd {
	struct microcode_header_amd	hdr;
	unsigned int			mpb[0];
};

#define SECTION_HDR_SIZE	8
#define CONTAINER_HDR_SZ	12

static struct equiv_cpu_entry *equiv_cpu_table;

/* page-sized ucode patch buffer */
void *patch;

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
		return -1;
	}

	csig->rev = c->microcode;
	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);

	return 0;
}

static unsigned int verify_ucode_size(int cpu, u32 patch_size,
				      unsigned int size)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	u32 max_size;

#define F1XH_MPB_MAX_SIZE 2048
#define F14H_MPB_MAX_SIZE 1824
#define F15H_MPB_MAX_SIZE 4096

	switch (c->x86) {
	case 0x14:
		max_size = F14H_MPB_MAX_SIZE;
		break;
	case 0x15:
		max_size = F15H_MPB_MAX_SIZE;
		break;
	default:
		max_size = F1XH_MPB_MAX_SIZE;
		break;
	}

	if (patch_size > min_t(u32, size, max_size)) {
		pr_err("patch size mismatch\n");
		return 0;
	}

	return patch_size;
}

static u16 find_equiv_id(void)
{
	unsigned int current_cpu_id, i = 0;

	BUG_ON(equiv_cpu_table == NULL);

	current_cpu_id = cpuid_eax(0x00000001);

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (current_cpu_id == equiv_cpu_table[i].installed_cpu)
			return equiv_cpu_table[i].equiv_cpu;

		i++;
	}
	return 0;
}

/*
 * we signal a good patch is found by returning its size > 0
 */
static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
				  unsigned int leftover_size, int rev,
				  unsigned int *current_size)
{
	struct microcode_header_amd *mc_hdr;
	unsigned int actual_size;
	u16 equiv_cpu_id;

	/* size of the current patch we're staring at */
	*current_size = *(u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE;

	equiv_cpu_id = find_equiv_id();
	if (!equiv_cpu_id)
		return 0;

	/*
	 * let's look at the patch header itself now
	 */
	mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE);

	if (mc_hdr->processor_rev_id != equiv_cpu_id)
		return 0;

	/* ucode might be chipset specific -- currently we don't support this */
	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
		pr_err("CPU%d: chipset specific code not yet supported\n",
		       cpu);
		return 0;
	}

	if (mc_hdr->patch_id <= rev)
		return 0;

	/*
	 * now that the header looks sane, verify its size
	 */
	actual_size = verify_ucode_size(cpu, *current_size, leftover_size);
	if (!actual_size)
		return 0;

	/* clear the patch buffer */
	memset(patch, 0, PAGE_SIZE);

	/* all looks ok, get the binary patch */
	get_ucode_data(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size);

	return actual_size;
}

static int apply_microcode_amd(int cpu)
{
	u32 rev, dummy;
	int cpu_num = raw_smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
	struct microcode_amd *mc_amd = uci->mc;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	/* We should bind the task to the CPU */
	BUG_ON(cpu_num != cpu);

	if (mc_amd == NULL)
		return 0;

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	/* get patch id after patching */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* check current patch id and patch's id for match */
	if (rev != mc_amd->hdr.patch_id) {
		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
		       cpu, mc_amd->hdr.patch_id);
		return -1;
	}

	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
	uci->cpu_sig.rev = rev;
	c->microcode = rev;

	return 0;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	unsigned int *ibuf = (unsigned int *)buf;
	unsigned int type = ibuf[1];
	unsigned int size = ibuf[2];

	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("empty section/"
		       "invalid type field in container file section header\n");
		return -EINVAL;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return -ENOMEM;
	}

	get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);

	/* add header length */
	return size + CONTAINER_HDR_SZ;
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static enum ucode_state
generic_load_microcode(int cpu, const u8 *data, size_t size)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	struct microcode_header_amd *mc_hdr = NULL;
	unsigned int mc_size, leftover, current_size = 0;
	int offset;
	const u8 *ucode_ptr = data;
	void *new_mc = NULL;
	unsigned int new_rev = uci->cpu_sig.rev;
	enum ucode_state state = UCODE_ERROR;

	offset = install_equiv_cpu_table(ucode_ptr);
	if (offset < 0) {
		pr_err("failed to create equivalent cpu table\n");
		goto out;
	}
	ucode_ptr += offset;
	leftover = size - offset;

	if (*(u32 *)ucode_ptr != UCODE_UCODE_TYPE) {
		pr_err("invalid type field in container file section header\n");
		goto free_table;
	}

	while (leftover) {
		mc_size = get_matching_microcode(cpu, ucode_ptr, leftover,
						 new_rev, &current_size);
		if (mc_size) {
			mc_hdr  = patch;
			new_mc  = patch;
			new_rev = mc_hdr->patch_id;
			goto out_ok;
		}

		ucode_ptr += current_size;
		leftover  -= current_size;
	}

	if (!new_mc) {
		state = UCODE_NFOUND;
		goto free_table;
	}

out_ok:
	uci->mc = new_mc;
	state = UCODE_OK;
	pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
		 cpu, uci->cpu_sig.rev, new_rev);

free_table:
	free_equiv_cpu_table();

out:
	return state;
}

/*
 * AMD microcode firmware naming convention, up to family 15h they are in
 * the legacy file:
 *
 *    amd-ucode/microcode_amd.bin
 *
 * This legacy file is always smaller than 2K in size.
 *
 * Starting at family 15h they are in family specific firmware files:
 *
 *    amd-ucode/microcode_amd_fam15h.bin
 *    amd-ucode/microcode_amd_fam16h.bin
 *    ...
 *
 * These might be larger than 2K.
 */
static enum ucode_state request_microcode_amd(int cpu, struct device *device)
{
	char fw_name[36] = "amd-ucode/microcode_amd.bin";
	const struct firmware *fw;
	enum ucode_state ret = UCODE_NFOUND;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	if (c->x86 >= 0x15)
		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);

	if (request_firmware(&fw, (const char *)fw_name, device)) {
		pr_err("failed to load file %s\n", fw_name);
		goto out;
	}

	ret = UCODE_ERROR;
	if (*(u32 *)fw->data != UCODE_MAGIC) {
		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
		goto fw_release;
	}

	ret = generic_load_microcode(cpu, fw->data, fw->size);

fw_release:
	release_firmware(fw);

out:
	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_amd,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	patch = (void *)get_zeroed_page(GFP_KERNEL);
	if (!patch)
		return NULL;

	return &microcode_amd_ops;
}

void __exit exit_amd_microcode(void)
{
	free_page((unsigned long)patch);
}
Commit	Line	Data
80cc9f10 PO	1	/*
80cc9f10 PO	2	* AMD CPU Microcode Update Driver for Linux
597e11a3	3	* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
80cc9f10 PO	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
597e11a3 BP	10	* Maintainers:
	11	* Andreas Herrmann <andreas.herrmann3@amd.com>
	12	* Borislav Petkov <borislav.petkov@amd.com>
	13	*
	14	* This driver allows to upgrade microcode on F10h AMD
	15	* CPUs and later.
80cc9f10	16	*
2a3282a7	17	* Licensed under the terms of the GNU General Public
80cc9f10	18	* License version 2. See file COPYING for details.
4bae1967	19	*/
f58e1f53 JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
4bae1967	23	#include <linux/firmware.h>
4bae1967 IM	24	#include <linux/pci_ids.h>
	25	#include <linux/uaccess.h>
	26	#include <linux/vmalloc.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
80cc9f10	29	#include <linux/pci.h>
80cc9f10	30
80cc9f10	31	#include <asm/microcode.h>
4bae1967 IM	32	#include <asm/processor.h>
4bae1967 IM	33	#include <asm/msr.h>
80cc9f10 PO	34
80cc9f10 PO	35	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	36	MODULE_AUTHOR("Peter Oruba");
5d7b6052	37	MODULE_LICENSE("GPL v2");
80cc9f10 PO	38
	39	#define UCODE_MAGIC 0x00414d44
	40	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	41	#define UCODE_UCODE_TYPE 0x00000001
	42
18dbc916	43	struct equiv_cpu_entry {
5549b94b AH	44	u32 installed_cpu;
	45	u32 fixed_errata_mask;
	46	u32 fixed_errata_compare;
	47	u16 equiv_cpu;
	48	u16 res;
	49	} __attribute__((packed));
18dbc916 DA	50
18dbc916 DA	51	struct microcode_header_amd {
5549b94b AH	52	u32 data_code;
	53	u32 patch_id;
	54	u16 mc_patch_data_id;
	55	u8 mc_patch_data_len;
	56	u8 init_flag;
	57	u32 mc_patch_data_checksum;
	58	u32 nb_dev_id;
	59	u32 sb_dev_id;
	60	u16 processor_rev_id;
	61	u8 nb_rev_id;
	62	u8 sb_rev_id;
	63	u8 bios_api_rev;
	64	u8 reserved1[3];
	65	u32 match_reg[8];
	66	} __attribute__((packed));
18dbc916 DA	67
18dbc916 DA	68	struct microcode_amd {
4bae1967 IM	69	struct microcode_header_amd hdr;
4bae1967 IM	70	unsigned int mpb[0];
18dbc916 DA	71	};
18dbc916 DA	72
40b7f3df BP	73	#define SECTION_HDR_SIZE 8
40b7f3df BP	74	#define CONTAINER_HDR_SZ 12
80cc9f10	75
a0a29b62	76	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	77
96b0ee45 BP	78	/* page-sized ucode patch buffer */
	79	void *patch;
	80
d45de409	81	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	82	{
3b2e3d85	83	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10	84
3b2e3d85	85	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
258721ef	86	pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
3b2e3d85 AH	87	return -1;
3b2e3d85 AH	88	}
258721ef	89
bcb80e53	90	csig->rev = c->microcode;
258721ef BP	91	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
258721ef BP	92
d45de409	93	return 0;
80cc9f10 PO	94	}
80cc9f10 PO	95
be62adb4 BP	96	static unsigned int verify_ucode_size(int cpu, u32 patch_size,
be62adb4 BP	97	unsigned int size)
80cc9f10	98	{
be62adb4 BP	99	struct cpuinfo_x86 *c = &cpu_data(cpu);
	100	u32 max_size;
	101
	102	#define F1XH_MPB_MAX_SIZE 2048
	103	#define F14H_MPB_MAX_SIZE 1824
	104	#define F15H_MPB_MAX_SIZE 4096
	105
	106	switch (c->x86) {
	107	case 0x14:
	108	max_size = F14H_MPB_MAX_SIZE;
	109	break;
	110	case 0x15:
	111	max_size = F15H_MPB_MAX_SIZE;
	112	break;
	113	default:
	114	max_size = F1XH_MPB_MAX_SIZE;
	115	break;
	116	}
	117
	118	if (patch_size > min_t(u32, size, max_size)) {
	119	pr_err("patch size mismatch\n");
	120	return 0;
	121	}
	122
	123	return patch_size;
	124	}
	125
	126	static u16 find_equiv_id(void)
	127	{
	128	unsigned int current_cpu_id, i = 0;
80cc9f10	129
a0a29b62	130	BUG_ON(equiv_cpu_table == NULL);
be62adb4	131
80cc9f10 PO	132	current_cpu_id = cpuid_eax(0x00000001);
	133
	134	while (equiv_cpu_table[i].installed_cpu != 0) {
be62adb4 BP	135	if (current_cpu_id == equiv_cpu_table[i].installed_cpu)
	136	return equiv_cpu_table[i].equiv_cpu;
	137
80cc9f10 PO	138	i++;
80cc9f10 PO	139	}
be62adb4 BP	140	return 0;
be62adb4 BP	141	}
80cc9f10	142
be62adb4 BP	143	/*
	144	* we signal a good patch is found by returning its size > 0
	145	*/
	146	static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
	147	unsigned int leftover_size, int rev,
	148	unsigned int *current_size)
	149	{
	150	struct microcode_header_amd *mc_hdr;
	151	unsigned int actual_size;
	152	u16 equiv_cpu_id;
	153
	154	/* size of the current patch we're staring at */
	155	current_size = (u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE;
	156
	157	equiv_cpu_id = find_equiv_id();
14c56942	158	if (!equiv_cpu_id)
80cc9f10	159	return 0;
80cc9f10	160
be62adb4 BP	161	/*
	162	* let's look at the patch header itself now
	163	*/
	164	mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE);
	165
7cc27349	166	if (mc_hdr->processor_rev_id != equiv_cpu_id)
80cc9f10	167	return 0;
80cc9f10	168
98415301	169	/* ucode might be chipset specific -- currently we don't support this */
7cc27349	170	if (mc_hdr->nb_dev_id \|\| mc_hdr->sb_dev_id) {
258721ef	171	pr_err("CPU%d: chipset specific code not yet supported\n",
f58e1f53	172	cpu);
98415301	173	return 0;
80cc9f10 PO	174	}
80cc9f10 PO	175
7cc27349	176	if (mc_hdr->patch_id <= rev)
80cc9f10 PO	177	return 0;
80cc9f10 PO	178
be62adb4 BP	179	/*
	180	* now that the header looks sane, verify its size
	181	*/
	182	actual_size = verify_ucode_size(cpu, *current_size, leftover_size);
	183	if (!actual_size)
	184	return 0;
	185
	186	/* clear the patch buffer */
	187	memset(patch, 0, PAGE_SIZE);
	188
	189	/* all looks ok, get the binary patch */
	190	get_ucode_data(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size);
	191
	192	return actual_size;
80cc9f10 PO	193	}
80cc9f10 PO	194
871b72dd	195	static int apply_microcode_amd(int cpu)
80cc9f10	196	{
29d0887f	197	u32 rev, dummy;
80cc9f10 PO	198	int cpu_num = raw_smp_processor_id();
80cc9f10 PO	199	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
18dbc916	200	struct microcode_amd *mc_amd = uci->mc;
bcb80e53	201	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10 PO	202
	203	/* We should bind the task to the CPU */
	204	BUG_ON(cpu_num != cpu);
	205
18dbc916	206	if (mc_amd == NULL)
871b72dd	207	return 0;
80cc9f10	208
f34a10bd	209	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
80cc9f10	210	/* get patch id after patching */
29d0887f	211	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10 PO	212
80cc9f10 PO	213	/* check current patch id and patch's id for match */
18dbc916	214	if (rev != mc_amd->hdr.patch_id) {
258721ef	215	pr_err("CPU%d: update failed for patch_level=0x%08x\n",
f58e1f53	216	cpu, mc_amd->hdr.patch_id);
871b72dd	217	return -1;
80cc9f10 PO	218	}
80cc9f10 PO	219
258721ef	220	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
d45de409	221	uci->cpu_sig.rev = rev;
bcb80e53	222	c->microcode = rev;
871b72dd DA	223
871b72dd DA	224	return 0;
80cc9f10 PO	225	}
80cc9f10 PO	226
0657d9eb	227	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	228	{
10de52d6 BP	229	unsigned int ibuf = (unsigned int )buf;
	230	unsigned int type = ibuf[1];
	231	unsigned int size = ibuf[2];
80cc9f10	232
10de52d6	233	if (type != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
258721ef BP	234	pr_err("empty section/"
258721ef BP	235	"invalid type field in container file section header\n");
10de52d6	236	return -EINVAL;
80cc9f10 PO	237	}
80cc9f10 PO	238
8e5e9521	239	equiv_cpu_table = vmalloc(size);
80cc9f10	240	if (!equiv_cpu_table) {
f58e1f53	241	pr_err("failed to allocate equivalent CPU table\n");
10de52d6	242	return -ENOMEM;
80cc9f10 PO	243	}
80cc9f10 PO	244
40b7f3df	245	get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
80cc9f10	246
40b7f3df BP	247	/* add header length */
40b7f3df BP	248	return size + CONTAINER_HDR_SZ;
80cc9f10 PO	249	}
80cc9f10 PO	250
a0a29b62	251	static void free_equiv_cpu_table(void)
80cc9f10	252	{
aeef50bc F	253	vfree(equiv_cpu_table);
aeef50bc F	254	equiv_cpu_table = NULL;
a0a29b62	255	}
80cc9f10	256
871b72dd DA	257	static enum ucode_state
871b72dd DA	258	generic_load_microcode(int cpu, const u8 *data, size_t size)
a0a29b62 DA	259	{
a0a29b62 DA	260	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
7cc27349	261	struct microcode_header_amd *mc_hdr = NULL;
be62adb4	262	unsigned int mc_size, leftover, current_size = 0;
1396fa9c	263	int offset;
8c135206 AH	264	const u8 *ucode_ptr = data;
8c135206 AH	265	void *new_mc = NULL;
258721ef	266	unsigned int new_rev = uci->cpu_sig.rev;
be62adb4	267	enum ucode_state state = UCODE_ERROR;
80cc9f10	268
0657d9eb	269	offset = install_equiv_cpu_table(ucode_ptr);
10de52d6	270	if (offset < 0) {
f58e1f53	271	pr_err("failed to create equivalent cpu table\n");
be62adb4	272	goto out;
80cc9f10	273	}
a0a29b62 DA	274	ucode_ptr += offset;
	275	leftover = size - offset;
	276
be62adb4 BP	277	if ((u32 )ucode_ptr != UCODE_UCODE_TYPE) {
	278	pr_err("invalid type field in container file section header\n");
	279	goto free_table;
	280	}
a0a29b62	281
be62adb4 BP	282	while (leftover) {
	283	mc_size = get_matching_microcode(cpu, ucode_ptr, leftover,
	284	new_rev, &current_size);
	285	if (mc_size) {
	286	mc_hdr = patch;
	287	new_mc = patch;
7cc27349	288	new_rev = mc_hdr->patch_id;
d733689a	289	goto out_ok;
be62adb4	290	}
d733689a BP	291
	292	ucode_ptr += current_size;
	293	leftover -= current_size;
80cc9f10	294	}
a0a29b62	295
7cc27349	296	if (!new_mc) {
871b72dd	297	state = UCODE_NFOUND;
7cc27349 BP	298	goto free_table;
	299	}
	300
d733689a BP	301	out_ok:
	302	uci->mc = new_mc;
	303	state = UCODE_OK;
	304	pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
	305	cpu, uci->cpu_sig.rev, new_rev);
a0a29b62	306
7cc27349	307	free_table:
a0a29b62 DA	308	free_equiv_cpu_table();
a0a29b62 DA	309
be62adb4	310	out:
871b72dd	311	return state;
a0a29b62 DA	312	}
a0a29b62 DA	313
5b68edc9 AH	314	/*
	315	* AMD microcode firmware naming convention, up to family 15h they are in
	316	* the legacy file:
	317	*
	318	* amd-ucode/microcode_amd.bin
	319	*
	320	* This legacy file is always smaller than 2K in size.
	321	*
	322	* Starting at family 15h they are in family specific firmware files:
	323	*
	324	* amd-ucode/microcode_amd_fam15h.bin
	325	* amd-ucode/microcode_amd_fam16h.bin
	326	* ...
	327	*
	328	* These might be larger than 2K.
	329	*/
ffc7e8ac	330	static enum ucode_state request_microcode_amd(int cpu, struct device *device)
a0a29b62	331	{
5b68edc9	332	char fw_name[36] = "amd-ucode/microcode_amd.bin";
ffc7e8ac BP	333	const struct firmware *fw;
ffc7e8ac BP	334	enum ucode_state ret = UCODE_NFOUND;
5b68edc9 AH	335	struct cpuinfo_x86 *c = &cpu_data(cpu);
	336
	337	if (c->x86 >= 0x15)
	338	snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
a0a29b62	339
5b68edc9	340	if (request_firmware(&fw, (const char *)fw_name, device)) {
258721ef	341	pr_err("failed to load file %s\n", fw_name);
ffc7e8ac	342	goto out;
3b2e3d85	343	}
a0a29b62	344
ffc7e8ac BP	345	ret = UCODE_ERROR;
ffc7e8ac BP	346	if ((u32 )fw->data != UCODE_MAGIC) {
258721ef	347	pr_err("invalid magic value (0x%08x)\n", (u32 )fw->data);
ffc7e8ac	348	goto fw_release;
506f90ee BP	349	}
506f90ee BP	350
ffc7e8ac	351	ret = generic_load_microcode(cpu, fw->data, fw->size);
a0a29b62	352
ffc7e8ac BP	353	fw_release:
ffc7e8ac BP	354	release_firmware(fw);
3b2e3d85	355
ffc7e8ac	356	out:
a0a29b62 DA	357	return ret;
	358	}
	359
871b72dd DA	360	static enum ucode_state
871b72dd DA	361	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	362	{
871b72dd	363	return UCODE_ERROR;
80cc9f10 PO	364	}
80cc9f10 PO	365
80cc9f10 PO	366	static void microcode_fini_cpu_amd(int cpu)
	367	{
	368	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	369
18dbc916	370	uci->mc = NULL;
80cc9f10 PO	371	}
	372
	373	static struct microcode_ops microcode_amd_ops = {
a0a29b62	374	.request_microcode_user = request_microcode_user,
ffc7e8ac	375	.request_microcode_fw = request_microcode_amd,
80cc9f10 PO	376	.collect_cpu_info = collect_cpu_info_amd,
	377	.apply_microcode = apply_microcode_amd,
	378	.microcode_fini_cpu = microcode_fini_cpu_amd,
	379	};
	380
18dbc916	381	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	382	{
96b0ee45 BP	383	patch = (void *)get_zeroed_page(GFP_KERNEL);
	384	if (!patch)
	385	return NULL;
	386
18dbc916	387	return &microcode_amd_ops;
80cc9f10	388	}
f72c1a57 BP	389
	390	void __exit exit_amd_microcode(void)
	391	{
96b0ee45	392	free_page((unsigned long)patch);
f72c1a57	393	}