perf_counter: x86: Expose INV and EDGE bits
[deliverable/linux.git] / arch / x86 / kernel / microcode_intel.c
CommitLineData
1da177e4
LT
1/*
2 * Intel CPU Microcode Update Driver for Linux
3 *
69688262 4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
9a3110bf 5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4
LT
6 *
7 * This driver allows to upgrade microcode on Intel processors
bc4e0f9a 8 * belonging to IA-32 family - PentiumPro, Pentium II,
1da177e4
LT
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
bc4e0f9a
BC
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/design/pentium4/manuals/253668.htm
1da177e4
LT
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
f516526f
PO
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
1da177e4
LT
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
bc4e0f9a 62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
1da177e4
LT
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
bc4e0f9a 67 * because we no longer hold a copy of applied microcode
1da177e4
LT
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
4bae1967 73#include <linux/platform_device.h>
a9415644 74#include <linux/capability.h>
4bae1967
IM
75#include <linux/miscdevice.h>
76#include <linux/firmware.h>
77149367 77#include <linux/smp_lock.h>
4bae1967 78#include <linux/spinlock.h>
5cf6c541 79#include <linux/cpumask.h>
4bae1967 80#include <linux/uaccess.h>
1da177e4 81#include <linux/vmalloc.h>
4bae1967
IM
82#include <linux/kernel.h>
83#include <linux/module.h>
14cc3e2b 84#include <linux/mutex.h>
4bae1967
IM
85#include <linux/sched.h>
86#include <linux/init.h>
87#include <linux/slab.h>
a30a6a2c 88#include <linux/cpu.h>
4bae1967
IM
89#include <linux/fs.h>
90#include <linux/mm.h>
1da177e4 91
9a56a0f8 92#include <asm/microcode.h>
4bae1967
IM
93#include <asm/processor.h>
94#include <asm/msr.h>
1da177e4 95
3e135d88 96MODULE_DESCRIPTION("Microcode Update Driver");
69688262 97MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
1da177e4
LT
98MODULE_LICENSE("GPL");
99
18dbc916
DA
100struct microcode_header_intel {
101 unsigned int hdrver;
102 unsigned int rev;
103 unsigned int date;
104 unsigned int sig;
105 unsigned int cksum;
106 unsigned int ldrver;
107 unsigned int pf;
108 unsigned int datasize;
109 unsigned int totalsize;
110 unsigned int reserved[3];
111};
112
113struct microcode_intel {
114 struct microcode_header_intel hdr;
115 unsigned int bits[0];
116};
117
118/* microcode format is extended from prescott processors */
119struct extended_signature {
120 unsigned int sig;
121 unsigned int pf;
122 unsigned int cksum;
123};
124
125struct extended_sigtable {
126 unsigned int count;
127 unsigned int cksum;
128 unsigned int reserved[3];
129 struct extended_signature sigs[0];
130};
131
4bae1967 132#define DEFAULT_UCODE_DATASIZE (2000)
f516526f
PO
133#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
134#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
135#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
136#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
3e135d88 137#define DWSIZE (sizeof(u32))
4bae1967 138
1da177e4 139#define get_totalsize(mc) \
d4ee3668
PO
140 (((struct microcode_intel *)mc)->hdr.totalsize ? \
141 ((struct microcode_intel *)mc)->hdr.totalsize : \
142 DEFAULT_UCODE_TOTALSIZE)
143
1da177e4 144#define get_datasize(mc) \
d4ee3668
PO
145 (((struct microcode_intel *)mc)->hdr.datasize ? \
146 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
1da177e4
LT
147
148#define sigmatch(s1, s2, p1, p2) \
149 (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
150
151#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
152
153/* serialize access to the physical write to MSR 0x79 */
154static DEFINE_SPINLOCK(microcode_update_lock);
155
d45de409 156static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 157{
92cb7612 158 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
280a9ca5 159 unsigned long flags;
1da177e4
LT
160 unsigned int val[2];
161
d45de409 162 memset(csig, 0, sizeof(*csig));
1da177e4
LT
163
164 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
3e135d88 165 cpu_has(c, X86_FEATURE_IA64)) {
9a3110bf
SL
166 printk(KERN_ERR "microcode: CPU%d not a capable Intel "
167 "processor\n", cpu_num);
d45de409 168 return -1;
9a3110bf 169 }
1da177e4 170
d45de409 171 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
172
173 if ((c->x86_model >= 5) || (c->x86 > 6)) {
174 /* get processor flags from MSR 0x17 */
175 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 176 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
177 }
178
280a9ca5
DA
179 /* serialize access to the physical write to MSR 0x79 */
180 spin_lock_irqsave(&microcode_update_lock, flags);
181
1da177e4 182 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
245067d1 183 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 184 sync_core();
1da177e4 185 /* get the current revision from MSR 0x8B */
d45de409 186 rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
280a9ca5
DA
187 spin_unlock_irqrestore(&microcode_update_lock, flags);
188
1da177e4 189 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
d45de409
DA
190 csig->sig, csig->pf, csig->rev);
191
192 return 0;
1da177e4
LT
193}
194
a0a29b62 195static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
1da177e4 196{
a0a29b62
DA
197 return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
198}
1da177e4 199
dd3feda7 200static inline int
4bae1967 201update_match_revision(struct microcode_header_intel *mc_header, int rev)
a0a29b62
DA
202{
203 return (mc_header->rev <= rev) ? 0 : 1;
1da177e4
LT
204}
205
8d86f390 206static int microcode_sanity_check(void *mc)
1da177e4 207{
4bae1967 208 unsigned long total_size, data_size, ext_table_size;
d4ee3668 209 struct microcode_header_intel *mc_header = mc;
9a3110bf 210 struct extended_sigtable *ext_header = NULL;
9a3110bf 211 int sum, orig_sum, ext_sigcount = 0, i;
4bae1967 212 struct extended_signature *ext_sig;
9a3110bf
SL
213
214 total_size = get_totalsize(mc_header);
215 data_size = get_datasize(mc_header);
4bae1967 216
bd8e39f9 217 if (data_size + MC_HEADER_SIZE > total_size) {
9a3110bf 218 printk(KERN_ERR "microcode: error! "
4bae1967 219 "Bad data size in microcode data file\n");
9a3110bf
SL
220 return -EINVAL;
221 }
1da177e4 222
9a3110bf
SL
223 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
224 printk(KERN_ERR "microcode: error! "
4bae1967 225 "Unknown microcode update format\n");
9a3110bf
SL
226 return -EINVAL;
227 }
228 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
229 if (ext_table_size) {
230 if ((ext_table_size < EXT_HEADER_SIZE)
231 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
232 printk(KERN_ERR "microcode: error! "
233 "Small exttable size in microcode data file\n");
234 return -EINVAL;
1da177e4 235 }
9a3110bf
SL
236 ext_header = mc + MC_HEADER_SIZE + data_size;
237 if (ext_table_size != exttable_size(ext_header)) {
238 printk(KERN_ERR "microcode: error! "
239 "Bad exttable size in microcode data file\n");
240 return -EFAULT;
1da177e4 241 }
9a3110bf
SL
242 ext_sigcount = ext_header->count;
243 }
1da177e4 244
9a3110bf
SL
245 /* check extended table checksum */
246 if (ext_table_size) {
247 int ext_table_sum = 0;
9a4b9efa 248 int *ext_tablep = (int *)ext_header;
9a3110bf
SL
249
250 i = ext_table_size / DWSIZE;
251 while (i--)
252 ext_table_sum += ext_tablep[i];
253 if (ext_table_sum) {
254 printk(KERN_WARNING "microcode: aborting, "
255 "bad extended signature table checksum\n");
256 return -EINVAL;
1da177e4 257 }
9a3110bf 258 }
1da177e4 259
9a3110bf
SL
260 /* calculate the checksum */
261 orig_sum = 0;
262 i = (MC_HEADER_SIZE + data_size) / DWSIZE;
263 while (i--)
264 orig_sum += ((int *)mc)[i];
265 if (orig_sum) {
266 printk(KERN_ERR "microcode: aborting, bad checksum\n");
267 return -EINVAL;
268 }
269 if (!ext_table_size)
270 return 0;
271 /* check extended signature checksum */
272 for (i = 0; i < ext_sigcount; i++) {
ade1af77
JE
273 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
274 EXT_SIGNATURE_SIZE * i;
9a3110bf
SL
275 sum = orig_sum
276 - (mc_header->sig + mc_header->pf + mc_header->cksum)
277 + (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
278 if (sum) {
279 printk(KERN_ERR "microcode: aborting, bad checksum\n");
280 return -EINVAL;
1da177e4 281 }
9a3110bf
SL
282 }
283 return 0;
284}
5cf6c541 285
9a3110bf
SL
286/*
287 * return 0 - no update found
288 * return 1 - found update
9a3110bf 289 */
a0a29b62
DA
290static int
291get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
9a3110bf 292{
d4ee3668 293 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
294 struct extended_sigtable *ext_header;
295 unsigned long total_size = get_totalsize(mc_header);
296 int ext_sigcount, i;
297 struct extended_signature *ext_sig;
9a3110bf 298
a0a29b62
DA
299 if (!update_match_revision(mc_header, rev))
300 return 0;
301
302 if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
303 return 1;
9a3110bf 304
a0a29b62 305 /* Look for ext. headers: */
9a3110bf
SL
306 if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
307 return 0;
308
ade1af77 309 ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
9a3110bf 310 ext_sigcount = ext_header->count;
ade1af77 311 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
a0a29b62 312
9a3110bf 313 for (i = 0; i < ext_sigcount; i++) {
a0a29b62
DA
314 if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
315 return 1;
9a3110bf
SL
316 ext_sig++;
317 }
318 return 0;
1da177e4
LT
319}
320
8d86f390 321static void apply_microcode(int cpu)
1da177e4 322{
4bae1967
IM
323 struct microcode_intel *mc_intel;
324 struct ucode_cpu_info *uci;
1da177e4
LT
325 unsigned long flags;
326 unsigned int val[2];
4bae1967
IM
327 int cpu_num;
328
329 cpu_num = raw_smp_processor_id();
330 uci = ucode_cpu_info + cpu;
331 mc_intel = uci->mc;
1da177e4 332
9a3110bf
SL
333 /* We should bind the task to the CPU */
334 BUG_ON(cpu_num != cpu);
335
18dbc916 336 if (mc_intel == NULL)
1da177e4 337 return;
1da177e4
LT
338
339 /* serialize access to the physical write to MSR 0x79 */
bc4e0f9a 340 spin_lock_irqsave(&microcode_update_lock, flags);
1da177e4
LT
341
342 /* write microcode via MSR 0x79 */
343 wrmsr(MSR_IA32_UCODE_WRITE,
18dbc916
DA
344 (unsigned long) mc_intel->bits,
345 (unsigned long) mc_intel->bits >> 16 >> 16);
1da177e4
LT
346 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
347
245067d1 348 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 349 sync_core();
245067d1 350
1da177e4
LT
351 /* get the current revision from MSR 0x8B */
352 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
353
1da177e4 354 spin_unlock_irqrestore(&microcode_update_lock, flags);
18dbc916 355 if (val[1] != mc_intel->hdr.rev) {
fe176de0 356 printk(KERN_ERR "microcode: CPU%d update from revision "
4bae1967
IM
357 "0x%x to 0x%x failed\n",
358 cpu_num, uci->cpu_sig.rev, val[1]);
9a3110bf
SL
359 return;
360 }
fe176de0 361 printk(KERN_INFO "microcode: CPU%d updated from revision "
4bae1967 362 "0x%x to 0x%x, date = %04x-%02x-%02x \n",
d45de409 363 cpu_num, uci->cpu_sig.rev, val[1],
18dbc916
DA
364 mc_intel->hdr.date & 0xffff,
365 mc_intel->hdr.date >> 24,
366 (mc_intel->hdr.date >> 16) & 0xff);
4bae1967 367
d45de409 368 uci->cpu_sig.rev = val[1];
1da177e4
LT
369}
370
a0a29b62
DA
371static int generic_load_microcode(int cpu, void *data, size_t size,
372 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 373{
a0a29b62
DA
374 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
375 u8 *ucode_ptr = data, *new_mc = NULL, *mc;
376 int new_rev = uci->cpu_sig.rev;
377 unsigned int leftover = size;
9a3110bf 378
a0a29b62
DA
379 while (leftover) {
380 struct microcode_header_intel mc_header;
381 unsigned int mc_size;
9a3110bf 382
a0a29b62
DA
383 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
384 break;
a30a6a2c 385
a0a29b62
DA
386 mc_size = get_totalsize(&mc_header);
387 if (!mc_size || mc_size > leftover) {
388 printk(KERN_ERR "microcode: error!"
389 "Bad data in microcode data file\n");
390 break;
391 }
a30a6a2c 392
a0a29b62
DA
393 mc = vmalloc(mc_size);
394 if (!mc)
395 break;
396
397 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
398 microcode_sanity_check(mc) < 0) {
399 vfree(mc);
400 break;
401 }
402
403 if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
a1c75cc5
IM
404 if (new_mc)
405 vfree(new_mc);
a0a29b62
DA
406 new_rev = mc_header.rev;
407 new_mc = mc;
408 } else
409 vfree(mc);
410
411 ucode_ptr += mc_size;
412 leftover -= mc_size;
a30a6a2c
SL
413 }
414
4bae1967
IM
415 if (!new_mc)
416 goto out;
417
418 if (leftover) {
419 vfree(new_mc);
420 goto out;
a30a6a2c 421 }
a0a29b62 422
4bae1967
IM
423 if (uci->mc)
424 vfree(uci->mc);
425 uci->mc = (struct microcode_intel *)new_mc;
426
427 pr_debug("microcode: CPU%d found a matching microcode update with"
428 " version 0x%x (current=0x%x)\n",
429 cpu, new_rev, uci->cpu_sig.rev);
430
431 out:
a0a29b62 432 return (int)leftover;
a30a6a2c
SL
433}
434
a0a29b62
DA
435static int get_ucode_fw(void *to, const void *from, size_t n)
436{
437 memcpy(to, from, n);
438 return 0;
439}
a30a6a2c 440
a0a29b62 441static int request_microcode_fw(int cpu, struct device *device)
a30a6a2c
SL
442{
443 char name[30];
92cb7612 444 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 445 const struct firmware *firmware;
a0a29b62 446 int ret;
a30a6a2c
SL
447
448 /* We should bind the task to the CPU */
449 BUG_ON(cpu != raw_smp_processor_id());
3e135d88 450 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 451 c->x86, c->x86_model, c->x86_mask);
a0a29b62
DA
452 ret = request_firmware(&firmware, name, device);
453 if (ret) {
bc4e0f9a 454 pr_debug("microcode: data file %s load failed\n", name);
a0a29b62 455 return ret;
a30a6a2c 456 }
a0a29b62 457
dd3feda7
JSR
458 ret = generic_load_microcode(cpu, (void *)firmware->data,
459 firmware->size, &get_ucode_fw);
a0a29b62 460
a30a6a2c
SL
461 release_firmware(firmware);
462
a0a29b62
DA
463 return ret;
464}
465
466static int get_ucode_user(void *to, const void *from, size_t n)
467{
468 return copy_from_user(to, from, n);
469}
470
471static int request_microcode_user(int cpu, const void __user *buf, size_t size)
472{
473 /* We should bind the task to the CPU */
474 BUG_ON(cpu != raw_smp_processor_id());
475
dd3feda7 476 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
a30a6a2c
SL
477}
478
8d86f390 479static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
480{
481 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
482
18dbc916
DA
483 vfree(uci->mc);
484 uci->mc = NULL;
a30a6a2c 485}
8d86f390 486
4db646b1 487static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
488 .request_microcode_user = request_microcode_user,
489 .request_microcode_fw = request_microcode_fw,
8d86f390
PO
490 .collect_cpu_info = collect_cpu_info,
491 .apply_microcode = apply_microcode,
492 .microcode_fini_cpu = microcode_fini_cpu,
493};
494
18dbc916 495struct microcode_ops * __init init_intel_microcode(void)
8d86f390 496{
18dbc916 497 return &microcode_intel_ops;
8d86f390
PO
498}
499
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