Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/acpi.h> | |
19 | #include <linux/delay.h> | |
1da177e4 | 20 | #include <linux/bootmem.h> |
1da177e4 LT |
21 | #include <linux/kernel_stat.h> |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/bitops.h> | |
24 | ||
25 | #include <asm/smp.h> | |
26 | #include <asm/acpi.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/mpspec.h> | |
29 | #include <asm/io_apic.h> | |
ce3fe6b2 | 30 | #include <asm/bios_ebda.h> |
1da177e4 LT |
31 | |
32 | #include <mach_apic.h> | |
874c4fe3 | 33 | #include <mach_apicdef.h> |
1da177e4 | 34 | #include <mach_mpparse.h> |
1da177e4 LT |
35 | |
36 | /* Have we found an MP table */ | |
37 | int smp_found_config; | |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
c0a282c2 | 43 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 44 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
c0a282c2 | 45 | #endif |
a6333c3c | 46 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
4ef81297 | 47 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
48 | static int mp_current_pci_id; |
49 | ||
1da177e4 | 50 | int pic_mode; |
1da177e4 | 51 | |
1da177e4 LT |
52 | /* |
53 | * Intel MP BIOS table parsing routines: | |
54 | */ | |
55 | ||
1da177e4 LT |
56 | /* |
57 | * Checksum an MP configuration block. | |
58 | */ | |
59 | ||
60 | static int __init mpf_checksum(unsigned char *mp, int len) | |
61 | { | |
62 | int sum = 0; | |
63 | ||
64 | while (len--) | |
65 | sum += *mp++; | |
66 | ||
67 | return sum & 0xFF; | |
68 | } | |
69 | ||
86420506 | 70 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 LT |
71 | /* |
72 | * Have to match translation table entries to main table entries by counter | |
73 | * hence the mpc_record variable .... can't see a less disgusting way of | |
74 | * doing this .... | |
75 | */ | |
76 | ||
4ef81297 AS |
77 | static int mpc_record; |
78 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] | |
79 | __cpuinitdata; | |
86420506 | 80 | #endif |
1da177e4 | 81 | |
c853c676 AS |
82 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
83 | { | |
84 | int apicid; | |
85 | ||
7b1292e2 GC |
86 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
87 | disabled_cpus++; | |
1da177e4 | 88 | return; |
7b1292e2 | 89 | } |
4655c7de | 90 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 91 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
4655c7de AS |
92 | #else |
93 | Dprintk("Processor #%d %u:%u APIC version %d\n", | |
94 | m->mpc_apicid, | |
95 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, | |
4ef81297 | 96 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, m->mpc_apicver); |
4655c7de AS |
97 | apicid = m->mpc_apicid; |
98 | #endif | |
1da177e4 | 99 | |
4ef81297 | 100 | if (m->mpc_featureflag & (1 << 0)) |
1da177e4 | 101 | Dprintk(" Floating point unit present.\n"); |
4ef81297 | 102 | if (m->mpc_featureflag & (1 << 7)) |
1da177e4 | 103 | Dprintk(" Machine Exception supported.\n"); |
4ef81297 | 104 | if (m->mpc_featureflag & (1 << 8)) |
1da177e4 | 105 | Dprintk(" 64 bit compare & exchange supported.\n"); |
4ef81297 | 106 | if (m->mpc_featureflag & (1 << 9)) |
1da177e4 | 107 | Dprintk(" Internal APIC present.\n"); |
4ef81297 | 108 | if (m->mpc_featureflag & (1 << 11)) |
1da177e4 | 109 | Dprintk(" SEP present.\n"); |
4ef81297 | 110 | if (m->mpc_featureflag & (1 << 12)) |
1da177e4 | 111 | Dprintk(" MTRR present.\n"); |
4ef81297 | 112 | if (m->mpc_featureflag & (1 << 13)) |
1da177e4 | 113 | Dprintk(" PGE present.\n"); |
4ef81297 | 114 | if (m->mpc_featureflag & (1 << 14)) |
1da177e4 | 115 | Dprintk(" MCA present.\n"); |
4ef81297 | 116 | if (m->mpc_featureflag & (1 << 15)) |
1da177e4 | 117 | Dprintk(" CMOV present.\n"); |
4ef81297 | 118 | if (m->mpc_featureflag & (1 << 16)) |
1da177e4 | 119 | Dprintk(" PAT present.\n"); |
4ef81297 | 120 | if (m->mpc_featureflag & (1 << 17)) |
1da177e4 | 121 | Dprintk(" PSE present.\n"); |
4ef81297 | 122 | if (m->mpc_featureflag & (1 << 18)) |
1da177e4 | 123 | Dprintk(" PSN present.\n"); |
4ef81297 | 124 | if (m->mpc_featureflag & (1 << 19)) |
1da177e4 LT |
125 | Dprintk(" Cache Line Flush Instruction present.\n"); |
126 | /* 20 Reserved */ | |
4ef81297 | 127 | if (m->mpc_featureflag & (1 << 21)) |
1da177e4 | 128 | Dprintk(" Debug Trace and EMON Store present.\n"); |
4ef81297 | 129 | if (m->mpc_featureflag & (1 << 22)) |
1da177e4 | 130 | Dprintk(" ACPI Thermal Throttle Registers present.\n"); |
4ef81297 | 131 | if (m->mpc_featureflag & (1 << 23)) |
1da177e4 | 132 | Dprintk(" MMX present.\n"); |
4ef81297 | 133 | if (m->mpc_featureflag & (1 << 24)) |
1da177e4 | 134 | Dprintk(" FXSR present.\n"); |
4ef81297 | 135 | if (m->mpc_featureflag & (1 << 25)) |
1da177e4 | 136 | Dprintk(" XMM present.\n"); |
4ef81297 | 137 | if (m->mpc_featureflag & (1 << 26)) |
1da177e4 | 138 | Dprintk(" Willamette New Instructions present.\n"); |
4ef81297 | 139 | if (m->mpc_featureflag & (1 << 27)) |
1da177e4 | 140 | Dprintk(" Self Snoop present.\n"); |
4ef81297 | 141 | if (m->mpc_featureflag & (1 << 28)) |
1da177e4 | 142 | Dprintk(" HT present.\n"); |
4ef81297 | 143 | if (m->mpc_featureflag & (1 << 29)) |
1da177e4 LT |
144 | Dprintk(" Thermal Monitor present.\n"); |
145 | /* 30, 31 Reserved */ | |
146 | ||
1da177e4 LT |
147 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
148 | Dprintk(" Bootup CPU\n"); | |
149 | boot_cpu_physical_apicid = m->mpc_apicid; | |
1da177e4 LT |
150 | } |
151 | ||
c853c676 | 152 | generic_processor_info(apicid, m->mpc_apicver); |
1da177e4 LT |
153 | } |
154 | ||
4ef81297 | 155 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
156 | { |
157 | char str[7]; | |
158 | ||
159 | memcpy(str, m->mpc_bustype, 6); | |
160 | str[6] = 0; | |
161 | ||
0ec153af | 162 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 163 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
0ec153af AS |
164 | #else |
165 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
166 | #endif | |
1da177e4 | 167 | |
5e4edbb7 | 168 | #if MAX_MP_BUSSES < 256 |
c0ec31ad RD |
169 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
170 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " | |
4ef81297 AS |
171 | " is too large, max. supported is %d\n", |
172 | m->mpc_busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
173 | return; |
174 | } | |
5e4edbb7 | 175 | #endif |
c0ec31ad | 176 | |
a6333c3c | 177 | set_bit(m->mpc_busid, mp_bus_not_pci); |
4ef81297 | 178 | if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { |
d285e338 | 179 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 180 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
d285e338 | 181 | #endif |
a6333c3c | 182 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
183 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
184 | mp_current_pci_id++; | |
c0a282c2 AS |
185 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) |
186 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; | |
4ef81297 | 187 | } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
9e0a2de2 | 188 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; |
4ef81297 | 189 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
9e0a2de2 | 190 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; |
4ef81297 | 191 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) { |
1da177e4 | 192 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; |
1da177e4 LT |
193 | } else { |
194 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
c0a282c2 | 195 | #endif |
1da177e4 LT |
196 | } |
197 | } | |
198 | ||
61048c63 AS |
199 | #ifdef CONFIG_X86_IO_APIC |
200 | ||
857033a6 AS |
201 | static int bad_ioapic(unsigned long address) |
202 | { | |
203 | if (nr_ioapics >= MAX_IO_APICS) { | |
204 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
205 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
206 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
207 | } | |
208 | if (!address) { | |
209 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
210 | " found in table, skipping!\n"); | |
211 | return 1; | |
212 | } | |
213 | return 0; | |
214 | } | |
215 | ||
4ef81297 | 216 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
217 | { |
218 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
219 | return; | |
220 | ||
64883ab0 | 221 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
4ef81297 | 222 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
857033a6 AS |
223 | |
224 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 225 | return; |
857033a6 | 226 | |
1da177e4 LT |
227 | mp_ioapics[nr_ioapics] = *m; |
228 | nr_ioapics++; | |
229 | } | |
230 | ||
4ef81297 | 231 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 232 | { |
4ef81297 | 233 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
234 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
235 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
4ef81297 AS |
236 | m->mpc_irqtype, m->mpc_irqflag & 3, |
237 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
238 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
1da177e4 LT |
239 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
240 | panic("Max # of irq sources exceeded!!\n"); | |
241 | } | |
242 | ||
61048c63 AS |
243 | #endif |
244 | ||
4ef81297 | 245 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
246 | { |
247 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
248 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
4ef81297 AS |
249 | m->mpc_irqtype, m->mpc_irqflag & 3, |
250 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
251 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
252 | } |
253 | ||
254 | #ifdef CONFIG_X86_NUMAQ | |
4ef81297 | 255 | static void __init MP_translation_info(struct mpc_config_translation *m) |
1da177e4 | 256 | { |
4ef81297 AS |
257 | printk(KERN_INFO |
258 | "Translation: record %d, type %d, quad %d, global %d, local %d\n", | |
259 | mpc_record, m->trans_type, m->trans_quad, m->trans_global, | |
260 | m->trans_local); | |
1da177e4 | 261 | |
4ef81297 | 262 | if (mpc_record >= MAX_MPC_ENTRY) |
1da177e4 LT |
263 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); |
264 | else | |
4ef81297 | 265 | translation_table[mpc_record] = m; /* stash this for later */ |
1da177e4 LT |
266 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
267 | node_set_online(m->trans_quad); | |
268 | } | |
269 | ||
270 | /* | |
271 | * Read/parse the MPC oem tables | |
272 | */ | |
273 | ||
4ef81297 AS |
274 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, |
275 | unsigned short oemsize) | |
1da177e4 | 276 | { |
4ef81297 AS |
277 | int count = sizeof(*oemtable); /* the header size */ |
278 | unsigned char *oemptr = ((unsigned char *)oemtable) + count; | |
279 | ||
1da177e4 | 280 | mpc_record = 0; |
4ef81297 AS |
281 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", |
282 | oemtable); | |
283 | if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) { | |
284 | printk(KERN_WARNING | |
285 | "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
286 | oemtable->oem_signature[0], oemtable->oem_signature[1], | |
287 | oemtable->oem_signature[2], oemtable->oem_signature[3]); | |
1da177e4 LT |
288 | return; |
289 | } | |
4ef81297 | 290 | if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) { |
1da177e4 LT |
291 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
292 | return; | |
293 | } | |
294 | while (count < oemtable->oem_length) { | |
295 | switch (*oemptr) { | |
4ef81297 | 296 | case MP_TRANSLATION: |
1da177e4 | 297 | { |
4ef81297 AS |
298 | struct mpc_config_translation *m = |
299 | (struct mpc_config_translation *)oemptr; | |
1da177e4 LT |
300 | MP_translation_info(m); |
301 | oemptr += sizeof(*m); | |
302 | count += sizeof(*m); | |
303 | ++mpc_record; | |
304 | break; | |
305 | } | |
4ef81297 | 306 | default: |
1da177e4 | 307 | { |
4ef81297 AS |
308 | printk(KERN_WARNING |
309 | "Unrecognised OEM table entry type! - %d\n", | |
310 | (int)*oemptr); | |
1da177e4 LT |
311 | return; |
312 | } | |
313 | } | |
4ef81297 | 314 | } |
1da177e4 LT |
315 | } |
316 | ||
317 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, | |
4ef81297 | 318 | char *productid) |
1da177e4 LT |
319 | { |
320 | if (strncmp(oem, "IBM NUMA", 8)) | |
321 | printk("Warning! May not be a NUMA-Q system!\n"); | |
322 | if (mpc->mpc_oemptr) | |
4ef81297 AS |
323 | smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr, |
324 | mpc->mpc_oemsize); | |
1da177e4 | 325 | } |
4ef81297 | 326 | #endif /* CONFIG_X86_NUMAQ */ |
1da177e4 LT |
327 | |
328 | /* | |
329 | * Read/parse the MPC | |
330 | */ | |
331 | ||
332 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
333 | { | |
334 | char str[16]; | |
335 | char oem[10]; | |
4ef81297 AS |
336 | int count = sizeof(*mpc); |
337 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
1da177e4 | 338 | |
4ef81297 | 339 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { |
1da177e4 | 340 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", |
4ef81297 | 341 | *(u32 *) mpc->mpc_signature); |
1da177e4 LT |
342 | return 0; |
343 | } | |
4ef81297 | 344 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
1da177e4 LT |
345 | printk(KERN_ERR "SMP mptable: checksum error!\n"); |
346 | return 0; | |
347 | } | |
4ef81297 | 348 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
1da177e4 | 349 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", |
4ef81297 | 350 | mpc->mpc_spec); |
1da177e4 LT |
351 | return 0; |
352 | } | |
353 | if (!mpc->mpc_lapic) { | |
354 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); | |
355 | return 0; | |
356 | } | |
4ef81297 AS |
357 | memcpy(oem, mpc->mpc_oem, 8); |
358 | oem[8] = 0; | |
359 | printk(KERN_INFO "OEM ID: %s ", oem); | |
1da177e4 | 360 | |
4ef81297 AS |
361 | memcpy(str, mpc->mpc_productid, 12); |
362 | str[12] = 0; | |
363 | printk("Product ID: %s ", str); | |
1da177e4 LT |
364 | |
365 | mps_oem_check(mpc, oem, str); | |
366 | ||
64883ab0 | 367 | printk("APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 | 368 | |
64883ab0 | 369 | /* |
1da177e4 LT |
370 | * Save the local APIC address (it might be non-default) -- but only |
371 | * if we're not using ACPI. | |
372 | */ | |
373 | if (!acpi_lapic) | |
374 | mp_lapic_addr = mpc->mpc_lapic; | |
375 | ||
376 | /* | |
4ef81297 | 377 | * Now process the configuration blocks. |
1da177e4 | 378 | */ |
86420506 | 379 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 380 | mpc_record = 0; |
86420506 | 381 | #endif |
1da177e4 | 382 | while (count < mpc->mpc_length) { |
4ef81297 AS |
383 | switch (*mpt) { |
384 | case MP_PROCESSOR: | |
1da177e4 | 385 | { |
4ef81297 AS |
386 | struct mpc_config_processor *m = |
387 | (struct mpc_config_processor *)mpt; | |
1da177e4 LT |
388 | /* ACPI may have already provided this data */ |
389 | if (!acpi_lapic) | |
390 | MP_processor_info(m); | |
391 | mpt += sizeof(*m); | |
392 | count += sizeof(*m); | |
393 | break; | |
394 | } | |
4ef81297 | 395 | case MP_BUS: |
1da177e4 | 396 | { |
4ef81297 AS |
397 | struct mpc_config_bus *m = |
398 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
399 | MP_bus_info(m); |
400 | mpt += sizeof(*m); | |
401 | count += sizeof(*m); | |
402 | break; | |
403 | } | |
4ef81297 | 404 | case MP_IOAPIC: |
1da177e4 | 405 | { |
61048c63 | 406 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
407 | struct mpc_config_ioapic *m = |
408 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 409 | MP_ioapic_info(m); |
61048c63 | 410 | #endif |
4ef81297 AS |
411 | mpt += sizeof(struct mpc_config_ioapic); |
412 | count += sizeof(struct mpc_config_ioapic); | |
1da177e4 LT |
413 | break; |
414 | } | |
4ef81297 | 415 | case MP_INTSRC: |
1da177e4 | 416 | { |
61048c63 | 417 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
418 | struct mpc_config_intsrc *m = |
419 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
420 | |
421 | MP_intsrc_info(m); | |
61048c63 | 422 | #endif |
4ef81297 AS |
423 | mpt += sizeof(struct mpc_config_intsrc); |
424 | count += sizeof(struct mpc_config_intsrc); | |
1da177e4 LT |
425 | break; |
426 | } | |
4ef81297 | 427 | case MP_LINTSRC: |
1da177e4 | 428 | { |
4ef81297 AS |
429 | struct mpc_config_lintsrc *m = |
430 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 431 | MP_lintsrc_info(m); |
4ef81297 AS |
432 | mpt += sizeof(*m); |
433 | count += sizeof(*m); | |
1da177e4 LT |
434 | break; |
435 | } | |
4ef81297 | 436 | default: |
1da177e4 LT |
437 | { |
438 | count = mpc->mpc_length; | |
439 | break; | |
440 | } | |
441 | } | |
86420506 | 442 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 443 | ++mpc_record; |
86420506 | 444 | #endif |
1da177e4 | 445 | } |
3c43f039 | 446 | setup_apic_routing(); |
1da177e4 LT |
447 | if (!num_processors) |
448 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); | |
449 | return num_processors; | |
450 | } | |
451 | ||
61048c63 AS |
452 | #ifdef CONFIG_X86_IO_APIC |
453 | ||
1da177e4 LT |
454 | static int __init ELCR_trigger(unsigned int irq) |
455 | { | |
456 | unsigned int port; | |
457 | ||
458 | port = 0x4d0 + (irq >> 3); | |
459 | return (inb(port) >> (irq & 7)) & 1; | |
460 | } | |
461 | ||
462 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
463 | { | |
464 | struct mpc_config_intsrc intsrc; | |
465 | int i; | |
466 | int ELCR_fallback = 0; | |
467 | ||
468 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 469 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
470 | intsrc.mpc_srcbus = 0; |
471 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
472 | ||
473 | intsrc.mpc_irqtype = mp_INT; | |
474 | ||
475 | /* | |
476 | * If true, we have an ISA/PCI system with no IRQ entries | |
477 | * in the MP table. To prevent the PCI interrupts from being set up | |
478 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
479 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
480 | * never be level sensitive, so we simply see if the ELCR agrees. | |
481 | * If it does, we assume it's valid. | |
482 | */ | |
483 | if (mpc_default_type == 5) { | |
4ef81297 AS |
484 | printk(KERN_INFO |
485 | "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
1da177e4 | 486 | |
4ef81297 AS |
487 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) |
488 | || ELCR_trigger(13)) | |
489 | printk(KERN_WARNING | |
490 | "ELCR contains invalid data... not using ELCR\n"); | |
1da177e4 | 491 | else { |
4ef81297 AS |
492 | printk(KERN_INFO |
493 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
494 | ELCR_fallback = 1; |
495 | } | |
496 | } | |
497 | ||
498 | for (i = 0; i < 16; i++) { | |
499 | switch (mpc_default_type) { | |
500 | case 2: | |
501 | if (i == 0 || i == 13) | |
502 | continue; /* IRQ0 & IRQ13 not connected */ | |
503 | /* fall through */ | |
504 | default: | |
505 | if (i == 2) | |
506 | continue; /* IRQ2 is never connected */ | |
507 | } | |
508 | ||
509 | if (ELCR_fallback) { | |
510 | /* | |
511 | * If the ELCR indicates a level-sensitive interrupt, we | |
512 | * copy that information over to the MP table in the | |
513 | * irqflag field (level sensitive, active high polarity). | |
514 | */ | |
515 | if (ELCR_trigger(i)) | |
516 | intsrc.mpc_irqflag = 13; | |
517 | else | |
518 | intsrc.mpc_irqflag = 0; | |
519 | } | |
520 | ||
521 | intsrc.mpc_srcbusirq = i; | |
4ef81297 | 522 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
523 | MP_intsrc_info(&intsrc); |
524 | } | |
525 | ||
526 | intsrc.mpc_irqtype = mp_ExtINT; | |
527 | intsrc.mpc_srcbusirq = 0; | |
4ef81297 | 528 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
529 | MP_intsrc_info(&intsrc); |
530 | } | |
531 | ||
61048c63 AS |
532 | #endif |
533 | ||
1da177e4 LT |
534 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) |
535 | { | |
536 | struct mpc_config_processor processor; | |
537 | struct mpc_config_bus bus; | |
61048c63 | 538 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 539 | struct mpc_config_ioapic ioapic; |
61048c63 | 540 | #endif |
1da177e4 LT |
541 | struct mpc_config_lintsrc lintsrc; |
542 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
543 | int i; | |
544 | ||
545 | /* | |
546 | * local APIC has default address | |
547 | */ | |
548 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
549 | ||
550 | /* | |
551 | * 2 CPUs, numbered 0 & 1. | |
552 | */ | |
553 | processor.mpc_type = MP_PROCESSOR; | |
554 | /* Either an integrated APIC or a discrete 82489DX. */ | |
555 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
556 | processor.mpc_cpuflag = CPU_ENABLED; | |
557 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
4ef81297 | 558 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
1da177e4 LT |
559 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
560 | processor.mpc_reserved[0] = 0; | |
561 | processor.mpc_reserved[1] = 0; | |
562 | for (i = 0; i < 2; i++) { | |
563 | processor.mpc_apicid = i; | |
564 | MP_processor_info(&processor); | |
565 | } | |
566 | ||
567 | bus.mpc_type = MP_BUS; | |
568 | bus.mpc_busid = 0; | |
569 | switch (mpc_default_type) { | |
4ef81297 AS |
570 | default: |
571 | printk("???\n"); | |
572 | printk(KERN_ERR "Unknown standard configuration %d\n", | |
573 | mpc_default_type); | |
574 | /* fall through */ | |
575 | case 1: | |
576 | case 5: | |
577 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
578 | break; | |
579 | case 2: | |
580 | case 6: | |
581 | case 3: | |
582 | memcpy(bus.mpc_bustype, "EISA ", 6); | |
583 | break; | |
584 | case 4: | |
585 | case 7: | |
586 | memcpy(bus.mpc_bustype, "MCA ", 6); | |
1da177e4 LT |
587 | } |
588 | MP_bus_info(&bus); | |
589 | if (mpc_default_type > 4) { | |
590 | bus.mpc_busid = 1; | |
591 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
592 | MP_bus_info(&bus); | |
593 | } | |
594 | ||
61048c63 | 595 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
596 | ioapic.mpc_type = MP_IOAPIC; |
597 | ioapic.mpc_apicid = 2; | |
598 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
599 | ioapic.mpc_flags = MPC_APIC_USABLE; | |
600 | ioapic.mpc_apicaddr = 0xFEC00000; | |
601 | MP_ioapic_info(&ioapic); | |
602 | ||
603 | /* | |
604 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
605 | */ | |
606 | construct_default_ioirq_mptable(mpc_default_type); | |
61048c63 | 607 | #endif |
1da177e4 | 608 | lintsrc.mpc_type = MP_LINTSRC; |
4ef81297 | 609 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
610 | lintsrc.mpc_srcbusid = 0; |
611 | lintsrc.mpc_srcbusirq = 0; | |
612 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
613 | for (i = 0; i < 2; i++) { | |
614 | lintsrc.mpc_irqtype = linttypes[i]; | |
615 | lintsrc.mpc_destapiclint = i; | |
616 | MP_lintsrc_info(&lintsrc); | |
617 | } | |
618 | } | |
619 | ||
620 | static struct intel_mp_floating *mpf_found; | |
621 | ||
622 | /* | |
623 | * Scan the memory blocks for an SMP configuration block. | |
624 | */ | |
4ef81297 | 625 | void __init get_smp_config(void) |
1da177e4 LT |
626 | { |
627 | struct intel_mp_floating *mpf = mpf_found; | |
628 | ||
629 | /* | |
4ef81297 | 630 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
1da177e4 LT |
631 | * processors, where MPS only supports physical. |
632 | */ | |
633 | if (acpi_lapic && acpi_ioapic) { | |
4ef81297 AS |
634 | printk(KERN_INFO |
635 | "Using ACPI (MADT) for SMP configuration information\n"); | |
1da177e4 | 636 | return; |
4ef81297 AS |
637 | } else if (acpi_lapic) |
638 | printk(KERN_INFO | |
639 | "Using ACPI for processor (LAPIC) configuration information\n"); | |
1da177e4 | 640 | |
4ef81297 AS |
641 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
642 | mpf->mpf_specification); | |
643 | if (mpf->mpf_feature2 & (1 << 7)) { | |
1da177e4 LT |
644 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
645 | pic_mode = 1; | |
646 | } else { | |
647 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
648 | pic_mode = 0; | |
649 | } | |
650 | ||
651 | /* | |
652 | * Now see if we need to read further. | |
653 | */ | |
654 | if (mpf->mpf_feature1 != 0) { | |
655 | ||
4ef81297 AS |
656 | printk(KERN_INFO "Default MP configuration #%d\n", |
657 | mpf->mpf_feature1); | |
1da177e4 LT |
658 | construct_default_ISA_mptable(mpf->mpf_feature1); |
659 | ||
660 | } else if (mpf->mpf_physptr) { | |
661 | ||
662 | /* | |
663 | * Read the physical hardware table. Anything here will | |
664 | * override the defaults. | |
665 | */ | |
7d4c8e56 | 666 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 | 667 | smp_found_config = 0; |
4ef81297 AS |
668 | printk(KERN_ERR |
669 | "BIOS bug, MP table errors detected!...\n"); | |
670 | printk(KERN_ERR | |
671 | "... disabling SMP support. (tell your hw vendor)\n"); | |
1da177e4 LT |
672 | return; |
673 | } | |
61048c63 AS |
674 | |
675 | #ifdef CONFIG_X86_IO_APIC | |
1da177e4 LT |
676 | /* |
677 | * If there are no explicit MP IRQ entries, then we are | |
678 | * broken. We set up most of the low 16 IO-APIC pins to | |
679 | * ISA defaults and hope it will work. | |
680 | */ | |
681 | if (!mp_irq_entries) { | |
682 | struct mpc_config_bus bus; | |
683 | ||
4ef81297 AS |
684 | printk(KERN_ERR |
685 | "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
1da177e4 LT |
686 | |
687 | bus.mpc_type = MP_BUS; | |
688 | bus.mpc_busid = 0; | |
689 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
690 | MP_bus_info(&bus); | |
691 | ||
692 | construct_default_ioirq_mptable(0); | |
693 | } | |
61048c63 | 694 | #endif |
1da177e4 LT |
695 | } else |
696 | BUG(); | |
697 | ||
698 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
699 | /* | |
700 | * Only use the first configuration found. | |
701 | */ | |
702 | } | |
703 | ||
4ef81297 | 704 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 LT |
705 | { |
706 | unsigned long *bp = phys_to_virt(base); | |
707 | struct intel_mp_floating *mpf; | |
708 | ||
4ef81297 | 709 | printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
710 | if (sizeof(*mpf) != 16) |
711 | printk("Error: MPF size\n"); | |
712 | ||
713 | while (length > 0) { | |
714 | mpf = (struct intel_mp_floating *)bp; | |
715 | if ((*bp == SMP_MAGIC_IDENT) && | |
4ef81297 AS |
716 | (mpf->mpf_length == 1) && |
717 | !mpf_checksum((unsigned char *)bp, 16) && | |
718 | ((mpf->mpf_specification == 1) | |
719 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
720 | |
721 | smp_found_config = 1; | |
e91a3b43 | 722 | printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", |
4ef81297 | 723 | mpf, virt_to_phys(mpf)); |
72a7fe39 BW |
724 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, |
725 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
726 | if (mpf->mpf_physptr) { |
727 | /* | |
728 | * We cannot access to MPC table to compute | |
729 | * table size yet, as only few megabytes from | |
730 | * the bottom is mapped now. | |
731 | * PC-9800's MPC table places on the very last | |
732 | * of physical memory; so that simply reserving | |
733 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() | |
734 | * in reserve_bootmem. | |
735 | */ | |
736 | unsigned long size = PAGE_SIZE; | |
737 | unsigned long end = max_low_pfn * PAGE_SIZE; | |
738 | if (mpf->mpf_physptr + size > end) | |
739 | size = end - mpf->mpf_physptr; | |
72a7fe39 BW |
740 | reserve_bootmem(mpf->mpf_physptr, size, |
741 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
742 | } |
743 | ||
744 | mpf_found = mpf; | |
745 | return 1; | |
746 | } | |
747 | bp += 4; | |
748 | length -= 16; | |
749 | } | |
750 | return 0; | |
751 | } | |
752 | ||
4ef81297 | 753 | void __init find_smp_config(void) |
1da177e4 LT |
754 | { |
755 | unsigned int address; | |
756 | ||
757 | /* | |
758 | * FIXME: Linux assumes you have 640K of base ram.. | |
759 | * this continues the error... | |
760 | * | |
761 | * 1) Scan the bottom 1K for a signature | |
762 | * 2) Scan the top 1K of base RAM | |
763 | * 3) Scan the 64K of bios | |
764 | */ | |
4ef81297 AS |
765 | if (smp_scan_config(0x0, 0x400) || |
766 | smp_scan_config(639 * 0x400, 0x400) || | |
767 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
768 | return; |
769 | /* | |
770 | * If it is an SMP machine we should know now, unless the | |
771 | * configuration is in an EISA/MCA bus machine with an | |
772 | * extended bios data area. | |
773 | * | |
774 | * there is a real-mode segmented pointer pointing to the | |
775 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
776 | * | |
777 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
778 | * area, and as such this kind of SMP config may be less | |
779 | * trustworthy, simply because the SMP table may have been | |
780 | * stomped on during early boot. These loaders are buggy and | |
781 | * should be fixed. | |
782 | * | |
783 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
784 | */ | |
785 | ||
786 | address = get_bios_ebda(); | |
787 | if (address) | |
788 | smp_scan_config(address, 0x400); | |
789 | } | |
790 | ||
791 | /* -------------------------------------------------------------------------- | |
792 | ACPI-based MP Configuration | |
793 | -------------------------------------------------------------------------- */ | |
794 | ||
888ba6c6 | 795 | #ifdef CONFIG_ACPI |
1da177e4 | 796 | |
8466361a | 797 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
798 | |
799 | #define MP_ISA_BUS 0 | |
800 | #define MP_MAX_IOAPIC_PIN 127 | |
801 | ||
9e5c5f1d | 802 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 803 | |
4ef81297 | 804 | static int mp_find_ioapic(int gsi) |
1da177e4 | 805 | { |
19f03ffe | 806 | int i = 0; |
1da177e4 LT |
807 | |
808 | /* Find the IOAPIC that manages this GSI. */ | |
809 | for (i = 0; i < nr_ioapics; i++) { | |
810 | if ((gsi >= mp_ioapic_routing[i].gsi_base) | |
4ef81297 | 811 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
812 | return i; |
813 | } | |
814 | ||
815 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
816 | ||
817 | return -1; | |
818 | } | |
1da177e4 | 819 | |
e3e3ffa2 AS |
820 | static u8 uniq_ioapic_id(u8 id) |
821 | { | |
822 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
823 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
824 | return io_apic_get_unique_id(nr_ioapics, id); | |
825 | else | |
826 | return id; | |
827 | } | |
828 | ||
a65d1d64 | 829 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 830 | { |
19f03ffe | 831 | int idx = 0; |
1da177e4 | 832 | |
857033a6 | 833 | if (bad_ioapic(address)) |
1da177e4 | 834 | return; |
1da177e4 | 835 | |
e3e3ffa2 | 836 | idx = nr_ioapics; |
1da177e4 LT |
837 | |
838 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
839 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
840 | mp_ioapics[idx].mpc_apicaddr = address; | |
841 | ||
842 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
e3e3ffa2 | 843 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
1da177e4 | 844 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
4ef81297 AS |
845 | |
846 | /* | |
1da177e4 LT |
847 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
848 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
849 | */ | |
850 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
851 | mp_ioapic_routing[idx].gsi_base = gsi_base; | |
64883ab0 | 852 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
4ef81297 | 853 | io_apic_get_redir_entries(idx); |
1da177e4 | 854 | |
64883ab0 TG |
855 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
856 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, | |
e3e3ffa2 AS |
857 | mp_ioapics[idx].mpc_apicver, |
858 | mp_ioapics[idx].mpc_apicaddr, | |
4ef81297 | 859 | mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end); |
e3e3ffa2 AS |
860 | |
861 | nr_ioapics++; | |
1da177e4 LT |
862 | } |
863 | ||
4ef81297 | 864 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
865 | { |
866 | struct mpc_config_intsrc intsrc; | |
4ef81297 AS |
867 | int ioapic = -1; |
868 | int pin = -1; | |
1da177e4 | 869 | |
4ef81297 | 870 | /* |
1da177e4 LT |
871 | * Convert 'gsi' to 'ioapic.pin'. |
872 | */ | |
873 | ioapic = mp_find_ioapic(gsi); | |
874 | if (ioapic < 0) | |
875 | return; | |
876 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
877 | ||
878 | /* | |
879 | * TBD: This check is for faulty timer entries, where the override | |
4ef81297 | 880 | * erroneously sets the trigger to level, resulting in a HUGE |
1da177e4 LT |
881 | * increase of timer interrupts! |
882 | */ | |
883 | if ((bus_irq == 0) && (trigger == 3)) | |
884 | trigger = 1; | |
885 | ||
886 | intsrc.mpc_type = MP_INTSRC; | |
887 | intsrc.mpc_irqtype = mp_INT; | |
888 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
889 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
4ef81297 AS |
890 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
891 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
892 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 LT |
893 | |
894 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
4ef81297 AS |
895 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
896 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
897 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
898 | ||
899 | mp_irqs[mp_irq_entries] = intsrc; | |
900 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
901 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
902 | } |
903 | ||
2df29726 AS |
904 | int es7000_plat; |
905 | ||
4ef81297 | 906 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
907 | { |
908 | struct mpc_config_intsrc intsrc; | |
19f03ffe AK |
909 | int i = 0; |
910 | int ioapic = -1; | |
1da177e4 | 911 | |
c0a282c2 | 912 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 913 | /* |
1da177e4 LT |
914 | * Fabricate the legacy ISA bus (bus #31). |
915 | */ | |
916 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; | |
c0a282c2 | 917 | #endif |
a6333c3c | 918 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
919 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
920 | ||
921 | /* | |
922 | * Older generations of ES7000 have no legacy identity mappings | |
923 | */ | |
924 | if (es7000_plat == 1) | |
925 | return; | |
926 | ||
4ef81297 AS |
927 | /* |
928 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
1da177e4 LT |
929 | */ |
930 | ioapic = mp_find_ioapic(0); | |
931 | if (ioapic < 0) | |
932 | return; | |
933 | ||
934 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 935 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 | 936 | intsrc.mpc_srcbus = MP_ISA_BUS; |
61048c63 | 937 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 938 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; |
61048c63 | 939 | #endif |
4ef81297 | 940 | /* |
1da177e4 | 941 | * Use the default configuration for the IRQs 0-15. Unless |
27b46d76 | 942 | * overridden by (MADT) interrupt source override entries. |
1da177e4 LT |
943 | */ |
944 | for (i = 0; i < 16; i++) { | |
945 | int idx; | |
946 | ||
947 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
948 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
949 | ||
950 | /* Do we already have a mapping for this ISA IRQ? */ | |
4ef81297 AS |
951 | if (irq->mpc_srcbus == MP_ISA_BUS |
952 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
953 | break; |
954 | ||
955 | /* Do we already have a mapping for this IOAPIC pin */ | |
956 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
4ef81297 | 957 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
958 | break; |
959 | } | |
960 | ||
961 | if (idx != mp_irq_entries) { | |
962 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
4ef81297 | 963 | continue; /* IRQ already used */ |
1da177e4 LT |
964 | } |
965 | ||
966 | intsrc.mpc_irqtype = mp_INT; | |
4ef81297 | 967 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
968 | intsrc.mpc_dstirq = i; |
969 | ||
970 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
4ef81297 AS |
971 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
972 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
973 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
974 | intsrc.mpc_dstirq); |
975 | ||
976 | mp_irqs[mp_irq_entries] = intsrc; | |
977 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
978 | panic("Max # of irq sources exceeded!\n"); | |
979 | } | |
980 | } | |
981 | ||
c434b7a6 | 982 | #define MAX_GSI_NUM 4096 |
2ba7deef | 983 | #define IRQ_COMPRESSION_START 64 |
c434b7a6 | 984 | |
19f03ffe | 985 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 986 | { |
19f03ffe AK |
987 | int ioapic = -1; |
988 | int ioapic_pin = 0; | |
989 | int idx, bit = 0; | |
2ba7deef | 990 | static int pci_irq = IRQ_COMPRESSION_START; |
c434b7a6 | 991 | /* |
ab4a574e | 992 | * Mapping between Global System Interrupts, which |
c434b7a6 NP |
993 | * represent all possible interrupts, and IRQs |
994 | * assigned to actual devices. | |
995 | */ | |
4ef81297 | 996 | static int gsi_to_irq[MAX_GSI_NUM]; |
1da177e4 | 997 | |
1da177e4 | 998 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 999 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 1000 | return gsi; |
1da177e4 LT |
1001 | |
1002 | ioapic = mp_find_ioapic(gsi); | |
1003 | if (ioapic < 0) { | |
1004 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
1005 | return gsi; | |
1006 | } | |
1007 | ||
1008 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
1009 | ||
1010 | if (ioapic_renumber_irq) | |
1011 | gsi = ioapic_renumber_irq(ioapic, gsi); | |
1012 | ||
4ef81297 AS |
1013 | /* |
1014 | * Avoid pin reprogramming. PRTs typically include entries | |
1da177e4 LT |
1015 | * with redundant pin->gsi mappings (but unique PCI devices); |
1016 | * we only program the IOAPIC on the first. | |
1017 | */ | |
1018 | bit = ioapic_pin % 32; | |
1019 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
1020 | if (idx > 3) { | |
1021 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
4ef81297 AS |
1022 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
1023 | ioapic_pin); | |
1da177e4 LT |
1024 | return gsi; |
1025 | } | |
4ef81297 | 1026 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
1027 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
1028 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
2ba7deef | 1029 | return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); |
1da177e4 LT |
1030 | } |
1031 | ||
4ef81297 | 1032 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 | 1033 | |
2ba7deef LB |
1034 | /* |
1035 | * For GSI >= 64, use IRQ compression | |
1036 | */ | |
1037 | if ((gsi >= IRQ_COMPRESSION_START) | |
4ef81297 | 1038 | && (triggering == ACPI_LEVEL_SENSITIVE)) { |
c434b7a6 NP |
1039 | /* |
1040 | * For PCI devices assign IRQs in order, avoiding gaps | |
1041 | * due to unused I/O APIC pins. | |
1042 | */ | |
1043 | int irq = gsi; | |
1044 | if (gsi < MAX_GSI_NUM) { | |
e0c1e9bf KM |
1045 | /* |
1046 | * Retain the VIA chipset work-around (gsi > 15), but | |
1047 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
1048 | * via an override (so it's not on pin 0 of the ioapic), | |
1049 | * and at the same time, the pin 0 interrupt is a PCI | |
1050 | * type. The gsi > 15 test could cause these two pins | |
1051 | * to be shared as IRQ0, and they are not shareable. | |
1052 | * So test for this condition, and if necessary, avoid | |
1053 | * the pin collision. | |
1054 | */ | |
ede1389f | 1055 | gsi = pci_irq++; |
e1afc3f5 NP |
1056 | /* |
1057 | * Don't assign IRQ used by ACPI SCI | |
1058 | */ | |
cee324b1 | 1059 | if (gsi == acpi_gbl_FADT.sci_interrupt) |
e1afc3f5 | 1060 | gsi = pci_irq++; |
c434b7a6 NP |
1061 | gsi_to_irq[irq] = gsi; |
1062 | } else { | |
1063 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
1064 | return gsi; | |
1065 | } | |
1066 | } | |
1067 | ||
1da177e4 | 1068 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
4ef81297 AS |
1069 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
1070 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
1071 | return gsi; |
1072 | } | |
1073 | ||
8466361a | 1074 | #endif /* CONFIG_X86_IO_APIC */ |
888ba6c6 | 1075 | #endif /* CONFIG_ACPI */ |