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x86: get boot_cpu_id as early for k8_scan_nodes
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h>
1da177e4 20#include <linux/bootmem.h>
1da177e4
LT		 21#include <linux/kernel_stat.h>
22#include <linux/mc146818rtc.h>
23#include <linux/bitops.h>
24
25#include <asm/smp.h>
26#include <asm/acpi.h>
27#include <asm/mtrr.h>
28#include <asm/mpspec.h>
29#include <asm/io_apic.h>
30
31#include <mach_apic.h>
874c4fe3 32#include <mach_apicdef.h>
1da177e4
LT		 33#include <mach_mpparse.h>
34#include <bios_ebda.h>
35
36/* Have we found an MP table */
37int smp_found_config;
4a5d107a 38unsigned int __cpuinitdata maxcpus = NR_CPUS;
1da177e4
LT		 39
40/*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44int apic_version [MAX_APICS];
45int mp_bus_id_to_type [MAX_MP_BUSSES];
46int mp_bus_id_to_node [MAX_MP_BUSSES];
47int mp_bus_id_to_local [MAX_MP_BUSSES];
1da177e4
LT		 48int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49static int mp_current_pci_id;
50
51/* I/O APIC entries */
52struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53
54/* # of MP IRQ source entries */
55struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56
57/* MP IRQ source entries */
58int mp_irq_entries;
59
60int nr_ioapics;
61
62int pic_mode;
63unsigned long mp_lapic_addr;
64
911a62d4
VP		 65unsigned int def_to_bigsmp = 0;
66
1da177e4
LT		 67/* Processor that is doing the boot up */
68unsigned int boot_cpu_physical_apicid = -1U;
1da177e4 69/* Internal processor count */
87d7e980 70unsigned int num_processors;
1da177e4 71
7b1292e2
GC		 72unsigned disabled_cpus __cpuinitdata;
73
1da177e4
LT		 74/* Bitmask of physically existing CPUs */
75physid_mask_t phys_cpu_present_map;
76
77u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
78
79/*
80 * Intel MP BIOS table parsing routines:
81 */
82
83
84/*
85 * Checksum an MP configuration block.
86 */
87
88static int __init mpf_checksum(unsigned char *mp, int len)
89{
90 int sum = 0;
91
92 while (len--)
93 sum += *mp++;
94
95 return sum & 0xFF;
96}
97
98/*
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
101 * doing this ....
102 */
103
104static int mpc_record;
4a5d107a 105static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
1da177e4 106
4a5d107a 107static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 108{
1299232b
AM		 109 int ver, apicid;
110 physid_mask_t phys_cpu;
1da177e4 111
7b1292e2
GC		 112 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
113 disabled_cpus++;
1da177e4 114 return;
7b1292e2 115 }
1da177e4
LT		 116
117 apicid = mpc_apic_id(m, translation_table[mpc_record]);
118
119 if (m->mpc_featureflag&(1<<0))
120 Dprintk(" Floating point unit present.\n");
121 if (m->mpc_featureflag&(1<<7))
122 Dprintk(" Machine Exception supported.\n");
123 if (m->mpc_featureflag&(1<<8))
124 Dprintk(" 64 bit compare & exchange supported.\n");
125 if (m->mpc_featureflag&(1<<9))
126 Dprintk(" Internal APIC present.\n");
127 if (m->mpc_featureflag&(1<<11))
128 Dprintk(" SEP present.\n");
129 if (m->mpc_featureflag&(1<<12))
130 Dprintk(" MTRR present.\n");
131 if (m->mpc_featureflag&(1<<13))
132 Dprintk(" PGE present.\n");
133 if (m->mpc_featureflag&(1<<14))
134 Dprintk(" MCA present.\n");
135 if (m->mpc_featureflag&(1<<15))
136 Dprintk(" CMOV present.\n");
137 if (m->mpc_featureflag&(1<<16))
138 Dprintk(" PAT present.\n");
139 if (m->mpc_featureflag&(1<<17))
140 Dprintk(" PSE present.\n");
141 if (m->mpc_featureflag&(1<<18))
142 Dprintk(" PSN present.\n");
143 if (m->mpc_featureflag&(1<<19))
144 Dprintk(" Cache Line Flush Instruction present.\n");
145 /* 20 Reserved */
146 if (m->mpc_featureflag&(1<<21))
147 Dprintk(" Debug Trace and EMON Store present.\n");
148 if (m->mpc_featureflag&(1<<22))
149 Dprintk(" ACPI Thermal Throttle Registers present.\n");
150 if (m->mpc_featureflag&(1<<23))
151 Dprintk(" MMX present.\n");
152 if (m->mpc_featureflag&(1<<24))
153 Dprintk(" FXSR present.\n");
154 if (m->mpc_featureflag&(1<<25))
155 Dprintk(" XMM present.\n");
156 if (m->mpc_featureflag&(1<<26))
157 Dprintk(" Willamette New Instructions present.\n");
158 if (m->mpc_featureflag&(1<<27))
159 Dprintk(" Self Snoop present.\n");
160 if (m->mpc_featureflag&(1<<28))
161 Dprintk(" HT present.\n");
162 if (m->mpc_featureflag&(1<<29))
163 Dprintk(" Thermal Monitor present.\n");
164 /* 30, 31 Reserved */
165
166
167 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
168 Dprintk(" Bootup CPU\n");
169 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 170 }
171
1da177e4
LT		 172 ver = m->mpc_apicver;
173
1da177e4
LT		 174 /*
175 * Validate version
176 */
177 if (ver == 0x0) {
1299232b
AM		 178 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
179 "fixing up to 0x10. (tell your hw vendor)\n",
180 m->mpc_apicid);
1da177e4
LT		 181 ver = 0x10;
182 }
183 apic_version[m->mpc_apicid] = ver;
6c180d94
EB		 184
185 phys_cpu = apicid_to_cpu_present(apicid);
186 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
187
188 if (num_processors >= NR_CPUS) {
189 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
190 " Processor ignored.\n", NR_CPUS);
191 return;
192 }
193
194 if (num_processors >= maxcpus) {
195 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
196 " Processor ignored.\n", maxcpus);
197 return;
198 }
199
200 cpu_set(num_processors, cpu_possible_map);
201 num_processors++;
202
6cf272ac
AR		 203 /*
204 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
205 * but we need to work other dependencies like SMP_SUSPEND etc
206 * before this can be done without some confusion.
207 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
208 * - Ashok Raj <ashok.raj@intel.com>
209 */
210 if (num_processors > 8) {
e72c8585
AR		 211 switch (boot_cpu_data.x86_vendor) {
212 case X86_VENDOR_INTEL:
213 if (!APIC_XAPIC(ver)) {
214 def_to_bigsmp = 0;
215 break;
216 }
217 /* If P4 and above fall through */
218 case X86_VENDOR_AMD:
219 def_to_bigsmp = 1;
220 }
221 }
1da177e4
LT		 222 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
223}
224
225static void __init MP_bus_info (struct mpc_config_bus *m)
226{
227 char str[7];
228
229 memcpy(str, m->mpc_bustype, 6);
230 str[6] = 0;
231
232 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
233
5e4edbb7 234#if MAX_MP_BUSSES < 256
c0ec31ad
RD		 235 if (m->mpc_busid >= MAX_MP_BUSSES) {
236 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
237 " is too large, max. supported is %d\n",
238 m->mpc_busid, str, MAX_MP_BUSSES - 1);
239 return;
240 }
5e4edbb7 241#endif
c0ec31ad 242
1da177e4
LT		 243 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
245 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
246 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
247 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
248 mpc_oem_pci_bus(m, translation_table[mpc_record]);
249 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
250 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
251 mp_current_pci_id++;
252 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
253 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
1da177e4
LT		 254 } else {
255 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
256 }
257}
258
259static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
260{
261 if (!(m->mpc_flags & MPC_APIC_USABLE))
262 return;
263
64883ab0 264 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
1da177e4
LT		 265 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
266 if (nr_ioapics >= MAX_IO_APICS) {
267 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
268 MAX_IO_APICS, nr_ioapics);
269 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
270 }
271 if (!m->mpc_apicaddr) {
272 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
273 " found in MP table, skipping!\n");
274 return;
275 }
276 mp_ioapics[nr_ioapics] = *m;
277 nr_ioapics++;
278}
279
280static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
281{
282 mp_irqs [mp_irq_entries] = *m;
283 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
284 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
285 m->mpc_irqtype, m->mpc_irqflag & 3,
286 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
287 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
288 if (++mp_irq_entries == MAX_IRQ_SOURCES)
289 panic("Max # of irq sources exceeded!!\n");
290}
291
292static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
293{
294 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
295 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
296 m->mpc_irqtype, m->mpc_irqflag & 3,
297 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
298 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
1da177e4
LT		 299}
300
301#ifdef CONFIG_X86_NUMAQ
302static void __init MP_translation_info (struct mpc_config_translation *m)
303{
304 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
305
306 if (mpc_record >= MAX_MPC_ENTRY)
307 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
308 else
309 translation_table[mpc_record] = m; /* stash this for later */
310 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
311 node_set_online(m->trans_quad);
312}
313
314/*
315 * Read/parse the MPC oem tables
316 */
317
318static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
319 unsigned short oemsize)
320{
321 int count = sizeof (*oemtable); /* the header size */
322 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
323
324 mpc_record = 0;
325 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
326 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
327 {
328 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
329 oemtable->oem_signature[0],
330 oemtable->oem_signature[1],
331 oemtable->oem_signature[2],
332 oemtable->oem_signature[3]);
333 return;
334 }
335 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
336 {
337 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
338 return;
339 }
340 while (count < oemtable->oem_length) {
341 switch (*oemptr) {
342 case MP_TRANSLATION:
343 {
344 struct mpc_config_translation *m=
345 (struct mpc_config_translation *)oemptr;
346 MP_translation_info(m);
347 oemptr += sizeof(*m);
348 count += sizeof(*m);
349 ++mpc_record;
350 break;
351 }
352 default:
353 {
354 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
355 return;
356 }
357 }
358 }
359}
360
361static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
362 char *productid)
363{
364 if (strncmp(oem, "IBM NUMA", 8))
365 printk("Warning! May not be a NUMA-Q system!\n");
366 if (mpc->mpc_oemptr)
367 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
368 mpc->mpc_oemsize);
369}
370#endif /* CONFIG_X86_NUMAQ */
371
372/*
373 * Read/parse the MPC
374 */
375
376static int __init smp_read_mpc(struct mp_config_table *mpc)
377{
378 char str[16];
379 char oem[10];
380 int count=sizeof(*mpc);
381 unsigned char *mpt=((unsigned char *)mpc)+count;
382
383 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
384 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
385 *(u32 *)mpc->mpc_signature);
386 return 0;
387 }
388 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
389 printk(KERN_ERR "SMP mptable: checksum error!\n");
390 return 0;
391 }
392 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
393 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
394 mpc->mpc_spec);
395 return 0;
396 }
397 if (!mpc->mpc_lapic) {
398 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
399 return 0;
400 }
401 memcpy(oem,mpc->mpc_oem,8);
402 oem[8]=0;
403 printk(KERN_INFO "OEM ID: %s ",oem);
404
405 memcpy(str,mpc->mpc_productid,12);
406 str[12]=0;
407 printk("Product ID: %s ",str);
408
409 mps_oem_check(mpc, oem, str);
410
64883ab0 411 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
1da177e4 412
64883ab0 413 /*
1da177e4
LT		 414 * Save the local APIC address (it might be non-default) -- but only
415 * if we're not using ACPI.
416 */
417 if (!acpi_lapic)
418 mp_lapic_addr = mpc->mpc_lapic;
419
420 /*
421 * Now process the configuration blocks.
422 */
423 mpc_record = 0;
424 while (count < mpc->mpc_length) {
425 switch(*mpt) {
426 case MP_PROCESSOR:
427 {
428 struct mpc_config_processor *m=
429 (struct mpc_config_processor *)mpt;
430 /* ACPI may have already provided this data */
431 if (!acpi_lapic)
432 MP_processor_info(m);
433 mpt += sizeof(*m);
434 count += sizeof(*m);
435 break;
436 }
437 case MP_BUS:
438 {
439 struct mpc_config_bus *m=
440 (struct mpc_config_bus *)mpt;
441 MP_bus_info(m);
442 mpt += sizeof(*m);
443 count += sizeof(*m);
444 break;
445 }
446 case MP_IOAPIC:
447 {
448 struct mpc_config_ioapic *m=
449 (struct mpc_config_ioapic *)mpt;
450 MP_ioapic_info(m);
451 mpt+=sizeof(*m);
452 count+=sizeof(*m);
453 break;
454 }
455 case MP_INTSRC:
456 {
457 struct mpc_config_intsrc *m=
458 (struct mpc_config_intsrc *)mpt;
459
460 MP_intsrc_info(m);
461 mpt+=sizeof(*m);
462 count+=sizeof(*m);
463 break;
464 }
465 case MP_LINTSRC:
466 {
467 struct mpc_config_lintsrc *m=
468 (struct mpc_config_lintsrc *)mpt;
469 MP_lintsrc_info(m);
470 mpt+=sizeof(*m);
471 count+=sizeof(*m);
472 break;
473 }
474 default:
475 {
476 count = mpc->mpc_length;
477 break;
478 }
479 }
480 ++mpc_record;
481 }
3c43f039 482 setup_apic_routing();
1da177e4
LT		 483 if (!num_processors)
484 printk(KERN_ERR "SMP mptable: no processors registered!\n");
485 return num_processors;
486}
487
488static int __init ELCR_trigger(unsigned int irq)
489{
490 unsigned int port;
491
492 port = 0x4d0 + (irq >> 3);
493 return (inb(port) >> (irq & 7)) & 1;
494}
495
496static void __init construct_default_ioirq_mptable(int mpc_default_type)
497{
498 struct mpc_config_intsrc intsrc;
499 int i;
500 int ELCR_fallback = 0;
501
502 intsrc.mpc_type = MP_INTSRC;
503 intsrc.mpc_irqflag = 0; /* conforming */
504 intsrc.mpc_srcbus = 0;
505 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
506
507 intsrc.mpc_irqtype = mp_INT;
508
509 /*
510 * If true, we have an ISA/PCI system with no IRQ entries
511 * in the MP table. To prevent the PCI interrupts from being set up
512 * incorrectly, we try to use the ELCR. The sanity check to see if
513 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
514 * never be level sensitive, so we simply see if the ELCR agrees.
515 * If it does, we assume it's valid.
516 */
517 if (mpc_default_type == 5) {
518 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
519
520 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
521 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
522 else {
523 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
524 ELCR_fallback = 1;
525 }
526 }
527
528 for (i = 0; i < 16; i++) {
529 switch (mpc_default_type) {
530 case 2:
531 if (i == 0 || i == 13)
532 continue; /* IRQ0 & IRQ13 not connected */
533 /* fall through */
534 default:
535 if (i == 2)
536 continue; /* IRQ2 is never connected */
537 }
538
539 if (ELCR_fallback) {
540 /*
541 * If the ELCR indicates a level-sensitive interrupt, we
542 * copy that information over to the MP table in the
543 * irqflag field (level sensitive, active high polarity).
544 */
545 if (ELCR_trigger(i))
546 intsrc.mpc_irqflag = 13;
547 else
548 intsrc.mpc_irqflag = 0;
549 }
550
551 intsrc.mpc_srcbusirq = i;
552 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
553 MP_intsrc_info(&intsrc);
554 }
555
556 intsrc.mpc_irqtype = mp_ExtINT;
557 intsrc.mpc_srcbusirq = 0;
558 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
559 MP_intsrc_info(&intsrc);
560}
561
562static inline void __init construct_default_ISA_mptable(int mpc_default_type)
563{
564 struct mpc_config_processor processor;
565 struct mpc_config_bus bus;
566 struct mpc_config_ioapic ioapic;
567 struct mpc_config_lintsrc lintsrc;
568 int linttypes[2] = { mp_ExtINT, mp_NMI };
569 int i;
570
571 /*
572 * local APIC has default address
573 */
574 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
575
576 /*
577 * 2 CPUs, numbered 0 & 1.
578 */
579 processor.mpc_type = MP_PROCESSOR;
580 /* Either an integrated APIC or a discrete 82489DX. */
581 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
582 processor.mpc_cpuflag = CPU_ENABLED;
583 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
584 (boot_cpu_data.x86_model << 4) |
585 boot_cpu_data.x86_mask;
586 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
587 processor.mpc_reserved[0] = 0;
588 processor.mpc_reserved[1] = 0;
589 for (i = 0; i < 2; i++) {
590 processor.mpc_apicid = i;
591 MP_processor_info(&processor);
592 }
593
594 bus.mpc_type = MP_BUS;
595 bus.mpc_busid = 0;
596 switch (mpc_default_type) {
597 default:
598 printk("???\n");
599 printk(KERN_ERR "Unknown standard configuration %d\n",
600 mpc_default_type);
601 /* fall through */
602 case 1:
603 case 5:
604 memcpy(bus.mpc_bustype, "ISA ", 6);
605 break;
606 case 2:
607 case 6:
608 case 3:
609 memcpy(bus.mpc_bustype, "EISA ", 6);
610 break;
611 case 4:
612 case 7:
613 memcpy(bus.mpc_bustype, "MCA ", 6);
614 }
615 MP_bus_info(&bus);
616 if (mpc_default_type > 4) {
617 bus.mpc_busid = 1;
618 memcpy(bus.mpc_bustype, "PCI ", 6);
619 MP_bus_info(&bus);
620 }
621
622 ioapic.mpc_type = MP_IOAPIC;
623 ioapic.mpc_apicid = 2;
624 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
625 ioapic.mpc_flags = MPC_APIC_USABLE;
626 ioapic.mpc_apicaddr = 0xFEC00000;
627 MP_ioapic_info(&ioapic);
628
629 /*
630 * We set up most of the low 16 IO-APIC pins according to MPS rules.
631 */
632 construct_default_ioirq_mptable(mpc_default_type);
633
634 lintsrc.mpc_type = MP_LINTSRC;
635 lintsrc.mpc_irqflag = 0; /* conforming */
636 lintsrc.mpc_srcbusid = 0;
637 lintsrc.mpc_srcbusirq = 0;
638 lintsrc.mpc_destapic = MP_APIC_ALL;
639 for (i = 0; i < 2; i++) {
640 lintsrc.mpc_irqtype = linttypes[i];
641 lintsrc.mpc_destapiclint = i;
642 MP_lintsrc_info(&lintsrc);
643 }
644}
645
646static struct intel_mp_floating *mpf_found;
647
648/*
649 * Scan the memory blocks for an SMP configuration block.
650 */
651void __init get_smp_config (void)
652{
653 struct intel_mp_floating *mpf = mpf_found;
654
655 /*
1da177e4
LT		 656 * ACPI supports both logical (e.g. Hyper-Threading) and physical
657 * processors, where MPS only supports physical.
658 */
659 if (acpi_lapic && acpi_ioapic) {
660 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
661 return;
662 }
663 else if (acpi_lapic)
664 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
665
666 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
667 if (mpf->mpf_feature2 & (1<<7)) {
668 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
669 pic_mode = 1;
670 } else {
671 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
672 pic_mode = 0;
673 }
674
675 /*
676 * Now see if we need to read further.
677 */
678 if (mpf->mpf_feature1 != 0) {
679
680 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
681 construct_default_ISA_mptable(mpf->mpf_feature1);
682
683 } else if (mpf->mpf_physptr) {
684
685 /*
686 * Read the physical hardware table. Anything here will
687 * override the defaults.
688 */
7d4c8e56 689 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
1da177e4
LT		 690 smp_found_config = 0;
691 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
692 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
693 return;
694 }
695 /*
696 * If there are no explicit MP IRQ entries, then we are
697 * broken. We set up most of the low 16 IO-APIC pins to
698 * ISA defaults and hope it will work.
699 */
700 if (!mp_irq_entries) {
701 struct mpc_config_bus bus;
702
703 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
704
705 bus.mpc_type = MP_BUS;
706 bus.mpc_busid = 0;
707 memcpy(bus.mpc_bustype, "ISA ", 6);
708 MP_bus_info(&bus);
709
710 construct_default_ioirq_mptable(0);
711 }
712
713 } else
714 BUG();
715
716 printk(KERN_INFO "Processors: %d\n", num_processors);
717 /*
718 * Only use the first configuration found.
719 */
720}
721
722static int __init smp_scan_config (unsigned long base, unsigned long length)
723{
724 unsigned long *bp = phys_to_virt(base);
725 struct intel_mp_floating *mpf;
726
e91a3b43 727 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
1da177e4
LT		 728 if (sizeof(*mpf) != 16)
729 printk("Error: MPF size\n");
730
731 while (length > 0) {
732 mpf = (struct intel_mp_floating *)bp;
733 if ((*bp == SMP_MAGIC_IDENT) &&
734 (mpf->mpf_length == 1) &&
735 !mpf_checksum((unsigned char *)bp, 16) &&
736 ((mpf->mpf_specification == 1)
737 || (mpf->mpf_specification == 4)) ) {
738
739 smp_found_config = 1;
e91a3b43
IM		 740 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
741 mpf, virt_to_phys(mpf));
72a7fe39
BW		 742 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
743 BOOTMEM_DEFAULT);
1da177e4
LT		 744 if (mpf->mpf_physptr) {
745 /*
746 * We cannot access to MPC table to compute
747 * table size yet, as only few megabytes from
748 * the bottom is mapped now.
749 * PC-9800's MPC table places on the very last
750 * of physical memory; so that simply reserving
751 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
752 * in reserve_bootmem.
753 */
754 unsigned long size = PAGE_SIZE;
755 unsigned long end = max_low_pfn * PAGE_SIZE;
756 if (mpf->mpf_physptr + size > end)
757 size = end - mpf->mpf_physptr;
72a7fe39
BW		 758 reserve_bootmem(mpf->mpf_physptr, size,
759 BOOTMEM_DEFAULT);
1da177e4
LT		 760 }
761
762 mpf_found = mpf;
763 return 1;
764 }
765 bp += 4;
766 length -= 16;
767 }
768 return 0;
769}
770
771void __init find_smp_config (void)
772{
773 unsigned int address;
774
775 /*
776 * FIXME: Linux assumes you have 640K of base ram..
777 * this continues the error...
778 *
779 * 1) Scan the bottom 1K for a signature
780 * 2) Scan the top 1K of base RAM
781 * 3) Scan the 64K of bios
782 */
783 if (smp_scan_config(0x0,0x400) ||
784 smp_scan_config(639*0x400,0x400) ||
785 smp_scan_config(0xF0000,0x10000))
786 return;
787 /*
788 * If it is an SMP machine we should know now, unless the
789 * configuration is in an EISA/MCA bus machine with an
790 * extended bios data area.
791 *
792 * there is a real-mode segmented pointer pointing to the
793 * 4K EBDA area at 0x40E, calculate and scan it here.
794 *
795 * NOTE! There are Linux loaders that will corrupt the EBDA
796 * area, and as such this kind of SMP config may be less
797 * trustworthy, simply because the SMP table may have been
798 * stomped on during early boot. These loaders are buggy and
799 * should be fixed.
800 *
801 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
802 */
803
804 address = get_bios_ebda();
805 if (address)
806 smp_scan_config(address, 0x400);
807}
808
e5428ede
NP		 809int es7000_plat;
810
1da177e4
LT		 811/* --------------------------------------------------------------------------
812 ACPI-based MP Configuration
813 -------------------------------------------------------------------------- */
814
888ba6c6 815#ifdef CONFIG_ACPI
1da177e4 816
19f03ffe 817void __init mp_register_lapic_address(u64 address)
1da177e4
LT		 818{
819 mp_lapic_addr = (unsigned long) address;
820
821 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
822
823 if (boot_cpu_physical_apicid == -1U)
824 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
825
826 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
827}
828
4a5d107a 829void __cpuinit mp_register_lapic (u8 id, u8 enabled)
1da177e4
LT		 830{
831 struct mpc_config_processor processor;
19f03ffe 832 int boot_cpu = 0;
1da177e4
LT		 833
834 if (MAX_APICS - id <= 0) {
835 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
836 id, MAX_APICS);
837 return;
838 }
839
840 if (id == boot_cpu_physical_apicid)
841 boot_cpu = 1;
842
843 processor.mpc_type = MP_PROCESSOR;
844 processor.mpc_apicid = id;
845 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
846 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
847 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
848 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
849 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
850 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
851 processor.mpc_reserved[0] = 0;
852 processor.mpc_reserved[1] = 0;
853
854 MP_processor_info(&processor);
855}
856
8466361a 857#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 858
859#define MP_ISA_BUS 0
860#define MP_MAX_IOAPIC_PIN 127
861
862static struct mp_ioapic_routing {
863 int apic_id;
864 int gsi_base;
865 int gsi_end;
866 u32 pin_programmed[4];
867} mp_ioapic_routing[MAX_IO_APICS];
868
19f03ffe 869static int mp_find_ioapic (int gsi)
1da177e4 870{
19f03ffe 871 int i = 0;
1da177e4
LT		 872
873 /* Find the IOAPIC that manages this GSI. */
874 for (i = 0; i < nr_ioapics; i++) {
875 if ((gsi >= mp_ioapic_routing[i].gsi_base)
876 && (gsi <= mp_ioapic_routing[i].gsi_end))
877 return i;
878 }
879
880 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
881
882 return -1;
883}
1da177e4 884
19f03ffe 885void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
1da177e4 886{
19f03ffe
AK		 887 int idx = 0;
888 int tmpid;
1da177e4
LT		 889
890 if (nr_ioapics >= MAX_IO_APICS) {
891 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
892 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
893 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
894 }
895 if (!address) {
896 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
897 " found in MADT table, skipping!\n");
898 return;
899 }
900
901 idx = nr_ioapics++;
902
903 mp_ioapics[idx].mpc_type = MP_IOAPIC;
904 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
905 mp_ioapics[idx].mpc_apicaddr = address;
906
907 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
7c5c1e42
SL		 908 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
909 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
6070f9ec 910 tmpid = io_apic_get_unique_id(idx, id);
ca05fea6 911 else
6070f9ec
AD		 912 tmpid = id;
913 if (tmpid == -1) {
914 nr_ioapics--;
915 return;
916 }
917 mp_ioapics[idx].mpc_apicid = tmpid;
1da177e4
LT		 918 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
919
920 /*
921 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
922 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
923 */
924 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
925 mp_ioapic_routing[idx].gsi_base = gsi_base;
64883ab0 926 mp_ioapic_routing[idx].gsi_end = gsi_base +
1da177e4
LT		 927 io_apic_get_redir_entries(idx);
928
64883ab0
TG		 929 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
930 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
931 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
932 mp_ioapic_routing[idx].gsi_base,
933 mp_ioapic_routing[idx].gsi_end);
1da177e4
LT		 934}
935
19f03ffe
AK		 936void __init
937mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
1da177e4
LT		 938{
939 struct mpc_config_intsrc intsrc;
940 int ioapic = -1;
941 int pin = -1;
942
943 /*
944 * Convert 'gsi' to 'ioapic.pin'.
945 */
946 ioapic = mp_find_ioapic(gsi);
947 if (ioapic < 0)
948 return;
949 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
950
951 /*
952 * TBD: This check is for faulty timer entries, where the override
953 * erroneously sets the trigger to level, resulting in a HUGE
954 * increase of timer interrupts!
955 */
956 if ((bus_irq == 0) && (trigger == 3))
957 trigger = 1;
958
959 intsrc.mpc_type = MP_INTSRC;
960 intsrc.mpc_irqtype = mp_INT;
961 intsrc.mpc_irqflag = (trigger << 2) | polarity;
962 intsrc.mpc_srcbus = MP_ISA_BUS;
963 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
964 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
965 intsrc.mpc_dstirq = pin; /* INTIN# */
966
967 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
968 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
969 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
970 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
971
972 mp_irqs[mp_irq_entries] = intsrc;
973 if (++mp_irq_entries == MAX_IRQ_SOURCES)
974 panic("Max # of irq sources exceeded!\n");
1da177e4
LT		 975}
976
1da177e4
LT		 977void __init mp_config_acpi_legacy_irqs (void)
978{
979 struct mpc_config_intsrc intsrc;
19f03ffe
AK		 980 int i = 0;
981 int ioapic = -1;
1da177e4
LT		 982
983 /*
984 * Fabricate the legacy ISA bus (bus #31).
985 */
986 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
987 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
988
989 /*
990 * Older generations of ES7000 have no legacy identity mappings
991 */
992 if (es7000_plat == 1)
993 return;
994
995 /*
996 * Locate the IOAPIC that manages the ISA IRQs (0-15).
997 */
998 ioapic = mp_find_ioapic(0);
999 if (ioapic < 0)
1000 return;
1001
1002 intsrc.mpc_type = MP_INTSRC;
1003 intsrc.mpc_irqflag = 0; /* Conforming */
1004 intsrc.mpc_srcbus = MP_ISA_BUS;
1005 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1006
1007 /*
1008 * Use the default configuration for the IRQs 0-15. Unless
27b46d76 1009 * overridden by (MADT) interrupt source override entries.
1da177e4
LT		 1010 */
1011 for (i = 0; i < 16; i++) {
1012 int idx;
1013
1014 for (idx = 0; idx < mp_irq_entries; idx++) {
1015 struct mpc_config_intsrc *irq = mp_irqs + idx;
1016
1017 /* Do we already have a mapping for this ISA IRQ? */
1018 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1019 break;
1020
1021 /* Do we already have a mapping for this IOAPIC pin */
1022 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1023 (irq->mpc_dstirq == i))
1024 break;
1025 }
1026
1027 if (idx != mp_irq_entries) {
1028 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1029 continue; /* IRQ already used */
1030 }
1031
1032 intsrc.mpc_irqtype = mp_INT;
1033 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1034 intsrc.mpc_dstirq = i;
1035
1036 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1037 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1038 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1039 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1040 intsrc.mpc_dstirq);
1041
1042 mp_irqs[mp_irq_entries] = intsrc;
1043 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1044 panic("Max # of irq sources exceeded!\n");
1045 }
1046}
1047
c434b7a6 1048#define MAX_GSI_NUM 4096
2ba7deef 1049#define IRQ_COMPRESSION_START 64
c434b7a6 1050
19f03ffe 1051int mp_register_gsi(u32 gsi, int triggering, int polarity)
1da177e4 1052{
19f03ffe
AK		 1053 int ioapic = -1;
1054 int ioapic_pin = 0;
1055 int idx, bit = 0;
2ba7deef 1056 static int pci_irq = IRQ_COMPRESSION_START;
c434b7a6 1057 /*
ab4a574e 1058 * Mapping between Global System Interrupts, which
c434b7a6
NP		 1059 * represent all possible interrupts, and IRQs
1060 * assigned to actual devices.
1061 */
1062 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4 1063
1da177e4 1064 /* Don't set up the ACPI SCI because it's already set up */
cee324b1 1065 if (acpi_gbl_FADT.sci_interrupt == gsi)
1da177e4 1066 return gsi;
1da177e4
LT		 1067
1068 ioapic = mp_find_ioapic(gsi);
1069 if (ioapic < 0) {
1070 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1071 return gsi;
1072 }
1073
1074 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1075
1076 if (ioapic_renumber_irq)
1077 gsi = ioapic_renumber_irq(ioapic, gsi);
1078
1079 /*
1080 * Avoid pin reprogramming. PRTs typically include entries
1081 * with redundant pin->gsi mappings (but unique PCI devices);
1082 * we only program the IOAPIC on the first.
1083 */
1084 bit = ioapic_pin % 32;
1085 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1086 if (idx > 3) {
1087 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1088 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1089 ioapic_pin);
1090 return gsi;
1091 }
1092 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1093 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1094 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
2ba7deef 1095 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1da177e4
LT		 1096 }
1097
1098 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1099
2ba7deef
LB		 1100 /*
1101 * For GSI >= 64, use IRQ compression
1102 */
1103 if ((gsi >= IRQ_COMPRESSION_START)
1104 && (triggering == ACPI_LEVEL_SENSITIVE)) {
c434b7a6
NP		 1105 /*
1106 * For PCI devices assign IRQs in order, avoiding gaps
1107 * due to unused I/O APIC pins.
1108 */
1109 int irq = gsi;
1110 if (gsi < MAX_GSI_NUM) {
e0c1e9bf
KM		 1111 /*
1112 * Retain the VIA chipset work-around (gsi > 15), but
1113 * avoid a problem where the 8254 timer (IRQ0) is setup
1114 * via an override (so it's not on pin 0 of the ioapic),
1115 * and at the same time, the pin 0 interrupt is a PCI
1116 * type. The gsi > 15 test could cause these two pins
1117 * to be shared as IRQ0, and they are not shareable.
1118 * So test for this condition, and if necessary, avoid
1119 * the pin collision.
1120 */
1121 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
e1afc3f5 1122 gsi = pci_irq++;
e1afc3f5
NP		 1123 /*
1124 * Don't assign IRQ used by ACPI SCI
1125 */
cee324b1 1126 if (gsi == acpi_gbl_FADT.sci_interrupt)
e1afc3f5 1127 gsi = pci_irq++;
c434b7a6
NP		 1128 gsi_to_irq[irq] = gsi;
1129 } else {
1130 printk(KERN_ERR "GSI %u is too high\n", gsi);
1131 return gsi;
1132 }
1133 }
1134
1da177e4 1135 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
cb654695
LB		 1136 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1137 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1da177e4
LT		 1138 return gsi;
1139}
1140
8466361a 1141#endif /* CONFIG_X86_IO_APIC */
888ba6c6 1142#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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