Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/acpi.h> | |
19 | #include <linux/delay.h> | |
1da177e4 | 20 | #include <linux/bootmem.h> |
1da177e4 LT |
21 | #include <linux/kernel_stat.h> |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/bitops.h> | |
24 | ||
25 | #include <asm/smp.h> | |
26 | #include <asm/acpi.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/mpspec.h> | |
29 | #include <asm/io_apic.h> | |
30 | ||
31 | #include <mach_apic.h> | |
874c4fe3 | 32 | #include <mach_apicdef.h> |
1da177e4 LT |
33 | #include <mach_mpparse.h> |
34 | #include <bios_ebda.h> | |
35 | ||
36 | /* Have we found an MP table */ | |
37 | int smp_found_config; | |
4a5d107a | 38 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1da177e4 LT |
39 | |
40 | /* | |
41 | * Various Linux-internal data structures created from the | |
42 | * MP-table. | |
43 | */ | |
44 | int apic_version [MAX_APICS]; | |
c0a282c2 | 45 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
1da177e4 | 46 | int mp_bus_id_to_type [MAX_MP_BUSSES]; |
c0a282c2 | 47 | #endif |
a6333c3c | 48 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 LT |
49 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
50 | static int mp_current_pci_id; | |
51 | ||
52 | /* I/O APIC entries */ | |
53 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
54 | ||
55 | /* # of MP IRQ source entries */ | |
56 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
57 | ||
58 | /* MP IRQ source entries */ | |
59 | int mp_irq_entries; | |
60 | ||
61 | int nr_ioapics; | |
62 | ||
63 | int pic_mode; | |
64 | unsigned long mp_lapic_addr; | |
65 | ||
911a62d4 VP |
66 | unsigned int def_to_bigsmp = 0; |
67 | ||
1da177e4 LT |
68 | /* Processor that is doing the boot up */ |
69 | unsigned int boot_cpu_physical_apicid = -1U; | |
1da177e4 | 70 | /* Internal processor count */ |
87d7e980 | 71 | unsigned int num_processors; |
1da177e4 | 72 | |
7b1292e2 GC |
73 | unsigned disabled_cpus __cpuinitdata; |
74 | ||
1da177e4 LT |
75 | /* Bitmask of physically existing CPUs */ |
76 | physid_mask_t phys_cpu_present_map; | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * Intel MP BIOS table parsing routines: | |
80 | */ | |
81 | ||
82 | ||
83 | /* | |
84 | * Checksum an MP configuration block. | |
85 | */ | |
86 | ||
87 | static int __init mpf_checksum(unsigned char *mp, int len) | |
88 | { | |
89 | int sum = 0; | |
90 | ||
91 | while (len--) | |
92 | sum += *mp++; | |
93 | ||
94 | return sum & 0xFF; | |
95 | } | |
96 | ||
97 | /* | |
98 | * Have to match translation table entries to main table entries by counter | |
99 | * hence the mpc_record variable .... can't see a less disgusting way of | |
100 | * doing this .... | |
101 | */ | |
102 | ||
103 | static int mpc_record; | |
4a5d107a | 104 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata; |
1da177e4 | 105 | |
4a5d107a | 106 | static void __cpuinit MP_processor_info (struct mpc_config_processor *m) |
1da177e4 | 107 | { |
a6c422cc GOC |
108 | int ver, apicid, cpu; |
109 | cpumask_t tmp_map; | |
1299232b | 110 | physid_mask_t phys_cpu; |
1da177e4 | 111 | |
7b1292e2 GC |
112 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
113 | disabled_cpus++; | |
1da177e4 | 114 | return; |
7b1292e2 | 115 | } |
1da177e4 LT |
116 | |
117 | apicid = mpc_apic_id(m, translation_table[mpc_record]); | |
118 | ||
119 | if (m->mpc_featureflag&(1<<0)) | |
120 | Dprintk(" Floating point unit present.\n"); | |
121 | if (m->mpc_featureflag&(1<<7)) | |
122 | Dprintk(" Machine Exception supported.\n"); | |
123 | if (m->mpc_featureflag&(1<<8)) | |
124 | Dprintk(" 64 bit compare & exchange supported.\n"); | |
125 | if (m->mpc_featureflag&(1<<9)) | |
126 | Dprintk(" Internal APIC present.\n"); | |
127 | if (m->mpc_featureflag&(1<<11)) | |
128 | Dprintk(" SEP present.\n"); | |
129 | if (m->mpc_featureflag&(1<<12)) | |
130 | Dprintk(" MTRR present.\n"); | |
131 | if (m->mpc_featureflag&(1<<13)) | |
132 | Dprintk(" PGE present.\n"); | |
133 | if (m->mpc_featureflag&(1<<14)) | |
134 | Dprintk(" MCA present.\n"); | |
135 | if (m->mpc_featureflag&(1<<15)) | |
136 | Dprintk(" CMOV present.\n"); | |
137 | if (m->mpc_featureflag&(1<<16)) | |
138 | Dprintk(" PAT present.\n"); | |
139 | if (m->mpc_featureflag&(1<<17)) | |
140 | Dprintk(" PSE present.\n"); | |
141 | if (m->mpc_featureflag&(1<<18)) | |
142 | Dprintk(" PSN present.\n"); | |
143 | if (m->mpc_featureflag&(1<<19)) | |
144 | Dprintk(" Cache Line Flush Instruction present.\n"); | |
145 | /* 20 Reserved */ | |
146 | if (m->mpc_featureflag&(1<<21)) | |
147 | Dprintk(" Debug Trace and EMON Store present.\n"); | |
148 | if (m->mpc_featureflag&(1<<22)) | |
149 | Dprintk(" ACPI Thermal Throttle Registers present.\n"); | |
150 | if (m->mpc_featureflag&(1<<23)) | |
151 | Dprintk(" MMX present.\n"); | |
152 | if (m->mpc_featureflag&(1<<24)) | |
153 | Dprintk(" FXSR present.\n"); | |
154 | if (m->mpc_featureflag&(1<<25)) | |
155 | Dprintk(" XMM present.\n"); | |
156 | if (m->mpc_featureflag&(1<<26)) | |
157 | Dprintk(" Willamette New Instructions present.\n"); | |
158 | if (m->mpc_featureflag&(1<<27)) | |
159 | Dprintk(" Self Snoop present.\n"); | |
160 | if (m->mpc_featureflag&(1<<28)) | |
161 | Dprintk(" HT present.\n"); | |
162 | if (m->mpc_featureflag&(1<<29)) | |
163 | Dprintk(" Thermal Monitor present.\n"); | |
164 | /* 30, 31 Reserved */ | |
165 | ||
166 | ||
167 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
168 | Dprintk(" Bootup CPU\n"); | |
169 | boot_cpu_physical_apicid = m->mpc_apicid; | |
1da177e4 LT |
170 | } |
171 | ||
1da177e4 LT |
172 | ver = m->mpc_apicver; |
173 | ||
1da177e4 LT |
174 | /* |
175 | * Validate version | |
176 | */ | |
177 | if (ver == 0x0) { | |
1299232b AM |
178 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " |
179 | "fixing up to 0x10. (tell your hw vendor)\n", | |
180 | m->mpc_apicid); | |
1da177e4 LT |
181 | ver = 0x10; |
182 | } | |
183 | apic_version[m->mpc_apicid] = ver; | |
6c180d94 EB |
184 | |
185 | phys_cpu = apicid_to_cpu_present(apicid); | |
186 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
187 | ||
188 | if (num_processors >= NR_CPUS) { | |
189 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
190 | " Processor ignored.\n", NR_CPUS); | |
191 | return; | |
192 | } | |
193 | ||
194 | if (num_processors >= maxcpus) { | |
195 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
196 | " Processor ignored.\n", maxcpus); | |
197 | return; | |
198 | } | |
199 | ||
200 | cpu_set(num_processors, cpu_possible_map); | |
201 | num_processors++; | |
a6c422cc GOC |
202 | cpus_complement(tmp_map, cpu_present_map); |
203 | cpu = first_cpu(tmp_map); | |
204 | ||
205 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) | |
206 | /* | |
207 | * x86_bios_cpu_apicid is required to have processors listed | |
208 | * in same order as logical cpu numbers. Hence the first | |
209 | * entry is BSP, and so on. | |
210 | */ | |
211 | cpu = 0; | |
6c180d94 | 212 | |
6cf272ac AR |
213 | /* |
214 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
215 | * but we need to work other dependencies like SMP_SUSPEND etc | |
216 | * before this can be done without some confusion. | |
217 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
218 | * - Ashok Raj <ashok.raj@intel.com> | |
219 | */ | |
220 | if (num_processors > 8) { | |
e72c8585 AR |
221 | switch (boot_cpu_data.x86_vendor) { |
222 | case X86_VENDOR_INTEL: | |
223 | if (!APIC_XAPIC(ver)) { | |
224 | def_to_bigsmp = 0; | |
225 | break; | |
226 | } | |
227 | /* If P4 and above fall through */ | |
228 | case X86_VENDOR_AMD: | |
229 | def_to_bigsmp = 1; | |
230 | } | |
231 | } | |
73bf102b GOC |
232 | /* are we being called early in kernel startup? */ |
233 | if (x86_cpu_to_apicid_early_ptr) { | |
a6c422cc | 234 | u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr; |
73bf102b | 235 | u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; |
a6c422cc GOC |
236 | |
237 | cpu_to_apicid[cpu] = m->mpc_apicid; | |
73bf102b GOC |
238 | bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; |
239 | } else { | |
a6c422cc | 240 | per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid; |
73bf102b GOC |
241 | per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid; |
242 | } | |
a6c422cc | 243 | cpu_set(cpu, cpu_present_map); |
1da177e4 LT |
244 | } |
245 | ||
246 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
247 | { | |
248 | char str[7]; | |
249 | ||
250 | memcpy(str, m->mpc_bustype, 6); | |
251 | str[6] = 0; | |
252 | ||
253 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); | |
254 | ||
5e4edbb7 | 255 | #if MAX_MP_BUSSES < 256 |
c0ec31ad RD |
256 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
257 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " | |
258 | " is too large, max. supported is %d\n", | |
259 | m->mpc_busid, str, MAX_MP_BUSSES - 1); | |
260 | return; | |
261 | } | |
5e4edbb7 | 262 | #endif |
c0ec31ad | 263 | |
a6333c3c | 264 | set_bit(m->mpc_busid, mp_bus_not_pci); |
9e0a2de2 | 265 | if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) { |
1da177e4 | 266 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
a6333c3c | 267 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
268 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
269 | mp_current_pci_id++; | |
c0a282c2 AS |
270 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) |
271 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; | |
9e0a2de2 AS |
272 | } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) { |
273 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; | |
274 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) { | |
275 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; | |
1da177e4 LT |
276 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) { |
277 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; | |
1da177e4 LT |
278 | } else { |
279 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
c0a282c2 | 280 | #endif |
1da177e4 LT |
281 | } |
282 | } | |
283 | ||
284 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) | |
285 | { | |
286 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
287 | return; | |
288 | ||
64883ab0 | 289 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
1da177e4 LT |
290 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
291 | if (nr_ioapics >= MAX_IO_APICS) { | |
292 | printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n", | |
293 | MAX_IO_APICS, nr_ioapics); | |
294 | panic("Recompile kernel with bigger MAX_IO_APICS!.\n"); | |
295 | } | |
296 | if (!m->mpc_apicaddr) { | |
297 | printk(KERN_ERR "WARNING: bogus zero I/O APIC address" | |
298 | " found in MP table, skipping!\n"); | |
299 | return; | |
300 | } | |
301 | mp_ioapics[nr_ioapics] = *m; | |
302 | nr_ioapics++; | |
303 | } | |
304 | ||
305 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
306 | { | |
307 | mp_irqs [mp_irq_entries] = *m; | |
308 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
309 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
310 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
311 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
312 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
313 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
314 | panic("Max # of irq sources exceeded!!\n"); | |
315 | } | |
316 | ||
317 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
318 | { | |
319 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
320 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
321 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
322 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
323 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
324 | } |
325 | ||
326 | #ifdef CONFIG_X86_NUMAQ | |
327 | static void __init MP_translation_info (struct mpc_config_translation *m) | |
328 | { | |
329 | printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local); | |
330 | ||
331 | if (mpc_record >= MAX_MPC_ENTRY) | |
332 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); | |
333 | else | |
334 | translation_table[mpc_record] = m; /* stash this for later */ | |
335 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) | |
336 | node_set_online(m->trans_quad); | |
337 | } | |
338 | ||
339 | /* | |
340 | * Read/parse the MPC oem tables | |
341 | */ | |
342 | ||
343 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \ | |
344 | unsigned short oemsize) | |
345 | { | |
346 | int count = sizeof (*oemtable); /* the header size */ | |
347 | unsigned char *oemptr = ((unsigned char *)oemtable)+count; | |
348 | ||
349 | mpc_record = 0; | |
350 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable); | |
351 | if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4)) | |
352 | { | |
353 | printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
354 | oemtable->oem_signature[0], | |
355 | oemtable->oem_signature[1], | |
356 | oemtable->oem_signature[2], | |
357 | oemtable->oem_signature[3]); | |
358 | return; | |
359 | } | |
360 | if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length)) | |
361 | { | |
362 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); | |
363 | return; | |
364 | } | |
365 | while (count < oemtable->oem_length) { | |
366 | switch (*oemptr) { | |
367 | case MP_TRANSLATION: | |
368 | { | |
369 | struct mpc_config_translation *m= | |
370 | (struct mpc_config_translation *)oemptr; | |
371 | MP_translation_info(m); | |
372 | oemptr += sizeof(*m); | |
373 | count += sizeof(*m); | |
374 | ++mpc_record; | |
375 | break; | |
376 | } | |
377 | default: | |
378 | { | |
379 | printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr); | |
380 | return; | |
381 | } | |
382 | } | |
383 | } | |
384 | } | |
385 | ||
386 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, | |
387 | char *productid) | |
388 | { | |
389 | if (strncmp(oem, "IBM NUMA", 8)) | |
390 | printk("Warning! May not be a NUMA-Q system!\n"); | |
391 | if (mpc->mpc_oemptr) | |
392 | smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr, | |
393 | mpc->mpc_oemsize); | |
394 | } | |
395 | #endif /* CONFIG_X86_NUMAQ */ | |
396 | ||
397 | /* | |
398 | * Read/parse the MPC | |
399 | */ | |
400 | ||
401 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
402 | { | |
403 | char str[16]; | |
404 | char oem[10]; | |
405 | int count=sizeof(*mpc); | |
406 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
407 | ||
408 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
409 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", | |
410 | *(u32 *)mpc->mpc_signature); | |
411 | return 0; | |
412 | } | |
413 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
414 | printk(KERN_ERR "SMP mptable: checksum error!\n"); | |
415 | return 0; | |
416 | } | |
417 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
418 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", | |
419 | mpc->mpc_spec); | |
420 | return 0; | |
421 | } | |
422 | if (!mpc->mpc_lapic) { | |
423 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); | |
424 | return 0; | |
425 | } | |
426 | memcpy(oem,mpc->mpc_oem,8); | |
427 | oem[8]=0; | |
428 | printk(KERN_INFO "OEM ID: %s ",oem); | |
429 | ||
430 | memcpy(str,mpc->mpc_productid,12); | |
431 | str[12]=0; | |
432 | printk("Product ID: %s ",str); | |
433 | ||
434 | mps_oem_check(mpc, oem, str); | |
435 | ||
64883ab0 | 436 | printk("APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 | 437 | |
64883ab0 | 438 | /* |
1da177e4 LT |
439 | * Save the local APIC address (it might be non-default) -- but only |
440 | * if we're not using ACPI. | |
441 | */ | |
442 | if (!acpi_lapic) | |
443 | mp_lapic_addr = mpc->mpc_lapic; | |
444 | ||
445 | /* | |
446 | * Now process the configuration blocks. | |
447 | */ | |
448 | mpc_record = 0; | |
449 | while (count < mpc->mpc_length) { | |
450 | switch(*mpt) { | |
451 | case MP_PROCESSOR: | |
452 | { | |
453 | struct mpc_config_processor *m= | |
454 | (struct mpc_config_processor *)mpt; | |
455 | /* ACPI may have already provided this data */ | |
456 | if (!acpi_lapic) | |
457 | MP_processor_info(m); | |
458 | mpt += sizeof(*m); | |
459 | count += sizeof(*m); | |
460 | break; | |
461 | } | |
462 | case MP_BUS: | |
463 | { | |
464 | struct mpc_config_bus *m= | |
465 | (struct mpc_config_bus *)mpt; | |
466 | MP_bus_info(m); | |
467 | mpt += sizeof(*m); | |
468 | count += sizeof(*m); | |
469 | break; | |
470 | } | |
471 | case MP_IOAPIC: | |
472 | { | |
473 | struct mpc_config_ioapic *m= | |
474 | (struct mpc_config_ioapic *)mpt; | |
475 | MP_ioapic_info(m); | |
476 | mpt+=sizeof(*m); | |
477 | count+=sizeof(*m); | |
478 | break; | |
479 | } | |
480 | case MP_INTSRC: | |
481 | { | |
482 | struct mpc_config_intsrc *m= | |
483 | (struct mpc_config_intsrc *)mpt; | |
484 | ||
485 | MP_intsrc_info(m); | |
486 | mpt+=sizeof(*m); | |
487 | count+=sizeof(*m); | |
488 | break; | |
489 | } | |
490 | case MP_LINTSRC: | |
491 | { | |
492 | struct mpc_config_lintsrc *m= | |
493 | (struct mpc_config_lintsrc *)mpt; | |
494 | MP_lintsrc_info(m); | |
495 | mpt+=sizeof(*m); | |
496 | count+=sizeof(*m); | |
497 | break; | |
498 | } | |
499 | default: | |
500 | { | |
501 | count = mpc->mpc_length; | |
502 | break; | |
503 | } | |
504 | } | |
505 | ++mpc_record; | |
506 | } | |
3c43f039 | 507 | setup_apic_routing(); |
1da177e4 LT |
508 | if (!num_processors) |
509 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); | |
510 | return num_processors; | |
511 | } | |
512 | ||
513 | static int __init ELCR_trigger(unsigned int irq) | |
514 | { | |
515 | unsigned int port; | |
516 | ||
517 | port = 0x4d0 + (irq >> 3); | |
518 | return (inb(port) >> (irq & 7)) & 1; | |
519 | } | |
520 | ||
521 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
522 | { | |
523 | struct mpc_config_intsrc intsrc; | |
524 | int i; | |
525 | int ELCR_fallback = 0; | |
526 | ||
527 | intsrc.mpc_type = MP_INTSRC; | |
528 | intsrc.mpc_irqflag = 0; /* conforming */ | |
529 | intsrc.mpc_srcbus = 0; | |
530 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
531 | ||
532 | intsrc.mpc_irqtype = mp_INT; | |
533 | ||
534 | /* | |
535 | * If true, we have an ISA/PCI system with no IRQ entries | |
536 | * in the MP table. To prevent the PCI interrupts from being set up | |
537 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
538 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
539 | * never be level sensitive, so we simply see if the ELCR agrees. | |
540 | * If it does, we assume it's valid. | |
541 | */ | |
542 | if (mpc_default_type == 5) { | |
543 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
544 | ||
545 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
546 | printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n"); | |
547 | else { | |
548 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
549 | ELCR_fallback = 1; | |
550 | } | |
551 | } | |
552 | ||
553 | for (i = 0; i < 16; i++) { | |
554 | switch (mpc_default_type) { | |
555 | case 2: | |
556 | if (i == 0 || i == 13) | |
557 | continue; /* IRQ0 & IRQ13 not connected */ | |
558 | /* fall through */ | |
559 | default: | |
560 | if (i == 2) | |
561 | continue; /* IRQ2 is never connected */ | |
562 | } | |
563 | ||
564 | if (ELCR_fallback) { | |
565 | /* | |
566 | * If the ELCR indicates a level-sensitive interrupt, we | |
567 | * copy that information over to the MP table in the | |
568 | * irqflag field (level sensitive, active high polarity). | |
569 | */ | |
570 | if (ELCR_trigger(i)) | |
571 | intsrc.mpc_irqflag = 13; | |
572 | else | |
573 | intsrc.mpc_irqflag = 0; | |
574 | } | |
575 | ||
576 | intsrc.mpc_srcbusirq = i; | |
577 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
578 | MP_intsrc_info(&intsrc); | |
579 | } | |
580 | ||
581 | intsrc.mpc_irqtype = mp_ExtINT; | |
582 | intsrc.mpc_srcbusirq = 0; | |
583 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
584 | MP_intsrc_info(&intsrc); | |
585 | } | |
586 | ||
587 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
588 | { | |
589 | struct mpc_config_processor processor; | |
590 | struct mpc_config_bus bus; | |
591 | struct mpc_config_ioapic ioapic; | |
592 | struct mpc_config_lintsrc lintsrc; | |
593 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
594 | int i; | |
595 | ||
596 | /* | |
597 | * local APIC has default address | |
598 | */ | |
599 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
600 | ||
601 | /* | |
602 | * 2 CPUs, numbered 0 & 1. | |
603 | */ | |
604 | processor.mpc_type = MP_PROCESSOR; | |
605 | /* Either an integrated APIC or a discrete 82489DX. */ | |
606 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
607 | processor.mpc_cpuflag = CPU_ENABLED; | |
608 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
609 | (boot_cpu_data.x86_model << 4) | | |
610 | boot_cpu_data.x86_mask; | |
611 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; | |
612 | processor.mpc_reserved[0] = 0; | |
613 | processor.mpc_reserved[1] = 0; | |
614 | for (i = 0; i < 2; i++) { | |
615 | processor.mpc_apicid = i; | |
616 | MP_processor_info(&processor); | |
617 | } | |
618 | ||
619 | bus.mpc_type = MP_BUS; | |
620 | bus.mpc_busid = 0; | |
621 | switch (mpc_default_type) { | |
622 | default: | |
623 | printk("???\n"); | |
624 | printk(KERN_ERR "Unknown standard configuration %d\n", | |
625 | mpc_default_type); | |
626 | /* fall through */ | |
627 | case 1: | |
628 | case 5: | |
629 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
630 | break; | |
631 | case 2: | |
632 | case 6: | |
633 | case 3: | |
634 | memcpy(bus.mpc_bustype, "EISA ", 6); | |
635 | break; | |
636 | case 4: | |
637 | case 7: | |
638 | memcpy(bus.mpc_bustype, "MCA ", 6); | |
639 | } | |
640 | MP_bus_info(&bus); | |
641 | if (mpc_default_type > 4) { | |
642 | bus.mpc_busid = 1; | |
643 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
644 | MP_bus_info(&bus); | |
645 | } | |
646 | ||
647 | ioapic.mpc_type = MP_IOAPIC; | |
648 | ioapic.mpc_apicid = 2; | |
649 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
650 | ioapic.mpc_flags = MPC_APIC_USABLE; | |
651 | ioapic.mpc_apicaddr = 0xFEC00000; | |
652 | MP_ioapic_info(&ioapic); | |
653 | ||
654 | /* | |
655 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
656 | */ | |
657 | construct_default_ioirq_mptable(mpc_default_type); | |
658 | ||
659 | lintsrc.mpc_type = MP_LINTSRC; | |
660 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
661 | lintsrc.mpc_srcbusid = 0; | |
662 | lintsrc.mpc_srcbusirq = 0; | |
663 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
664 | for (i = 0; i < 2; i++) { | |
665 | lintsrc.mpc_irqtype = linttypes[i]; | |
666 | lintsrc.mpc_destapiclint = i; | |
667 | MP_lintsrc_info(&lintsrc); | |
668 | } | |
669 | } | |
670 | ||
671 | static struct intel_mp_floating *mpf_found; | |
672 | ||
673 | /* | |
674 | * Scan the memory blocks for an SMP configuration block. | |
675 | */ | |
676 | void __init get_smp_config (void) | |
677 | { | |
678 | struct intel_mp_floating *mpf = mpf_found; | |
679 | ||
680 | /* | |
1da177e4 LT |
681 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
682 | * processors, where MPS only supports physical. | |
683 | */ | |
684 | if (acpi_lapic && acpi_ioapic) { | |
685 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
686 | return; | |
687 | } | |
688 | else if (acpi_lapic) | |
689 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
690 | ||
691 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
692 | if (mpf->mpf_feature2 & (1<<7)) { | |
693 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); | |
694 | pic_mode = 1; | |
695 | } else { | |
696 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
697 | pic_mode = 0; | |
698 | } | |
699 | ||
700 | /* | |
701 | * Now see if we need to read further. | |
702 | */ | |
703 | if (mpf->mpf_feature1 != 0) { | |
704 | ||
705 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
706 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
707 | ||
708 | } else if (mpf->mpf_physptr) { | |
709 | ||
710 | /* | |
711 | * Read the physical hardware table. Anything here will | |
712 | * override the defaults. | |
713 | */ | |
7d4c8e56 | 714 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
715 | smp_found_config = 0; |
716 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
717 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
718 | return; | |
719 | } | |
720 | /* | |
721 | * If there are no explicit MP IRQ entries, then we are | |
722 | * broken. We set up most of the low 16 IO-APIC pins to | |
723 | * ISA defaults and hope it will work. | |
724 | */ | |
725 | if (!mp_irq_entries) { | |
726 | struct mpc_config_bus bus; | |
727 | ||
728 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
729 | ||
730 | bus.mpc_type = MP_BUS; | |
731 | bus.mpc_busid = 0; | |
732 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
733 | MP_bus_info(&bus); | |
734 | ||
735 | construct_default_ioirq_mptable(0); | |
736 | } | |
737 | ||
738 | } else | |
739 | BUG(); | |
740 | ||
741 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
742 | /* | |
743 | * Only use the first configuration found. | |
744 | */ | |
745 | } | |
746 | ||
747 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
748 | { | |
749 | unsigned long *bp = phys_to_virt(base); | |
750 | struct intel_mp_floating *mpf; | |
751 | ||
e91a3b43 | 752 | printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length); |
1da177e4 LT |
753 | if (sizeof(*mpf) != 16) |
754 | printk("Error: MPF size\n"); | |
755 | ||
756 | while (length > 0) { | |
757 | mpf = (struct intel_mp_floating *)bp; | |
758 | if ((*bp == SMP_MAGIC_IDENT) && | |
759 | (mpf->mpf_length == 1) && | |
760 | !mpf_checksum((unsigned char *)bp, 16) && | |
761 | ((mpf->mpf_specification == 1) | |
762 | || (mpf->mpf_specification == 4)) ) { | |
763 | ||
764 | smp_found_config = 1; | |
e91a3b43 IM |
765 | printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", |
766 | mpf, virt_to_phys(mpf)); | |
72a7fe39 BW |
767 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, |
768 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
769 | if (mpf->mpf_physptr) { |
770 | /* | |
771 | * We cannot access to MPC table to compute | |
772 | * table size yet, as only few megabytes from | |
773 | * the bottom is mapped now. | |
774 | * PC-9800's MPC table places on the very last | |
775 | * of physical memory; so that simply reserving | |
776 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() | |
777 | * in reserve_bootmem. | |
778 | */ | |
779 | unsigned long size = PAGE_SIZE; | |
780 | unsigned long end = max_low_pfn * PAGE_SIZE; | |
781 | if (mpf->mpf_physptr + size > end) | |
782 | size = end - mpf->mpf_physptr; | |
72a7fe39 BW |
783 | reserve_bootmem(mpf->mpf_physptr, size, |
784 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
785 | } |
786 | ||
787 | mpf_found = mpf; | |
788 | return 1; | |
789 | } | |
790 | bp += 4; | |
791 | length -= 16; | |
792 | } | |
793 | return 0; | |
794 | } | |
795 | ||
796 | void __init find_smp_config (void) | |
797 | { | |
798 | unsigned int address; | |
799 | ||
800 | /* | |
801 | * FIXME: Linux assumes you have 640K of base ram.. | |
802 | * this continues the error... | |
803 | * | |
804 | * 1) Scan the bottom 1K for a signature | |
805 | * 2) Scan the top 1K of base RAM | |
806 | * 3) Scan the 64K of bios | |
807 | */ | |
808 | if (smp_scan_config(0x0,0x400) || | |
809 | smp_scan_config(639*0x400,0x400) || | |
810 | smp_scan_config(0xF0000,0x10000)) | |
811 | return; | |
812 | /* | |
813 | * If it is an SMP machine we should know now, unless the | |
814 | * configuration is in an EISA/MCA bus machine with an | |
815 | * extended bios data area. | |
816 | * | |
817 | * there is a real-mode segmented pointer pointing to the | |
818 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
819 | * | |
820 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
821 | * area, and as such this kind of SMP config may be less | |
822 | * trustworthy, simply because the SMP table may have been | |
823 | * stomped on during early boot. These loaders are buggy and | |
824 | * should be fixed. | |
825 | * | |
826 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
827 | */ | |
828 | ||
829 | address = get_bios_ebda(); | |
830 | if (address) | |
831 | smp_scan_config(address, 0x400); | |
832 | } | |
833 | ||
e5428ede NP |
834 | int es7000_plat; |
835 | ||
1da177e4 LT |
836 | /* -------------------------------------------------------------------------- |
837 | ACPI-based MP Configuration | |
838 | -------------------------------------------------------------------------- */ | |
839 | ||
888ba6c6 | 840 | #ifdef CONFIG_ACPI |
1da177e4 | 841 | |
19f03ffe | 842 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
843 | { |
844 | mp_lapic_addr = (unsigned long) address; | |
845 | ||
846 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); | |
847 | ||
848 | if (boot_cpu_physical_apicid == -1U) | |
849 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
850 | ||
851 | Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid); | |
852 | } | |
853 | ||
4a5d107a | 854 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
855 | { |
856 | struct mpc_config_processor processor; | |
19f03ffe | 857 | int boot_cpu = 0; |
1da177e4 LT |
858 | |
859 | if (MAX_APICS - id <= 0) { | |
860 | printk(KERN_WARNING "Processor #%d invalid (max %d)\n", | |
861 | id, MAX_APICS); | |
862 | return; | |
863 | } | |
864 | ||
865 | if (id == boot_cpu_physical_apicid) | |
866 | boot_cpu = 1; | |
867 | ||
868 | processor.mpc_type = MP_PROCESSOR; | |
869 | processor.mpc_apicid = id; | |
870 | processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
871 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); | |
872 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
873 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
874 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; | |
875 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; | |
876 | processor.mpc_reserved[0] = 0; | |
877 | processor.mpc_reserved[1] = 0; | |
878 | ||
879 | MP_processor_info(&processor); | |
880 | } | |
881 | ||
8466361a | 882 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
883 | |
884 | #define MP_ISA_BUS 0 | |
885 | #define MP_MAX_IOAPIC_PIN 127 | |
886 | ||
887 | static struct mp_ioapic_routing { | |
888 | int apic_id; | |
889 | int gsi_base; | |
890 | int gsi_end; | |
891 | u32 pin_programmed[4]; | |
892 | } mp_ioapic_routing[MAX_IO_APICS]; | |
893 | ||
19f03ffe | 894 | static int mp_find_ioapic (int gsi) |
1da177e4 | 895 | { |
19f03ffe | 896 | int i = 0; |
1da177e4 LT |
897 | |
898 | /* Find the IOAPIC that manages this GSI. */ | |
899 | for (i = 0; i < nr_ioapics; i++) { | |
900 | if ((gsi >= mp_ioapic_routing[i].gsi_base) | |
901 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
902 | return i; | |
903 | } | |
904 | ||
905 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
906 | ||
907 | return -1; | |
908 | } | |
1da177e4 | 909 | |
19f03ffe | 910 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 911 | { |
19f03ffe AK |
912 | int idx = 0; |
913 | int tmpid; | |
1da177e4 LT |
914 | |
915 | if (nr_ioapics >= MAX_IO_APICS) { | |
916 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
917 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
918 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
919 | } | |
920 | if (!address) { | |
921 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
922 | " found in MADT table, skipping!\n"); | |
923 | return; | |
924 | } | |
925 | ||
926 | idx = nr_ioapics++; | |
927 | ||
928 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
929 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
930 | mp_ioapics[idx].mpc_apicaddr = address; | |
931 | ||
932 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
7c5c1e42 SL |
933 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
934 | && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
6070f9ec | 935 | tmpid = io_apic_get_unique_id(idx, id); |
ca05fea6 | 936 | else |
6070f9ec AD |
937 | tmpid = id; |
938 | if (tmpid == -1) { | |
939 | nr_ioapics--; | |
940 | return; | |
941 | } | |
942 | mp_ioapics[idx].mpc_apicid = tmpid; | |
1da177e4 LT |
943 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
944 | ||
945 | /* | |
946 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
947 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
948 | */ | |
949 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
950 | mp_ioapic_routing[idx].gsi_base = gsi_base; | |
64883ab0 | 951 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
1da177e4 LT |
952 | io_apic_get_redir_entries(idx); |
953 | ||
64883ab0 TG |
954 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
955 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, | |
956 | mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, | |
957 | mp_ioapic_routing[idx].gsi_base, | |
958 | mp_ioapic_routing[idx].gsi_end); | |
1da177e4 LT |
959 | } |
960 | ||
19f03ffe AK |
961 | void __init |
962 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
963 | { |
964 | struct mpc_config_intsrc intsrc; | |
965 | int ioapic = -1; | |
966 | int pin = -1; | |
967 | ||
968 | /* | |
969 | * Convert 'gsi' to 'ioapic.pin'. | |
970 | */ | |
971 | ioapic = mp_find_ioapic(gsi); | |
972 | if (ioapic < 0) | |
973 | return; | |
974 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
975 | ||
976 | /* | |
977 | * TBD: This check is for faulty timer entries, where the override | |
978 | * erroneously sets the trigger to level, resulting in a HUGE | |
979 | * increase of timer interrupts! | |
980 | */ | |
981 | if ((bus_irq == 0) && (trigger == 3)) | |
982 | trigger = 1; | |
983 | ||
984 | intsrc.mpc_type = MP_INTSRC; | |
985 | intsrc.mpc_irqtype = mp_INT; | |
986 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
987 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
988 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
989 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
990 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
991 | ||
992 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
993 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
994 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
995 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
996 | ||
997 | mp_irqs[mp_irq_entries] = intsrc; | |
998 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
999 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
1000 | } |
1001 | ||
1da177e4 LT |
1002 | void __init mp_config_acpi_legacy_irqs (void) |
1003 | { | |
1004 | struct mpc_config_intsrc intsrc; | |
19f03ffe AK |
1005 | int i = 0; |
1006 | int ioapic = -1; | |
1da177e4 | 1007 | |
c0a282c2 | 1008 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
1da177e4 LT |
1009 | /* |
1010 | * Fabricate the legacy ISA bus (bus #31). | |
1011 | */ | |
1012 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; | |
c0a282c2 | 1013 | #endif |
a6333c3c | 1014 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
1015 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
1016 | ||
1017 | /* | |
1018 | * Older generations of ES7000 have no legacy identity mappings | |
1019 | */ | |
1020 | if (es7000_plat == 1) | |
1021 | return; | |
1022 | ||
1023 | /* | |
1024 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
1025 | */ | |
1026 | ioapic = mp_find_ioapic(0); | |
1027 | if (ioapic < 0) | |
1028 | return; | |
1029 | ||
1030 | intsrc.mpc_type = MP_INTSRC; | |
1031 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
1032 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
1033 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
1034 | ||
1035 | /* | |
1036 | * Use the default configuration for the IRQs 0-15. Unless | |
27b46d76 | 1037 | * overridden by (MADT) interrupt source override entries. |
1da177e4 LT |
1038 | */ |
1039 | for (i = 0; i < 16; i++) { | |
1040 | int idx; | |
1041 | ||
1042 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
1043 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
1044 | ||
1045 | /* Do we already have a mapping for this ISA IRQ? */ | |
1046 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
1047 | break; | |
1048 | ||
1049 | /* Do we already have a mapping for this IOAPIC pin */ | |
1050 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
1051 | (irq->mpc_dstirq == i)) | |
1052 | break; | |
1053 | } | |
1054 | ||
1055 | if (idx != mp_irq_entries) { | |
1056 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
1057 | continue; /* IRQ already used */ | |
1058 | } | |
1059 | ||
1060 | intsrc.mpc_irqtype = mp_INT; | |
1061 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
1062 | intsrc.mpc_dstirq = i; | |
1063 | ||
1064 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
1065 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
1066 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1067 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1068 | intsrc.mpc_dstirq); | |
1069 | ||
1070 | mp_irqs[mp_irq_entries] = intsrc; | |
1071 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
1072 | panic("Max # of irq sources exceeded!\n"); | |
1073 | } | |
1074 | } | |
1075 | ||
c434b7a6 | 1076 | #define MAX_GSI_NUM 4096 |
2ba7deef | 1077 | #define IRQ_COMPRESSION_START 64 |
c434b7a6 | 1078 | |
19f03ffe | 1079 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 1080 | { |
19f03ffe AK |
1081 | int ioapic = -1; |
1082 | int ioapic_pin = 0; | |
1083 | int idx, bit = 0; | |
2ba7deef | 1084 | static int pci_irq = IRQ_COMPRESSION_START; |
c434b7a6 | 1085 | /* |
ab4a574e | 1086 | * Mapping between Global System Interrupts, which |
c434b7a6 NP |
1087 | * represent all possible interrupts, and IRQs |
1088 | * assigned to actual devices. | |
1089 | */ | |
1090 | static int gsi_to_irq[MAX_GSI_NUM]; | |
1da177e4 | 1091 | |
1da177e4 | 1092 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 1093 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 1094 | return gsi; |
1da177e4 LT |
1095 | |
1096 | ioapic = mp_find_ioapic(gsi); | |
1097 | if (ioapic < 0) { | |
1098 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
1099 | return gsi; | |
1100 | } | |
1101 | ||
1102 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
1103 | ||
1104 | if (ioapic_renumber_irq) | |
1105 | gsi = ioapic_renumber_irq(ioapic, gsi); | |
1106 | ||
1107 | /* | |
1108 | * Avoid pin reprogramming. PRTs typically include entries | |
1109 | * with redundant pin->gsi mappings (but unique PCI devices); | |
1110 | * we only program the IOAPIC on the first. | |
1111 | */ | |
1112 | bit = ioapic_pin % 32; | |
1113 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
1114 | if (idx > 3) { | |
1115 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
1116 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
1117 | ioapic_pin); | |
1118 | return gsi; | |
1119 | } | |
1120 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
1121 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
1122 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
2ba7deef | 1123 | return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); |
1da177e4 LT |
1124 | } |
1125 | ||
1126 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
1127 | ||
2ba7deef LB |
1128 | /* |
1129 | * For GSI >= 64, use IRQ compression | |
1130 | */ | |
1131 | if ((gsi >= IRQ_COMPRESSION_START) | |
1132 | && (triggering == ACPI_LEVEL_SENSITIVE)) { | |
c434b7a6 NP |
1133 | /* |
1134 | * For PCI devices assign IRQs in order, avoiding gaps | |
1135 | * due to unused I/O APIC pins. | |
1136 | */ | |
1137 | int irq = gsi; | |
1138 | if (gsi < MAX_GSI_NUM) { | |
e0c1e9bf KM |
1139 | /* |
1140 | * Retain the VIA chipset work-around (gsi > 15), but | |
1141 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
1142 | * via an override (so it's not on pin 0 of the ioapic), | |
1143 | * and at the same time, the pin 0 interrupt is a PCI | |
1144 | * type. The gsi > 15 test could cause these two pins | |
1145 | * to be shared as IRQ0, and they are not shareable. | |
1146 | * So test for this condition, and if necessary, avoid | |
1147 | * the pin collision. | |
1148 | */ | |
1149 | if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) | |
e1afc3f5 | 1150 | gsi = pci_irq++; |
e1afc3f5 NP |
1151 | /* |
1152 | * Don't assign IRQ used by ACPI SCI | |
1153 | */ | |
cee324b1 | 1154 | if (gsi == acpi_gbl_FADT.sci_interrupt) |
e1afc3f5 | 1155 | gsi = pci_irq++; |
c434b7a6 NP |
1156 | gsi_to_irq[irq] = gsi; |
1157 | } else { | |
1158 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
1159 | return gsi; | |
1160 | } | |
1161 | } | |
1162 | ||
1da177e4 | 1163 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
cb654695 LB |
1164 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
1165 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
1166 | return gsi; |
1167 | } | |
1168 | ||
8466361a | 1169 | #endif /* CONFIG_X86_IO_APIC */ |
888ba6c6 | 1170 | #endif /* CONFIG_ACPI */ |