Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 | 7 | * |
5872fb94 | 8 | * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification. |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
cd76374e | 29 | #include <linux/sysdev.h> |
237a6224 | 30 | #include <linux/io.h> |
1da177e4 | 31 | #include <asm/atomic.h> |
1da177e4 LT |
32 | #include <asm/mtrr.h> |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/proto.h> | |
46a7fa27 | 35 | #include <asm/iommu.h> |
395624fc | 36 | #include <asm/gart.h> |
1da177e4 | 37 | #include <asm/cacheflush.h> |
17a941d8 MBY |
38 | #include <asm/swiotlb.h> |
39 | #include <asm/dma.h> | |
a32073bf | 40 | #include <asm/k8.h> |
1da177e4 | 41 | |
79da0874 | 42 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 43 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
44 | static unsigned long iommu_pages; /* .. and in pages */ |
45 | ||
05fccb0e | 46 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 47 | |
05fccb0e IM |
48 | /* |
49 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
50 | * of only flushing when an mapping is reused. With it true the GART is | |
51 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
52 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
53 | * has been also also seen with Qlogic at least). | |
54 | */ | |
c854c919 | 55 | static int iommu_fullflush = 1; |
1da177e4 | 56 | |
05fccb0e | 57 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 58 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
59 | /* Guarded by iommu_bitmap_lock: */ |
60 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 61 | |
05fccb0e | 62 | static u32 gart_unmapped_entry; |
1da177e4 LT |
63 | |
64 | #define GPTE_VALID 1 | |
65 | #define GPTE_COHERENT 2 | |
66 | #define GPTE_ENCODE(x) \ | |
67 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
68 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
69 | ||
05fccb0e | 70 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
71 | |
72 | #ifdef CONFIG_AGP | |
73 | #define AGPEXTERN extern | |
74 | #else | |
75 | #define AGPEXTERN | |
76 | #endif | |
77 | ||
78 | /* backdoor interface to AGP driver */ | |
79 | AGPEXTERN int agp_memory_reserved; | |
80 | AGPEXTERN __u32 *agp_gatt_table; | |
81 | ||
82 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 83 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 84 | |
7b22ff53 FT |
85 | static unsigned long alloc_iommu(struct device *dev, int size, |
86 | unsigned long align_mask) | |
05fccb0e | 87 | { |
1da177e4 | 88 | unsigned long offset, flags; |
fde9a109 FT |
89 | unsigned long boundary_size; |
90 | unsigned long base_index; | |
91 | ||
92 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
93 | PAGE_SIZE) >> PAGE_SHIFT; | |
05d3ed0a | 94 | boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 95 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 96 | |
05fccb0e | 97 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 98 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 99 | size, base_index, boundary_size, align_mask); |
1da177e4 | 100 | if (offset == -1) { |
3610f211 | 101 | need_flush = true; |
fde9a109 | 102 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
103 | size, base_index, boundary_size, |
104 | align_mask); | |
1da177e4 | 105 | } |
05fccb0e | 106 | if (offset != -1) { |
05fccb0e IM |
107 | next_bit = offset+size; |
108 | if (next_bit >= iommu_pages) { | |
1da177e4 | 109 | next_bit = 0; |
3610f211 | 110 | need_flush = true; |
05fccb0e IM |
111 | } |
112 | } | |
1da177e4 | 113 | if (iommu_fullflush) |
3610f211 | 114 | need_flush = true; |
05fccb0e IM |
115 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
116 | ||
1da177e4 | 117 | return offset; |
05fccb0e | 118 | } |
1da177e4 LT |
119 | |
120 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 121 | { |
1da177e4 | 122 | unsigned long flags; |
05fccb0e | 123 | |
1da177e4 | 124 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 125 | iommu_area_free(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
126 | if (offset >= next_bit) |
127 | next_bit = offset + size; | |
1da177e4 | 128 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 129 | } |
1da177e4 | 130 | |
05fccb0e | 131 | /* |
1da177e4 LT |
132 | * Use global flush state to avoid races with multiple flushers. |
133 | */ | |
a32073bf | 134 | static void flush_gart(void) |
05fccb0e | 135 | { |
1da177e4 | 136 | unsigned long flags; |
05fccb0e | 137 | |
1da177e4 | 138 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
139 | if (need_flush) { |
140 | k8_flush_garts(); | |
3610f211 | 141 | need_flush = false; |
05fccb0e | 142 | } |
1da177e4 | 143 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 144 | } |
1da177e4 | 145 | |
1da177e4 LT |
146 | #ifdef CONFIG_IOMMU_LEAK |
147 | ||
05fccb0e IM |
148 | #define SET_LEAK(x) \ |
149 | do { \ | |
150 | if (iommu_leak_tab) \ | |
151 | iommu_leak_tab[x] = __builtin_return_address(0);\ | |
152 | } while (0) | |
153 | ||
154 | #define CLEAR_LEAK(x) \ | |
155 | do { \ | |
156 | if (iommu_leak_tab) \ | |
157 | iommu_leak_tab[x] = NULL; \ | |
158 | } while (0) | |
1da177e4 LT |
159 | |
160 | /* Debugging aid for drivers that don't free their IOMMU tables */ | |
05fccb0e | 161 | static void **iommu_leak_tab; |
1da177e4 | 162 | static int leak_trace; |
79da0874 | 163 | static int iommu_leak_pages = 20; |
05fccb0e | 164 | |
79da0874 | 165 | static void dump_leak(void) |
1da177e4 LT |
166 | { |
167 | int i; | |
05fccb0e IM |
168 | static int dump; |
169 | ||
170 | if (dump || !iommu_leak_tab) | |
171 | return; | |
1da177e4 | 172 | dump = 1; |
05fccb0e IM |
173 | show_stack(NULL, NULL); |
174 | ||
175 | /* Very crude. dump some from the end of the table too */ | |
176 | printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n", | |
177 | iommu_leak_pages); | |
178 | for (i = 0; i < iommu_leak_pages; i += 2) { | |
179 | printk(KERN_DEBUG "%lu: ", iommu_pages-i); | |
237a6224 JR |
180 | printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], |
181 | 0); | |
05fccb0e IM |
182 | printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' '); |
183 | } | |
184 | printk(KERN_DEBUG "\n"); | |
1da177e4 LT |
185 | } |
186 | #else | |
05fccb0e IM |
187 | # define SET_LEAK(x) |
188 | # define CLEAR_LEAK(x) | |
1da177e4 LT |
189 | #endif |
190 | ||
17a941d8 | 191 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 192 | { |
05fccb0e | 193 | /* |
1da177e4 LT |
194 | * Ran out of IOMMU space for this operation. This is very bad. |
195 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 196 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
197 | * let the Northbridge deal with it. This will result in garbage |
198 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 199 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 200 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
201 | */ |
202 | ||
fc3a8828 | 203 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 204 | |
17a941d8 | 205 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
206 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
207 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
208 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
209 | panic(KERN_ERR | |
210 | "PCI-DMA: Random memory would be DMAed\n"); | |
211 | } | |
1da177e4 | 212 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 213 | dump_leak(); |
1da177e4 | 214 | #endif |
05fccb0e | 215 | } |
1da177e4 | 216 | |
05fccb0e IM |
217 | static inline int |
218 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
219 | { | |
ac4ff656 FT |
220 | return force_iommu || |
221 | !is_buffer_dma_capable(*dev->dma_mask, addr, size); | |
1da177e4 LT |
222 | } |
223 | ||
05fccb0e IM |
224 | static inline int |
225 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
226 | { | |
ac4ff656 | 227 | return !is_buffer_dma_capable(*dev->dma_mask, addr, size); |
1da177e4 LT |
228 | } |
229 | ||
230 | /* Map a single continuous physical area into the IOMMU. | |
231 | * Caller needs to check if the iommu is needed and flush. | |
232 | */ | |
17a941d8 | 233 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 234 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 235 | { |
1477b8e5 | 236 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
7b22ff53 | 237 | unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); |
1da177e4 | 238 | int i; |
05fccb0e | 239 | |
1da177e4 LT |
240 | if (iommu_page == -1) { |
241 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 242 | return phys_mem; |
1da177e4 LT |
243 | if (panic_on_overflow) |
244 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 245 | iommu_full(dev, size, dir); |
1da177e4 LT |
246 | return bad_dma_address; |
247 | } | |
248 | ||
249 | for (i = 0; i < npages; i++) { | |
250 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
251 | SET_LEAK(iommu_page + i); | |
252 | phys_mem += PAGE_SIZE; | |
253 | } | |
254 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
255 | } | |
256 | ||
257 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
258 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
259 | unsigned long offset, size_t size, | |
260 | enum dma_data_direction dir, | |
261 | struct dma_attrs *attrs) | |
1da177e4 | 262 | { |
2be62149 | 263 | unsigned long bus; |
052aedbf | 264 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 265 | |
1da177e4 | 266 | if (!dev) |
6c505ce3 | 267 | dev = &x86_dma_fallback_dev; |
1da177e4 | 268 | |
2be62149 IM |
269 | if (!need_iommu(dev, paddr, size)) |
270 | return paddr; | |
1da177e4 | 271 | |
7b22ff53 FT |
272 | bus = dma_map_area(dev, paddr, size, dir, 0); |
273 | flush_gart(); | |
05fccb0e IM |
274 | |
275 | return bus; | |
17a941d8 MBY |
276 | } |
277 | ||
7c2d9cd2 JM |
278 | /* |
279 | * Free a DMA mapping. | |
280 | */ | |
052aedbf FT |
281 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
282 | size_t size, enum dma_data_direction dir, | |
283 | struct dma_attrs *attrs) | |
7c2d9cd2 JM |
284 | { |
285 | unsigned long iommu_page; | |
286 | int npages; | |
287 | int i; | |
288 | ||
289 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
290 | dma_addr >= iommu_bus_base + iommu_size) | |
291 | return; | |
05fccb0e | 292 | |
7c2d9cd2 | 293 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 294 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
295 | for (i = 0; i < npages; i++) { |
296 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
297 | CLEAR_LEAK(iommu_page + i); | |
298 | } | |
299 | free_iommu(iommu_page, npages); | |
300 | } | |
301 | ||
17a941d8 MBY |
302 | /* |
303 | * Wrapper for pci_unmap_single working with scatterlists. | |
304 | */ | |
160c1d8e FT |
305 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
306 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
17a941d8 | 307 | { |
9ee1bea4 | 308 | struct scatterlist *s; |
17a941d8 MBY |
309 | int i; |
310 | ||
9ee1bea4 | 311 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 312 | if (!s->dma_length || !s->length) |
17a941d8 | 313 | break; |
d7dff840 | 314 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL); |
17a941d8 MBY |
315 | } |
316 | } | |
1da177e4 LT |
317 | |
318 | /* Fallback for dma_map_sg in case of overflow */ | |
319 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
320 | int nents, int dir) | |
321 | { | |
9ee1bea4 | 322 | struct scatterlist *s; |
1da177e4 LT |
323 | int i; |
324 | ||
325 | #ifdef CONFIG_IOMMU_DEBUG | |
326 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
327 | #endif | |
328 | ||
9ee1bea4 | 329 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 330 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
331 | |
332 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 333 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
05fccb0e IM |
334 | if (addr == bad_dma_address) { |
335 | if (i > 0) | |
160c1d8e | 336 | gart_unmap_sg(dev, sg, i, dir, NULL); |
05fccb0e | 337 | nents = 0; |
1da177e4 LT |
338 | sg[0].dma_length = 0; |
339 | break; | |
340 | } | |
341 | } | |
342 | s->dma_address = addr; | |
343 | s->dma_length = s->length; | |
344 | } | |
a32073bf | 345 | flush_gart(); |
05fccb0e | 346 | |
1da177e4 LT |
347 | return nents; |
348 | } | |
349 | ||
350 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
351 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
352 | int nelems, struct scatterlist *sout, | |
353 | unsigned long pages) | |
1da177e4 | 354 | { |
7b22ff53 | 355 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 356 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 357 | struct scatterlist *s; |
1da177e4 LT |
358 | int i; |
359 | ||
360 | if (iommu_start == -1) | |
361 | return -1; | |
9ee1bea4 JA |
362 | |
363 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
364 | unsigned long pages, addr; |
365 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 366 | |
9ee1bea4 JA |
367 | BUG_ON(s != start && s->offset); |
368 | if (s == start) { | |
1da177e4 LT |
369 | sout->dma_address = iommu_bus_base; |
370 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
371 | sout->dma_length = s->length; | |
05fccb0e IM |
372 | } else { |
373 | sout->dma_length += s->length; | |
1da177e4 LT |
374 | } |
375 | ||
376 | addr = phys_addr; | |
1477b8e5 | 377 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
378 | while (pages--) { |
379 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
380 | SET_LEAK(iommu_page); |
381 | addr += PAGE_SIZE; | |
382 | iommu_page++; | |
0d541064 | 383 | } |
05fccb0e IM |
384 | } |
385 | BUG_ON(iommu_page - iommu_start != pages); | |
386 | ||
1da177e4 LT |
387 | return 0; |
388 | } | |
389 | ||
05fccb0e | 390 | static inline int |
fde9a109 FT |
391 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
392 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 393 | { |
9ee1bea4 JA |
394 | if (!need) { |
395 | BUG_ON(nelems != 1); | |
e88a39de | 396 | sout->dma_address = start->dma_address; |
9ee1bea4 | 397 | sout->dma_length = start->length; |
1da177e4 | 398 | return 0; |
9ee1bea4 | 399 | } |
fde9a109 | 400 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 401 | } |
05fccb0e | 402 | |
1da177e4 LT |
403 | /* |
404 | * DMA map all entries in a scatterlist. | |
05fccb0e | 405 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 406 | */ |
160c1d8e FT |
407 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
408 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1da177e4 | 409 | { |
9ee1bea4 | 410 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
411 | int need = 0, nextneed, i, out, start; |
412 | unsigned long pages = 0; | |
42d00284 FT |
413 | unsigned int seg_size; |
414 | unsigned int max_seg_size; | |
1da177e4 | 415 | |
05fccb0e | 416 | if (nents == 0) |
1da177e4 LT |
417 | return 0; |
418 | ||
1da177e4 | 419 | if (!dev) |
6c505ce3 | 420 | dev = &x86_dma_fallback_dev; |
1da177e4 LT |
421 | |
422 | out = 0; | |
423 | start = 0; | |
9ee1bea4 | 424 | start_sg = sgmap = sg; |
42d00284 FT |
425 | seg_size = 0; |
426 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
427 | ps = NULL; /* shut up gcc */ |
428 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 429 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 430 | |
1da177e4 | 431 | s->dma_address = addr; |
05fccb0e | 432 | BUG_ON(s->length == 0); |
1da177e4 | 433 | |
05fccb0e | 434 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
435 | |
436 | /* Handle the previous not yet processed entries */ | |
437 | if (i > start) { | |
05fccb0e IM |
438 | /* |
439 | * Can only merge when the last chunk ends on a | |
440 | * page boundary and the new one doesn't have an | |
441 | * offset. | |
442 | */ | |
1da177e4 | 443 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 444 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 445 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
446 | if (dma_map_cont(dev, start_sg, i - start, |
447 | sgmap, pages, need) < 0) | |
1da177e4 LT |
448 | goto error; |
449 | out++; | |
42d00284 | 450 | seg_size = 0; |
9ee1bea4 | 451 | sgmap = sg_next(sgmap); |
1da177e4 | 452 | pages = 0; |
9ee1bea4 JA |
453 | start = i; |
454 | start_sg = s; | |
1da177e4 LT |
455 | } |
456 | } | |
457 | ||
42d00284 | 458 | seg_size += s->length; |
1da177e4 | 459 | need = nextneed; |
1477b8e5 | 460 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 461 | ps = s; |
1da177e4 | 462 | } |
fde9a109 | 463 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
464 | goto error; |
465 | out++; | |
a32073bf | 466 | flush_gart(); |
9ee1bea4 JA |
467 | if (out < nents) { |
468 | sgmap = sg_next(sgmap); | |
469 | sgmap->dma_length = 0; | |
470 | } | |
1da177e4 LT |
471 | return out; |
472 | ||
473 | error: | |
a32073bf | 474 | flush_gart(); |
160c1d8e | 475 | gart_unmap_sg(dev, sg, out, dir, NULL); |
05fccb0e | 476 | |
a1002a48 KV |
477 | /* When it was forced or merged try again in a dumb way */ |
478 | if (force_iommu || iommu_merge) { | |
479 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
480 | if (out > 0) | |
481 | return out; | |
482 | } | |
1da177e4 LT |
483 | if (panic_on_overflow) |
484 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 485 | |
17a941d8 | 486 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
487 | for_each_sg(sg, s, nents, i) |
488 | s->dma_address = bad_dma_address; | |
1da177e4 | 489 | return 0; |
05fccb0e | 490 | } |
1da177e4 | 491 | |
94581094 JR |
492 | /* allocate and map a coherent mapping */ |
493 | static void * | |
494 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
495 | gfp_t flag) | |
496 | { | |
f6a32a36 | 497 | dma_addr_t paddr; |
421076e2 | 498 | unsigned long align_mask; |
1d990882 FT |
499 | struct page *page; |
500 | ||
501 | if (force_iommu && !(flag & GFP_DMA)) { | |
502 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
503 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
504 | if (!page) | |
505 | return NULL; | |
506 | ||
507 | align_mask = (1UL << get_order(size)) - 1; | |
508 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
509 | DMA_BIDIRECTIONAL, align_mask); | |
510 | ||
511 | flush_gart(); | |
512 | if (paddr != bad_dma_address) { | |
513 | *dma_addr = paddr; | |
514 | return page_address(page); | |
515 | } | |
516 | __free_pages(page, get_order(size)); | |
517 | } else | |
518 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag); | |
94581094 JR |
519 | |
520 | return NULL; | |
521 | } | |
522 | ||
43a5a5a0 JR |
523 | /* free a coherent mapping */ |
524 | static void | |
525 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
526 | dma_addr_t dma_addr) | |
527 | { | |
d7dff840 | 528 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL); |
43a5a5a0 JR |
529 | free_pages((unsigned long)vaddr, get_order(size)); |
530 | } | |
531 | ||
17a941d8 | 532 | static int no_agp; |
1da177e4 LT |
533 | |
534 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
535 | { |
536 | unsigned long a; | |
537 | ||
538 | if (!iommu_size) { | |
539 | iommu_size = aper_size; | |
540 | if (!no_agp) | |
541 | iommu_size /= 2; | |
542 | } | |
543 | ||
544 | a = aper + iommu_size; | |
31422c51 | 545 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 546 | |
05fccb0e | 547 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 548 | printk(KERN_WARNING |
05fccb0e IM |
549 | "PCI-DMA: Warning: Small IOMMU %luMB." |
550 | " Consider increasing the AGP aperture in BIOS\n", | |
551 | iommu_size >> 20); | |
552 | } | |
553 | ||
1da177e4 | 554 | return iommu_size; |
05fccb0e | 555 | } |
1da177e4 | 556 | |
05fccb0e IM |
557 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
558 | { | |
559 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 560 | u64 aper_base; |
1da177e4 | 561 | |
3bb6fbf9 PM |
562 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
563 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 564 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 565 | |
05fccb0e | 566 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
567 | aper_base <<= 25; |
568 | ||
05fccb0e IM |
569 | aper_size = (32 * 1024 * 1024) << aper_order; |
570 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
571 | aper_base = 0; |
572 | ||
573 | *size = aper_size; | |
574 | return aper_base; | |
05fccb0e | 575 | } |
1da177e4 | 576 | |
6703f6d1 RW |
577 | static void enable_gart_translations(void) |
578 | { | |
579 | int i; | |
580 | ||
581 | for (i = 0; i < num_k8_northbridges; i++) { | |
582 | struct pci_dev *dev = k8_northbridges[i]; | |
583 | ||
584 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
585 | } | |
586 | } | |
587 | ||
588 | /* | |
589 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
590 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
591 | */ | |
592 | static bool fix_up_north_bridges; | |
593 | static u32 aperture_order; | |
594 | static u32 aperture_alloc; | |
595 | ||
596 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
597 | { | |
598 | fix_up_north_bridges = true; | |
599 | aperture_order = aper_order; | |
600 | aperture_alloc = aper_alloc; | |
601 | } | |
602 | ||
cd76374e PM |
603 | static int gart_resume(struct sys_device *dev) |
604 | { | |
6703f6d1 RW |
605 | printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n"); |
606 | ||
607 | if (fix_up_north_bridges) { | |
608 | int i; | |
609 | ||
610 | printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n"); | |
611 | ||
612 | for (i = 0; i < num_k8_northbridges; i++) { | |
613 | struct pci_dev *dev = k8_northbridges[i]; | |
614 | ||
615 | /* | |
616 | * Don't enable translations just yet. That is the next | |
617 | * step. Restore the pre-suspend aperture settings. | |
618 | */ | |
619 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, | |
620 | aperture_order << 1); | |
621 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, | |
622 | aperture_alloc >> 25); | |
623 | } | |
624 | } | |
625 | ||
626 | enable_gart_translations(); | |
627 | ||
cd76374e PM |
628 | return 0; |
629 | } | |
630 | ||
631 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
632 | { | |
6703f6d1 | 633 | return 0; |
cd76374e PM |
634 | } |
635 | ||
636 | static struct sysdev_class gart_sysdev_class = { | |
637 | .name = "gart", | |
638 | .suspend = gart_suspend, | |
639 | .resume = gart_resume, | |
640 | ||
641 | }; | |
642 | ||
643 | static struct sys_device device_gart = { | |
644 | .id = 0, | |
645 | .cls = &gart_sysdev_class, | |
646 | }; | |
647 | ||
05fccb0e | 648 | /* |
1da177e4 | 649 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 650 | * AGP driver for some reason. |
1da177e4 LT |
651 | */ |
652 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
653 | { |
654 | unsigned aper_size, gatt_size, new_aper_size; | |
655 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
656 | struct pci_dev *dev; |
657 | void *gatt; | |
cd76374e | 658 | int i, error; |
a32073bf | 659 | |
1da177e4 LT |
660 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
661 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
662 | dev = NULL; |
663 | for (i = 0; i < num_k8_northbridges; i++) { | |
664 | dev = k8_northbridges[i]; | |
05fccb0e IM |
665 | new_aper_base = read_aperture(dev, &new_aper_size); |
666 | if (!new_aper_base) | |
667 | goto nommu; | |
668 | ||
669 | if (!aper_base) { | |
1da177e4 LT |
670 | aper_size = new_aper_size; |
671 | aper_base = new_aper_base; | |
05fccb0e IM |
672 | } |
673 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
674 | goto nommu; |
675 | } | |
676 | if (!aper_base) | |
05fccb0e | 677 | goto nommu; |
1da177e4 | 678 | info->aper_base = aper_base; |
05fccb0e | 679 | info->aper_size = aper_size >> 20; |
1da177e4 | 680 | |
05fccb0e | 681 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
682 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
683 | get_order(gatt_size)); | |
05fccb0e | 684 | if (!gatt) |
cf6387da | 685 | panic("Cannot allocate GATT table"); |
6d238cc4 | 686 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 687 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 688 | |
1da177e4 | 689 | agp_gatt_table = gatt; |
a32073bf | 690 | |
6703f6d1 | 691 | enable_gart_translations(); |
cd76374e PM |
692 | |
693 | error = sysdev_class_register(&gart_sysdev_class); | |
694 | if (!error) | |
695 | error = sysdev_register(&device_gart); | |
696 | if (error) | |
237a6224 JR |
697 | panic("Could not register gart_sysdev -- " |
698 | "would corrupt data on next suspend"); | |
6703f6d1 | 699 | |
a32073bf | 700 | flush_gart(); |
05fccb0e IM |
701 | |
702 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
703 | aper_base, aper_size>>10); | |
7ab073b6 | 704 | |
1da177e4 LT |
705 | return 0; |
706 | ||
707 | nommu: | |
05fccb0e | 708 | /* Should not happen anymore */ |
8f59610d PM |
709 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
710 | KERN_WARNING "falling back to iommu=soft.\n"); | |
05fccb0e IM |
711 | return -1; |
712 | } | |
1da177e4 | 713 | |
160c1d8e | 714 | static struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
715 | .map_sg = gart_map_sg, |
716 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
717 | .map_page = gart_map_page, |
718 | .unmap_page = gart_unmap_page, | |
94581094 | 719 | .alloc_coherent = gart_alloc_coherent, |
43a5a5a0 | 720 | .free_coherent = gart_free_coherent, |
17a941d8 MBY |
721 | }; |
722 | ||
bc2cea6a YL |
723 | void gart_iommu_shutdown(void) |
724 | { | |
725 | struct pci_dev *dev; | |
726 | int i; | |
727 | ||
728 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
729 | return; | |
730 | ||
05fccb0e IM |
731 | for (i = 0; i < num_k8_northbridges; i++) { |
732 | u32 ctl; | |
bc2cea6a | 733 | |
05fccb0e | 734 | dev = k8_northbridges[i]; |
3bb6fbf9 | 735 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 736 | |
3bb6fbf9 | 737 | ctl &= ~GARTEN; |
bc2cea6a | 738 | |
3bb6fbf9 | 739 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 740 | } |
bc2cea6a YL |
741 | } |
742 | ||
0dc243ae | 743 | void __init gart_iommu_init(void) |
05fccb0e | 744 | { |
1da177e4 | 745 | struct agp_kern_info info; |
1da177e4 | 746 | unsigned long iommu_start; |
d99e9016 YL |
747 | unsigned long aper_base, aper_size; |
748 | unsigned long start_pfn, end_pfn; | |
1da177e4 LT |
749 | unsigned long scratch; |
750 | long i; | |
751 | ||
55aab5f4 | 752 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) |
0dc243ae | 753 | return; |
a32073bf | 754 | |
1da177e4 | 755 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 756 | no_agp = 1; |
1da177e4 LT |
757 | #else |
758 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
759 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
760 | no_agp = no_agp || |
761 | (agp_amd64_init() < 0) || | |
1da177e4 | 762 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 763 | #endif |
1da177e4 | 764 | |
60b08c67 | 765 | if (swiotlb) |
0dc243ae | 766 | return; |
60b08c67 | 767 | |
8d4f6b93 | 768 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 769 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 770 | return; |
8d4f6b93 | 771 | |
1da177e4 | 772 | if (no_iommu || |
c987d12f | 773 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 774 | !gart_iommu_aperture || |
1da177e4 | 775 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 776 | if (max_pfn > MAX_DMA32_PFN) { |
8f59610d | 777 | printk(KERN_WARNING "More than 4GB of memory " |
237a6224 JR |
778 | "but GART IOMMU not available.\n"); |
779 | printk(KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 780 | } |
0dc243ae | 781 | return; |
1da177e4 LT |
782 | } |
783 | ||
d99e9016 YL |
784 | /* need to map that range */ |
785 | aper_size = info.aper_size << 20; | |
786 | aper_base = info.aper_base; | |
787 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
788 | if (end_pfn > max_low_pfn_mapped) { | |
789 | start_pfn = (aper_base>>PAGE_SHIFT); | |
790 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
791 | } | |
792 | ||
5b7b644c | 793 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
794 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
795 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
796 | ||
0114267b | 797 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
798 | get_order(iommu_pages/8)); |
799 | if (!iommu_gart_bitmap) | |
800 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
801 | |
802 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e | 803 | if (leak_trace) { |
0114267b | 804 | iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, |
1da177e4 | 805 | get_order(iommu_pages*sizeof(void *))); |
0114267b | 806 | if (!iommu_leak_tab) |
05fccb0e IM |
807 | printk(KERN_DEBUG |
808 | "PCI-DMA: Cannot allocate leak trace area\n"); | |
809 | } | |
1da177e4 LT |
810 | #endif |
811 | ||
05fccb0e | 812 | /* |
1da177e4 | 813 | * Out of IOMMU space handling. |
05fccb0e IM |
814 | * Reserve some invalid pages at the beginning of the GART. |
815 | */ | |
d26dbc5c | 816 | iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 817 | |
05fccb0e | 818 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
819 | printk(KERN_INFO |
820 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 821 | iommu_size >> 20); |
1da177e4 | 822 | |
05fccb0e IM |
823 | iommu_start = aper_size - iommu_size; |
824 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
825 | bad_dma_address = iommu_bus_base; |
826 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
827 | ||
05fccb0e | 828 | /* |
1da177e4 LT |
829 | * Unmap the IOMMU part of the GART. The alias of the page is |
830 | * always mapped with cache enabled and there is no full cache | |
831 | * coherency across the GART remapping. The unmapping avoids | |
832 | * automatic prefetches from the CPU allocating cache lines in | |
833 | * there. All CPU accesses are done via the direct mapping to | |
834 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 835 | * devices. |
1da177e4 | 836 | */ |
28d6ee41 AK |
837 | set_memory_np((unsigned long)__va(iommu_bus_base), |
838 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
839 | /* |
840 | * Tricky. The GART table remaps the physical memory range, | |
841 | * so the CPU wont notice potential aliases and if the memory | |
842 | * is remapped to UC later on, we might surprise the PCI devices | |
843 | * with a stray writeout of a cacheline. So play it sure and | |
844 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
845 | * the pages as Not-Present: | |
846 | */ | |
847 | wbinvd(); | |
1da177e4 | 848 | |
05fccb0e | 849 | /* |
fa3d319a | 850 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 851 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 852 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 853 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 854 | */ |
05fccb0e IM |
855 | scratch = get_zeroed_page(GFP_KERNEL); |
856 | if (!scratch) | |
1da177e4 LT |
857 | panic("Cannot allocate iommu scratch page"); |
858 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 859 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
860 | iommu_gatt_base[i] = gart_unmapped_entry; |
861 | ||
a32073bf | 862 | flush_gart(); |
17a941d8 | 863 | dma_ops = &gart_dma_ops; |
05fccb0e | 864 | } |
1da177e4 | 865 | |
43999d9e | 866 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
867 | { |
868 | int arg; | |
869 | ||
1da177e4 | 870 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 871 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
872 | leak_trace = 1; |
873 | p += 4; | |
237a6224 JR |
874 | if (*p == '=') |
875 | ++p; | |
17a941d8 MBY |
876 | if (isdigit(*p) && get_option(&p, &arg)) |
877 | iommu_leak_pages = arg; | |
878 | } | |
1da177e4 | 879 | #endif |
17a941d8 MBY |
880 | if (isdigit(*p) && get_option(&p, &arg)) |
881 | iommu_size = arg; | |
05fccb0e | 882 | if (!strncmp(p, "fullflush", 8)) |
17a941d8 | 883 | iommu_fullflush = 1; |
05fccb0e | 884 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 885 | iommu_fullflush = 0; |
05fccb0e | 886 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 887 | no_agp = 1; |
05fccb0e | 888 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
889 | fix_aperture = 0; |
890 | /* duplicated from pci-dma.c */ | |
05fccb0e | 891 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 892 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 893 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 894 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
895 | if (!strncmp(p, "memaper", 7)) { |
896 | fallback_aper_force = 1; | |
897 | p += 7; | |
898 | if (*p == '=') { | |
899 | ++p; | |
900 | if (get_option(&p, &arg)) | |
901 | fallback_aper_order = arg; | |
902 | } | |
903 | } | |
904 | } |