Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 | 7 | * |
5872fb94 | 8 | * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification. |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
cd76374e | 29 | #include <linux/sysdev.h> |
237a6224 | 30 | #include <linux/io.h> |
1da177e4 | 31 | #include <asm/atomic.h> |
1da177e4 LT |
32 | #include <asm/mtrr.h> |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/proto.h> | |
46a7fa27 | 35 | #include <asm/iommu.h> |
395624fc | 36 | #include <asm/gart.h> |
1da177e4 | 37 | #include <asm/cacheflush.h> |
17a941d8 MBY |
38 | #include <asm/swiotlb.h> |
39 | #include <asm/dma.h> | |
a32073bf | 40 | #include <asm/k8.h> |
1da177e4 | 41 | |
79da0874 | 42 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 43 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
44 | static unsigned long iommu_pages; /* .. and in pages */ |
45 | ||
05fccb0e | 46 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 47 | |
05fccb0e IM |
48 | /* |
49 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
50 | * of only flushing when an mapping is reused. With it true the GART is | |
51 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
52 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
53 | * has been also also seen with Qlogic at least). | |
54 | */ | |
c854c919 | 55 | static int iommu_fullflush = 1; |
1da177e4 | 56 | |
05fccb0e | 57 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 58 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
59 | /* Guarded by iommu_bitmap_lock: */ |
60 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 61 | |
05fccb0e | 62 | static u32 gart_unmapped_entry; |
1da177e4 LT |
63 | |
64 | #define GPTE_VALID 1 | |
65 | #define GPTE_COHERENT 2 | |
66 | #define GPTE_ENCODE(x) \ | |
67 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
68 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
69 | ||
05fccb0e | 70 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
71 | |
72 | #ifdef CONFIG_AGP | |
73 | #define AGPEXTERN extern | |
74 | #else | |
75 | #define AGPEXTERN | |
76 | #endif | |
77 | ||
78 | /* backdoor interface to AGP driver */ | |
79 | AGPEXTERN int agp_memory_reserved; | |
80 | AGPEXTERN __u32 *agp_gatt_table; | |
81 | ||
82 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 83 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 84 | |
7b22ff53 FT |
85 | static unsigned long alloc_iommu(struct device *dev, int size, |
86 | unsigned long align_mask) | |
05fccb0e | 87 | { |
1da177e4 | 88 | unsigned long offset, flags; |
fde9a109 FT |
89 | unsigned long boundary_size; |
90 | unsigned long base_index; | |
91 | ||
92 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
93 | PAGE_SIZE) >> PAGE_SHIFT; | |
05d3ed0a | 94 | boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 95 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 96 | |
05fccb0e | 97 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 98 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 99 | size, base_index, boundary_size, align_mask); |
1da177e4 | 100 | if (offset == -1) { |
3610f211 | 101 | need_flush = true; |
fde9a109 | 102 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
103 | size, base_index, boundary_size, |
104 | align_mask); | |
1da177e4 | 105 | } |
05fccb0e | 106 | if (offset != -1) { |
05fccb0e IM |
107 | next_bit = offset+size; |
108 | if (next_bit >= iommu_pages) { | |
1da177e4 | 109 | next_bit = 0; |
3610f211 | 110 | need_flush = true; |
05fccb0e IM |
111 | } |
112 | } | |
1da177e4 | 113 | if (iommu_fullflush) |
3610f211 | 114 | need_flush = true; |
05fccb0e IM |
115 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
116 | ||
1da177e4 | 117 | return offset; |
05fccb0e | 118 | } |
1da177e4 LT |
119 | |
120 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 121 | { |
1da177e4 | 122 | unsigned long flags; |
05fccb0e | 123 | |
1da177e4 | 124 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 125 | iommu_area_free(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
126 | if (offset >= next_bit) |
127 | next_bit = offset + size; | |
1da177e4 | 128 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 129 | } |
1da177e4 | 130 | |
05fccb0e | 131 | /* |
1da177e4 LT |
132 | * Use global flush state to avoid races with multiple flushers. |
133 | */ | |
a32073bf | 134 | static void flush_gart(void) |
05fccb0e | 135 | { |
1da177e4 | 136 | unsigned long flags; |
05fccb0e | 137 | |
1da177e4 | 138 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
139 | if (need_flush) { |
140 | k8_flush_garts(); | |
3610f211 | 141 | need_flush = false; |
05fccb0e | 142 | } |
1da177e4 | 143 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 144 | } |
1da177e4 | 145 | |
1da177e4 | 146 | #ifdef CONFIG_IOMMU_LEAK |
1da177e4 | 147 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
1da177e4 | 148 | static int leak_trace; |
79da0874 | 149 | static int iommu_leak_pages = 20; |
05fccb0e | 150 | |
79da0874 | 151 | static void dump_leak(void) |
1da177e4 | 152 | { |
05fccb0e IM |
153 | static int dump; |
154 | ||
19c1a6f5 | 155 | if (dump) |
05fccb0e | 156 | return; |
1da177e4 | 157 | dump = 1; |
05fccb0e | 158 | |
19c1a6f5 FT |
159 | show_stack(NULL, NULL); |
160 | debug_dma_dump_mappings(NULL); | |
1da177e4 | 161 | } |
1da177e4 LT |
162 | #endif |
163 | ||
17a941d8 | 164 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 165 | { |
05fccb0e | 166 | /* |
1da177e4 LT |
167 | * Ran out of IOMMU space for this operation. This is very bad. |
168 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 169 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
170 | * let the Northbridge deal with it. This will result in garbage |
171 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 172 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 173 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
174 | */ |
175 | ||
fc3a8828 | 176 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 177 | |
17a941d8 | 178 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
179 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
180 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
181 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
182 | panic(KERN_ERR | |
183 | "PCI-DMA: Random memory would be DMAed\n"); | |
184 | } | |
1da177e4 | 185 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 186 | dump_leak(); |
1da177e4 | 187 | #endif |
05fccb0e | 188 | } |
1da177e4 | 189 | |
05fccb0e IM |
190 | static inline int |
191 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
192 | { | |
ac4ff656 FT |
193 | return force_iommu || |
194 | !is_buffer_dma_capable(*dev->dma_mask, addr, size); | |
1da177e4 LT |
195 | } |
196 | ||
05fccb0e IM |
197 | static inline int |
198 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
199 | { | |
ac4ff656 | 200 | return !is_buffer_dma_capable(*dev->dma_mask, addr, size); |
1da177e4 LT |
201 | } |
202 | ||
203 | /* Map a single continuous physical area into the IOMMU. | |
204 | * Caller needs to check if the iommu is needed and flush. | |
205 | */ | |
17a941d8 | 206 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 207 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 208 | { |
1477b8e5 | 209 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
7b22ff53 | 210 | unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); |
1da177e4 | 211 | int i; |
05fccb0e | 212 | |
1da177e4 LT |
213 | if (iommu_page == -1) { |
214 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 215 | return phys_mem; |
1da177e4 LT |
216 | if (panic_on_overflow) |
217 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 218 | iommu_full(dev, size, dir); |
1da177e4 LT |
219 | return bad_dma_address; |
220 | } | |
221 | ||
222 | for (i = 0; i < npages; i++) { | |
223 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
1da177e4 LT |
224 | phys_mem += PAGE_SIZE; |
225 | } | |
226 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
227 | } | |
228 | ||
229 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
230 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
231 | unsigned long offset, size_t size, | |
232 | enum dma_data_direction dir, | |
233 | struct dma_attrs *attrs) | |
1da177e4 | 234 | { |
2be62149 | 235 | unsigned long bus; |
052aedbf | 236 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 237 | |
1da177e4 | 238 | if (!dev) |
6c505ce3 | 239 | dev = &x86_dma_fallback_dev; |
1da177e4 | 240 | |
2be62149 IM |
241 | if (!need_iommu(dev, paddr, size)) |
242 | return paddr; | |
1da177e4 | 243 | |
7b22ff53 FT |
244 | bus = dma_map_area(dev, paddr, size, dir, 0); |
245 | flush_gart(); | |
05fccb0e IM |
246 | |
247 | return bus; | |
17a941d8 MBY |
248 | } |
249 | ||
7c2d9cd2 JM |
250 | /* |
251 | * Free a DMA mapping. | |
252 | */ | |
052aedbf FT |
253 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
254 | size_t size, enum dma_data_direction dir, | |
255 | struct dma_attrs *attrs) | |
7c2d9cd2 JM |
256 | { |
257 | unsigned long iommu_page; | |
258 | int npages; | |
259 | int i; | |
260 | ||
261 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
262 | dma_addr >= iommu_bus_base + iommu_size) | |
263 | return; | |
05fccb0e | 264 | |
7c2d9cd2 | 265 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 266 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
267 | for (i = 0; i < npages; i++) { |
268 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
7c2d9cd2 JM |
269 | } |
270 | free_iommu(iommu_page, npages); | |
271 | } | |
272 | ||
17a941d8 MBY |
273 | /* |
274 | * Wrapper for pci_unmap_single working with scatterlists. | |
275 | */ | |
160c1d8e FT |
276 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
277 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
17a941d8 | 278 | { |
9ee1bea4 | 279 | struct scatterlist *s; |
17a941d8 MBY |
280 | int i; |
281 | ||
9ee1bea4 | 282 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 283 | if (!s->dma_length || !s->length) |
17a941d8 | 284 | break; |
d7dff840 | 285 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL); |
17a941d8 MBY |
286 | } |
287 | } | |
1da177e4 LT |
288 | |
289 | /* Fallback for dma_map_sg in case of overflow */ | |
290 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
291 | int nents, int dir) | |
292 | { | |
9ee1bea4 | 293 | struct scatterlist *s; |
1da177e4 LT |
294 | int i; |
295 | ||
296 | #ifdef CONFIG_IOMMU_DEBUG | |
297 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
298 | #endif | |
299 | ||
9ee1bea4 | 300 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 301 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
302 | |
303 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 304 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
05fccb0e IM |
305 | if (addr == bad_dma_address) { |
306 | if (i > 0) | |
160c1d8e | 307 | gart_unmap_sg(dev, sg, i, dir, NULL); |
05fccb0e | 308 | nents = 0; |
1da177e4 LT |
309 | sg[0].dma_length = 0; |
310 | break; | |
311 | } | |
312 | } | |
313 | s->dma_address = addr; | |
314 | s->dma_length = s->length; | |
315 | } | |
a32073bf | 316 | flush_gart(); |
05fccb0e | 317 | |
1da177e4 LT |
318 | return nents; |
319 | } | |
320 | ||
321 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
322 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
323 | int nelems, struct scatterlist *sout, | |
324 | unsigned long pages) | |
1da177e4 | 325 | { |
7b22ff53 | 326 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 327 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 328 | struct scatterlist *s; |
1da177e4 LT |
329 | int i; |
330 | ||
331 | if (iommu_start == -1) | |
332 | return -1; | |
9ee1bea4 JA |
333 | |
334 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
335 | unsigned long pages, addr; |
336 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 337 | |
9ee1bea4 JA |
338 | BUG_ON(s != start && s->offset); |
339 | if (s == start) { | |
1da177e4 LT |
340 | sout->dma_address = iommu_bus_base; |
341 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
342 | sout->dma_length = s->length; | |
05fccb0e IM |
343 | } else { |
344 | sout->dma_length += s->length; | |
1da177e4 LT |
345 | } |
346 | ||
347 | addr = phys_addr; | |
1477b8e5 | 348 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
349 | while (pages--) { |
350 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
351 | addr += PAGE_SIZE; |
352 | iommu_page++; | |
0d541064 | 353 | } |
05fccb0e IM |
354 | } |
355 | BUG_ON(iommu_page - iommu_start != pages); | |
356 | ||
1da177e4 LT |
357 | return 0; |
358 | } | |
359 | ||
05fccb0e | 360 | static inline int |
fde9a109 FT |
361 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
362 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 363 | { |
9ee1bea4 JA |
364 | if (!need) { |
365 | BUG_ON(nelems != 1); | |
e88a39de | 366 | sout->dma_address = start->dma_address; |
9ee1bea4 | 367 | sout->dma_length = start->length; |
1da177e4 | 368 | return 0; |
9ee1bea4 | 369 | } |
fde9a109 | 370 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 371 | } |
05fccb0e | 372 | |
1da177e4 LT |
373 | /* |
374 | * DMA map all entries in a scatterlist. | |
05fccb0e | 375 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 376 | */ |
160c1d8e FT |
377 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
378 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1da177e4 | 379 | { |
9ee1bea4 | 380 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
381 | int need = 0, nextneed, i, out, start; |
382 | unsigned long pages = 0; | |
42d00284 FT |
383 | unsigned int seg_size; |
384 | unsigned int max_seg_size; | |
1da177e4 | 385 | |
05fccb0e | 386 | if (nents == 0) |
1da177e4 LT |
387 | return 0; |
388 | ||
1da177e4 | 389 | if (!dev) |
6c505ce3 | 390 | dev = &x86_dma_fallback_dev; |
1da177e4 LT |
391 | |
392 | out = 0; | |
393 | start = 0; | |
9ee1bea4 | 394 | start_sg = sgmap = sg; |
42d00284 FT |
395 | seg_size = 0; |
396 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
397 | ps = NULL; /* shut up gcc */ |
398 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 399 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 400 | |
1da177e4 | 401 | s->dma_address = addr; |
05fccb0e | 402 | BUG_ON(s->length == 0); |
1da177e4 | 403 | |
05fccb0e | 404 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
405 | |
406 | /* Handle the previous not yet processed entries */ | |
407 | if (i > start) { | |
05fccb0e IM |
408 | /* |
409 | * Can only merge when the last chunk ends on a | |
410 | * page boundary and the new one doesn't have an | |
411 | * offset. | |
412 | */ | |
1da177e4 | 413 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 414 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 415 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
416 | if (dma_map_cont(dev, start_sg, i - start, |
417 | sgmap, pages, need) < 0) | |
1da177e4 LT |
418 | goto error; |
419 | out++; | |
42d00284 | 420 | seg_size = 0; |
9ee1bea4 | 421 | sgmap = sg_next(sgmap); |
1da177e4 | 422 | pages = 0; |
9ee1bea4 JA |
423 | start = i; |
424 | start_sg = s; | |
1da177e4 LT |
425 | } |
426 | } | |
427 | ||
42d00284 | 428 | seg_size += s->length; |
1da177e4 | 429 | need = nextneed; |
1477b8e5 | 430 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 431 | ps = s; |
1da177e4 | 432 | } |
fde9a109 | 433 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
434 | goto error; |
435 | out++; | |
a32073bf | 436 | flush_gart(); |
9ee1bea4 JA |
437 | if (out < nents) { |
438 | sgmap = sg_next(sgmap); | |
439 | sgmap->dma_length = 0; | |
440 | } | |
1da177e4 LT |
441 | return out; |
442 | ||
443 | error: | |
a32073bf | 444 | flush_gart(); |
160c1d8e | 445 | gart_unmap_sg(dev, sg, out, dir, NULL); |
05fccb0e | 446 | |
a1002a48 KV |
447 | /* When it was forced or merged try again in a dumb way */ |
448 | if (force_iommu || iommu_merge) { | |
449 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
450 | if (out > 0) | |
451 | return out; | |
452 | } | |
1da177e4 LT |
453 | if (panic_on_overflow) |
454 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 455 | |
17a941d8 | 456 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
457 | for_each_sg(sg, s, nents, i) |
458 | s->dma_address = bad_dma_address; | |
1da177e4 | 459 | return 0; |
05fccb0e | 460 | } |
1da177e4 | 461 | |
94581094 JR |
462 | /* allocate and map a coherent mapping */ |
463 | static void * | |
464 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
465 | gfp_t flag) | |
466 | { | |
f6a32a36 | 467 | dma_addr_t paddr; |
421076e2 | 468 | unsigned long align_mask; |
1d990882 FT |
469 | struct page *page; |
470 | ||
471 | if (force_iommu && !(flag & GFP_DMA)) { | |
472 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
473 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
474 | if (!page) | |
475 | return NULL; | |
476 | ||
477 | align_mask = (1UL << get_order(size)) - 1; | |
478 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
479 | DMA_BIDIRECTIONAL, align_mask); | |
480 | ||
481 | flush_gart(); | |
482 | if (paddr != bad_dma_address) { | |
483 | *dma_addr = paddr; | |
484 | return page_address(page); | |
485 | } | |
486 | __free_pages(page, get_order(size)); | |
487 | } else | |
488 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag); | |
94581094 JR |
489 | |
490 | return NULL; | |
491 | } | |
492 | ||
43a5a5a0 JR |
493 | /* free a coherent mapping */ |
494 | static void | |
495 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
496 | dma_addr_t dma_addr) | |
497 | { | |
d7dff840 | 498 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL); |
43a5a5a0 JR |
499 | free_pages((unsigned long)vaddr, get_order(size)); |
500 | } | |
501 | ||
17a941d8 | 502 | static int no_agp; |
1da177e4 LT |
503 | |
504 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
505 | { |
506 | unsigned long a; | |
507 | ||
508 | if (!iommu_size) { | |
509 | iommu_size = aper_size; | |
510 | if (!no_agp) | |
511 | iommu_size /= 2; | |
512 | } | |
513 | ||
514 | a = aper + iommu_size; | |
31422c51 | 515 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 516 | |
05fccb0e | 517 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 518 | printk(KERN_WARNING |
05fccb0e IM |
519 | "PCI-DMA: Warning: Small IOMMU %luMB." |
520 | " Consider increasing the AGP aperture in BIOS\n", | |
521 | iommu_size >> 20); | |
522 | } | |
523 | ||
1da177e4 | 524 | return iommu_size; |
05fccb0e | 525 | } |
1da177e4 | 526 | |
05fccb0e IM |
527 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
528 | { | |
529 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 530 | u64 aper_base; |
1da177e4 | 531 | |
3bb6fbf9 PM |
532 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
533 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 534 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 535 | |
05fccb0e | 536 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
537 | aper_base <<= 25; |
538 | ||
05fccb0e IM |
539 | aper_size = (32 * 1024 * 1024) << aper_order; |
540 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
541 | aper_base = 0; |
542 | ||
543 | *size = aper_size; | |
544 | return aper_base; | |
05fccb0e | 545 | } |
1da177e4 | 546 | |
6703f6d1 RW |
547 | static void enable_gart_translations(void) |
548 | { | |
549 | int i; | |
550 | ||
551 | for (i = 0; i < num_k8_northbridges; i++) { | |
552 | struct pci_dev *dev = k8_northbridges[i]; | |
553 | ||
554 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
555 | } | |
556 | } | |
557 | ||
558 | /* | |
559 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
560 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
561 | */ | |
562 | static bool fix_up_north_bridges; | |
563 | static u32 aperture_order; | |
564 | static u32 aperture_alloc; | |
565 | ||
566 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
567 | { | |
568 | fix_up_north_bridges = true; | |
569 | aperture_order = aper_order; | |
570 | aperture_alloc = aper_alloc; | |
571 | } | |
572 | ||
cd76374e PM |
573 | static int gart_resume(struct sys_device *dev) |
574 | { | |
6703f6d1 RW |
575 | printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n"); |
576 | ||
577 | if (fix_up_north_bridges) { | |
578 | int i; | |
579 | ||
580 | printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n"); | |
581 | ||
582 | for (i = 0; i < num_k8_northbridges; i++) { | |
583 | struct pci_dev *dev = k8_northbridges[i]; | |
584 | ||
585 | /* | |
586 | * Don't enable translations just yet. That is the next | |
587 | * step. Restore the pre-suspend aperture settings. | |
588 | */ | |
589 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, | |
590 | aperture_order << 1); | |
591 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, | |
592 | aperture_alloc >> 25); | |
593 | } | |
594 | } | |
595 | ||
596 | enable_gart_translations(); | |
597 | ||
cd76374e PM |
598 | return 0; |
599 | } | |
600 | ||
601 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
602 | { | |
6703f6d1 | 603 | return 0; |
cd76374e PM |
604 | } |
605 | ||
606 | static struct sysdev_class gart_sysdev_class = { | |
607 | .name = "gart", | |
608 | .suspend = gart_suspend, | |
609 | .resume = gart_resume, | |
610 | ||
611 | }; | |
612 | ||
613 | static struct sys_device device_gart = { | |
614 | .id = 0, | |
615 | .cls = &gart_sysdev_class, | |
616 | }; | |
617 | ||
05fccb0e | 618 | /* |
1da177e4 | 619 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 620 | * AGP driver for some reason. |
1da177e4 LT |
621 | */ |
622 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
623 | { |
624 | unsigned aper_size, gatt_size, new_aper_size; | |
625 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
626 | struct pci_dev *dev; |
627 | void *gatt; | |
cd76374e | 628 | int i, error; |
a32073bf | 629 | |
1da177e4 LT |
630 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
631 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
632 | dev = NULL; |
633 | for (i = 0; i < num_k8_northbridges; i++) { | |
634 | dev = k8_northbridges[i]; | |
05fccb0e IM |
635 | new_aper_base = read_aperture(dev, &new_aper_size); |
636 | if (!new_aper_base) | |
637 | goto nommu; | |
638 | ||
639 | if (!aper_base) { | |
1da177e4 LT |
640 | aper_size = new_aper_size; |
641 | aper_base = new_aper_base; | |
05fccb0e IM |
642 | } |
643 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
644 | goto nommu; |
645 | } | |
646 | if (!aper_base) | |
05fccb0e | 647 | goto nommu; |
1da177e4 | 648 | info->aper_base = aper_base; |
05fccb0e | 649 | info->aper_size = aper_size >> 20; |
1da177e4 | 650 | |
05fccb0e | 651 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
652 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
653 | get_order(gatt_size)); | |
05fccb0e | 654 | if (!gatt) |
cf6387da | 655 | panic("Cannot allocate GATT table"); |
6d238cc4 | 656 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 657 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 658 | |
1da177e4 | 659 | agp_gatt_table = gatt; |
a32073bf | 660 | |
cd76374e PM |
661 | error = sysdev_class_register(&gart_sysdev_class); |
662 | if (!error) | |
663 | error = sysdev_register(&device_gart); | |
664 | if (error) | |
237a6224 JR |
665 | panic("Could not register gart_sysdev -- " |
666 | "would corrupt data on next suspend"); | |
6703f6d1 | 667 | |
a32073bf | 668 | flush_gart(); |
05fccb0e IM |
669 | |
670 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
671 | aper_base, aper_size>>10); | |
7ab073b6 | 672 | |
1da177e4 LT |
673 | return 0; |
674 | ||
675 | nommu: | |
05fccb0e | 676 | /* Should not happen anymore */ |
8f59610d | 677 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
ad361c98 | 678 | "falling back to iommu=soft.\n"); |
05fccb0e IM |
679 | return -1; |
680 | } | |
1da177e4 | 681 | |
160c1d8e | 682 | static struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
683 | .map_sg = gart_map_sg, |
684 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
685 | .map_page = gart_map_page, |
686 | .unmap_page = gart_unmap_page, | |
94581094 | 687 | .alloc_coherent = gart_alloc_coherent, |
43a5a5a0 | 688 | .free_coherent = gart_free_coherent, |
17a941d8 MBY |
689 | }; |
690 | ||
bc2cea6a YL |
691 | void gart_iommu_shutdown(void) |
692 | { | |
693 | struct pci_dev *dev; | |
694 | int i; | |
695 | ||
696 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
697 | return; | |
698 | ||
05fccb0e IM |
699 | for (i = 0; i < num_k8_northbridges; i++) { |
700 | u32 ctl; | |
bc2cea6a | 701 | |
05fccb0e | 702 | dev = k8_northbridges[i]; |
3bb6fbf9 | 703 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 704 | |
3bb6fbf9 | 705 | ctl &= ~GARTEN; |
bc2cea6a | 706 | |
3bb6fbf9 | 707 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 708 | } |
bc2cea6a YL |
709 | } |
710 | ||
0dc243ae | 711 | void __init gart_iommu_init(void) |
05fccb0e | 712 | { |
1da177e4 | 713 | struct agp_kern_info info; |
1da177e4 | 714 | unsigned long iommu_start; |
d99e9016 YL |
715 | unsigned long aper_base, aper_size; |
716 | unsigned long start_pfn, end_pfn; | |
1da177e4 LT |
717 | unsigned long scratch; |
718 | long i; | |
719 | ||
55aab5f4 | 720 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) |
0dc243ae | 721 | return; |
a32073bf | 722 | |
1da177e4 | 723 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 724 | no_agp = 1; |
1da177e4 LT |
725 | #else |
726 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
727 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
728 | no_agp = no_agp || |
729 | (agp_amd64_init() < 0) || | |
1da177e4 | 730 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 731 | #endif |
1da177e4 | 732 | |
60b08c67 | 733 | if (swiotlb) |
0dc243ae | 734 | return; |
60b08c67 | 735 | |
8d4f6b93 | 736 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 737 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 738 | return; |
8d4f6b93 | 739 | |
1da177e4 | 740 | if (no_iommu || |
c987d12f | 741 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 742 | !gart_iommu_aperture || |
1da177e4 | 743 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 744 | if (max_pfn > MAX_DMA32_PFN) { |
8f59610d | 745 | printk(KERN_WARNING "More than 4GB of memory " |
237a6224 JR |
746 | "but GART IOMMU not available.\n"); |
747 | printk(KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 748 | } |
0dc243ae | 749 | return; |
1da177e4 LT |
750 | } |
751 | ||
d99e9016 YL |
752 | /* need to map that range */ |
753 | aper_size = info.aper_size << 20; | |
754 | aper_base = info.aper_base; | |
755 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
756 | if (end_pfn > max_low_pfn_mapped) { | |
757 | start_pfn = (aper_base>>PAGE_SHIFT); | |
758 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
759 | } | |
760 | ||
5b7b644c | 761 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
762 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
763 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
764 | ||
0114267b | 765 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
766 | get_order(iommu_pages/8)); |
767 | if (!iommu_gart_bitmap) | |
768 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
769 | |
770 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e | 771 | if (leak_trace) { |
19c1a6f5 FT |
772 | int ret; |
773 | ||
774 | ret = dma_debug_resize_entries(iommu_pages); | |
775 | if (ret) | |
05fccb0e | 776 | printk(KERN_DEBUG |
19c1a6f5 | 777 | "PCI-DMA: Cannot trace all the entries\n"); |
05fccb0e | 778 | } |
1da177e4 LT |
779 | #endif |
780 | ||
05fccb0e | 781 | /* |
1da177e4 | 782 | * Out of IOMMU space handling. |
05fccb0e IM |
783 | * Reserve some invalid pages at the beginning of the GART. |
784 | */ | |
d26dbc5c | 785 | iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 786 | |
05fccb0e | 787 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
788 | printk(KERN_INFO |
789 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 790 | iommu_size >> 20); |
1da177e4 | 791 | |
05fccb0e IM |
792 | iommu_start = aper_size - iommu_size; |
793 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
794 | bad_dma_address = iommu_bus_base; |
795 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
796 | ||
05fccb0e | 797 | /* |
1da177e4 LT |
798 | * Unmap the IOMMU part of the GART. The alias of the page is |
799 | * always mapped with cache enabled and there is no full cache | |
800 | * coherency across the GART remapping. The unmapping avoids | |
801 | * automatic prefetches from the CPU allocating cache lines in | |
802 | * there. All CPU accesses are done via the direct mapping to | |
803 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 804 | * devices. |
1da177e4 | 805 | */ |
28d6ee41 AK |
806 | set_memory_np((unsigned long)__va(iommu_bus_base), |
807 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
808 | /* |
809 | * Tricky. The GART table remaps the physical memory range, | |
810 | * so the CPU wont notice potential aliases and if the memory | |
811 | * is remapped to UC later on, we might surprise the PCI devices | |
812 | * with a stray writeout of a cacheline. So play it sure and | |
813 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
814 | * the pages as Not-Present: | |
815 | */ | |
816 | wbinvd(); | |
fe2245c9 ML |
817 | |
818 | /* | |
819 | * Now all caches are flushed and we can safely enable | |
820 | * GART hardware. Doing it early leaves the possibility | |
821 | * of stale cache entries that can lead to GART PTE | |
822 | * errors. | |
823 | */ | |
824 | enable_gart_translations(); | |
1da177e4 | 825 | |
05fccb0e | 826 | /* |
fa3d319a | 827 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 828 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 829 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 830 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 831 | */ |
05fccb0e IM |
832 | scratch = get_zeroed_page(GFP_KERNEL); |
833 | if (!scratch) | |
1da177e4 LT |
834 | panic("Cannot allocate iommu scratch page"); |
835 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 836 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
837 | iommu_gatt_base[i] = gart_unmapped_entry; |
838 | ||
a32073bf | 839 | flush_gart(); |
17a941d8 | 840 | dma_ops = &gart_dma_ops; |
05fccb0e | 841 | } |
1da177e4 | 842 | |
43999d9e | 843 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
844 | { |
845 | int arg; | |
846 | ||
1da177e4 | 847 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 848 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
849 | leak_trace = 1; |
850 | p += 4; | |
237a6224 JR |
851 | if (*p == '=') |
852 | ++p; | |
17a941d8 MBY |
853 | if (isdigit(*p) && get_option(&p, &arg)) |
854 | iommu_leak_pages = arg; | |
855 | } | |
1da177e4 | 856 | #endif |
17a941d8 MBY |
857 | if (isdigit(*p) && get_option(&p, &arg)) |
858 | iommu_size = arg; | |
05fccb0e | 859 | if (!strncmp(p, "fullflush", 8)) |
17a941d8 | 860 | iommu_fullflush = 1; |
05fccb0e | 861 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 862 | iommu_fullflush = 0; |
05fccb0e | 863 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 864 | no_agp = 1; |
05fccb0e | 865 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
866 | fix_aperture = 0; |
867 | /* duplicated from pci-dma.c */ | |
05fccb0e | 868 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 869 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 870 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 871 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
872 | if (!strncmp(p, "memaper", 7)) { |
873 | fallback_aper_force = 1; | |
874 | p += 7; | |
875 | if (*p == '=') { | |
876 | ++p; | |
877 | if (get_option(&p, &arg)) | |
878 | fallback_aper_order = arg; | |
879 | } | |
880 | } | |
881 | } |