Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 LT |
7 | * |
8 | * See Documentation/DMA-mapping.txt for the interface specification. | |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
cd76374e | 29 | #include <linux/sysdev.h> |
1da177e4 LT |
30 | #include <asm/atomic.h> |
31 | #include <asm/io.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/proto.h> | |
46a7fa27 | 35 | #include <asm/iommu.h> |
395624fc | 36 | #include <asm/gart.h> |
1da177e4 | 37 | #include <asm/cacheflush.h> |
17a941d8 MBY |
38 | #include <asm/swiotlb.h> |
39 | #include <asm/dma.h> | |
a32073bf | 40 | #include <asm/k8.h> |
1da177e4 | 41 | |
79da0874 | 42 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 43 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
44 | static unsigned long iommu_pages; /* .. and in pages */ |
45 | ||
05fccb0e | 46 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 47 | |
afa9fdc2 FT |
48 | /* |
49 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
50 | * of only flushing when an mapping is reused. With it true the GART is | |
51 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
52 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
53 | * has been also also seen with Qlogic at least). | |
54 | */ | |
55 | int iommu_fullflush = 1; | |
56 | ||
05fccb0e | 57 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 58 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
59 | /* Guarded by iommu_bitmap_lock: */ |
60 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 61 | |
05fccb0e | 62 | static u32 gart_unmapped_entry; |
1da177e4 LT |
63 | |
64 | #define GPTE_VALID 1 | |
65 | #define GPTE_COHERENT 2 | |
66 | #define GPTE_ENCODE(x) \ | |
67 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
68 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
69 | ||
05fccb0e | 70 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
71 | |
72 | #ifdef CONFIG_AGP | |
73 | #define AGPEXTERN extern | |
74 | #else | |
75 | #define AGPEXTERN | |
76 | #endif | |
77 | ||
78 | /* backdoor interface to AGP driver */ | |
79 | AGPEXTERN int agp_memory_reserved; | |
80 | AGPEXTERN __u32 *agp_gatt_table; | |
81 | ||
82 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
05fccb0e | 83 | static int need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 84 | |
7b22ff53 | 85 | static unsigned long alloc_iommu(struct device *dev, int size, |
ecef533e | 86 | unsigned long align_mask) |
05fccb0e | 87 | { |
1da177e4 | 88 | unsigned long offset, flags; |
fde9a109 FT |
89 | unsigned long boundary_size; |
90 | unsigned long base_index; | |
91 | ||
92 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
93 | PAGE_SIZE) >> PAGE_SHIFT; | |
05d3ed0a | 94 | boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 95 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 96 | |
05fccb0e | 97 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
ecef533e | 98 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 99 | size, base_index, boundary_size, align_mask); |
ecef533e | 100 | if (offset == -1) { |
1da177e4 | 101 | need_flush = 1; |
ecef533e | 102 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
103 | size, base_index, boundary_size, |
104 | align_mask); | |
1da177e4 | 105 | } |
05fccb0e | 106 | if (offset != -1) { |
05fccb0e IM |
107 | next_bit = offset+size; |
108 | if (next_bit >= iommu_pages) { | |
1da177e4 LT |
109 | next_bit = 0; |
110 | need_flush = 1; | |
05fccb0e IM |
111 | } |
112 | } | |
1da177e4 LT |
113 | if (iommu_fullflush) |
114 | need_flush = 1; | |
05fccb0e IM |
115 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
116 | ||
1da177e4 | 117 | return offset; |
05fccb0e | 118 | } |
1da177e4 LT |
119 | |
120 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 121 | { |
1da177e4 | 122 | unsigned long flags; |
05fccb0e | 123 | |
1da177e4 | 124 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 125 | iommu_area_free(iommu_gart_bitmap, offset, size); |
1da177e4 | 126 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 127 | } |
1da177e4 | 128 | |
05fccb0e | 129 | /* |
1da177e4 LT |
130 | * Use global flush state to avoid races with multiple flushers. |
131 | */ | |
a32073bf | 132 | static void flush_gart(void) |
05fccb0e | 133 | { |
1da177e4 | 134 | unsigned long flags; |
05fccb0e | 135 | |
1da177e4 | 136 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
137 | if (need_flush) { |
138 | k8_flush_garts(); | |
1da177e4 | 139 | need_flush = 0; |
05fccb0e | 140 | } |
1da177e4 | 141 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 142 | } |
1da177e4 | 143 | |
1da177e4 LT |
144 | #ifdef CONFIG_IOMMU_LEAK |
145 | ||
05fccb0e IM |
146 | #define SET_LEAK(x) \ |
147 | do { \ | |
148 | if (iommu_leak_tab) \ | |
149 | iommu_leak_tab[x] = __builtin_return_address(0);\ | |
150 | } while (0) | |
151 | ||
152 | #define CLEAR_LEAK(x) \ | |
153 | do { \ | |
154 | if (iommu_leak_tab) \ | |
155 | iommu_leak_tab[x] = NULL; \ | |
156 | } while (0) | |
1da177e4 LT |
157 | |
158 | /* Debugging aid for drivers that don't free their IOMMU tables */ | |
05fccb0e | 159 | static void **iommu_leak_tab; |
1da177e4 | 160 | static int leak_trace; |
79da0874 | 161 | static int iommu_leak_pages = 20; |
05fccb0e | 162 | |
79da0874 | 163 | static void dump_leak(void) |
1da177e4 LT |
164 | { |
165 | int i; | |
05fccb0e IM |
166 | static int dump; |
167 | ||
168 | if (dump || !iommu_leak_tab) | |
169 | return; | |
1da177e4 | 170 | dump = 1; |
05fccb0e IM |
171 | show_stack(NULL, NULL); |
172 | ||
173 | /* Very crude. dump some from the end of the table too */ | |
174 | printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n", | |
175 | iommu_leak_pages); | |
176 | for (i = 0; i < iommu_leak_pages; i += 2) { | |
177 | printk(KERN_DEBUG "%lu: ", iommu_pages-i); | |
bc850d6b | 178 | printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0); |
05fccb0e IM |
179 | printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' '); |
180 | } | |
181 | printk(KERN_DEBUG "\n"); | |
1da177e4 LT |
182 | } |
183 | #else | |
05fccb0e IM |
184 | # define SET_LEAK(x) |
185 | # define CLEAR_LEAK(x) | |
1da177e4 LT |
186 | #endif |
187 | ||
17a941d8 | 188 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 189 | { |
05fccb0e | 190 | /* |
1da177e4 LT |
191 | * Ran out of IOMMU space for this operation. This is very bad. |
192 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 193 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
194 | * let the Northbridge deal with it. This will result in garbage |
195 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 196 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 197 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
198 | */ |
199 | ||
fc3a8828 | 200 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 201 | |
17a941d8 | 202 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
203 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
204 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
205 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
206 | panic(KERN_ERR | |
207 | "PCI-DMA: Random memory would be DMAed\n"); | |
208 | } | |
1da177e4 | 209 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 210 | dump_leak(); |
1da177e4 | 211 | #endif |
05fccb0e | 212 | } |
1da177e4 | 213 | |
05fccb0e IM |
214 | static inline int |
215 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
216 | { | |
ac4ff656 FT |
217 | return force_iommu || |
218 | !is_buffer_dma_capable(*dev->dma_mask, addr, size); | |
1da177e4 LT |
219 | } |
220 | ||
05fccb0e IM |
221 | static inline int |
222 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
223 | { | |
ac4ff656 | 224 | return !is_buffer_dma_capable(*dev->dma_mask, addr, size); |
1da177e4 LT |
225 | } |
226 | ||
227 | /* Map a single continuous physical area into the IOMMU. | |
228 | * Caller needs to check if the iommu is needed and flush. | |
229 | */ | |
17a941d8 | 230 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
ecef533e | 231 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 232 | { |
87e39ea5 | 233 | unsigned long npages = iommu_num_pages(phys_mem, size); |
ecef533e | 234 | unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); |
1da177e4 | 235 | int i; |
05fccb0e | 236 | |
1da177e4 LT |
237 | if (iommu_page == -1) { |
238 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 239 | return phys_mem; |
1da177e4 LT |
240 | if (panic_on_overflow) |
241 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 242 | iommu_full(dev, size, dir); |
1da177e4 LT |
243 | return bad_dma_address; |
244 | } | |
245 | ||
246 | for (i = 0; i < npages; i++) { | |
247 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
248 | SET_LEAK(iommu_page + i); | |
249 | phys_mem += PAGE_SIZE; | |
250 | } | |
251 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
252 | } | |
253 | ||
254 | /* Map a single area into the IOMMU */ | |
05fccb0e | 255 | static dma_addr_t |
2be62149 | 256 | gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir) |
1da177e4 | 257 | { |
2be62149 | 258 | unsigned long bus; |
1da177e4 | 259 | |
1da177e4 | 260 | if (!dev) |
6c505ce3 | 261 | dev = &x86_dma_fallback_dev; |
1da177e4 | 262 | |
2be62149 IM |
263 | if (!need_iommu(dev, paddr, size)) |
264 | return paddr; | |
1da177e4 | 265 | |
ecef533e | 266 | bus = dma_map_area(dev, paddr, size, dir, 0); |
7b22ff53 | 267 | flush_gart(); |
05fccb0e IM |
268 | |
269 | return bus; | |
17a941d8 MBY |
270 | } |
271 | ||
7c2d9cd2 JM |
272 | /* |
273 | * Free a DMA mapping. | |
274 | */ | |
1048fa52 | 275 | static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, |
05fccb0e | 276 | size_t size, int direction) |
7c2d9cd2 JM |
277 | { |
278 | unsigned long iommu_page; | |
279 | int npages; | |
280 | int i; | |
281 | ||
282 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
283 | dma_addr >= iommu_bus_base + iommu_size) | |
284 | return; | |
05fccb0e | 285 | |
7c2d9cd2 | 286 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
87e39ea5 | 287 | npages = iommu_num_pages(dma_addr, size); |
7c2d9cd2 JM |
288 | for (i = 0; i < npages; i++) { |
289 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
290 | CLEAR_LEAK(iommu_page + i); | |
291 | } | |
292 | free_iommu(iommu_page, npages); | |
293 | } | |
294 | ||
17a941d8 MBY |
295 | /* |
296 | * Wrapper for pci_unmap_single working with scatterlists. | |
297 | */ | |
05fccb0e IM |
298 | static void |
299 | gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
17a941d8 | 300 | { |
9ee1bea4 | 301 | struct scatterlist *s; |
17a941d8 MBY |
302 | int i; |
303 | ||
9ee1bea4 | 304 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 305 | if (!s->dma_length || !s->length) |
17a941d8 | 306 | break; |
7c2d9cd2 | 307 | gart_unmap_single(dev, s->dma_address, s->dma_length, dir); |
17a941d8 MBY |
308 | } |
309 | } | |
1da177e4 LT |
310 | |
311 | /* Fallback for dma_map_sg in case of overflow */ | |
312 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
313 | int nents, int dir) | |
314 | { | |
9ee1bea4 | 315 | struct scatterlist *s; |
1da177e4 LT |
316 | int i; |
317 | ||
318 | #ifdef CONFIG_IOMMU_DEBUG | |
319 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
320 | #endif | |
321 | ||
9ee1bea4 | 322 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 323 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
324 | |
325 | if (nonforced_iommu(dev, addr, s->length)) { | |
ecef533e | 326 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
05fccb0e IM |
327 | if (addr == bad_dma_address) { |
328 | if (i > 0) | |
17a941d8 | 329 | gart_unmap_sg(dev, sg, i, dir); |
05fccb0e | 330 | nents = 0; |
1da177e4 LT |
331 | sg[0].dma_length = 0; |
332 | break; | |
333 | } | |
334 | } | |
335 | s->dma_address = addr; | |
336 | s->dma_length = s->length; | |
337 | } | |
a32073bf | 338 | flush_gart(); |
05fccb0e | 339 | |
1da177e4 LT |
340 | return nents; |
341 | } | |
342 | ||
343 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
344 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
345 | int nelems, struct scatterlist *sout, | |
346 | unsigned long pages) | |
1da177e4 | 347 | { |
ecef533e FT |
348 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
349 | unsigned long iommu_page = iommu_start; | |
9ee1bea4 | 350 | struct scatterlist *s; |
1da177e4 LT |
351 | int i; |
352 | ||
353 | if (iommu_start == -1) | |
354 | return -1; | |
9ee1bea4 JA |
355 | |
356 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
357 | unsigned long pages, addr; |
358 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 359 | |
9ee1bea4 JA |
360 | BUG_ON(s != start && s->offset); |
361 | if (s == start) { | |
1da177e4 LT |
362 | sout->dma_address = iommu_bus_base; |
363 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
364 | sout->dma_length = s->length; | |
05fccb0e IM |
365 | } else { |
366 | sout->dma_length += s->length; | |
1da177e4 LT |
367 | } |
368 | ||
369 | addr = phys_addr; | |
87e39ea5 | 370 | pages = iommu_num_pages(s->offset, s->length); |
05fccb0e IM |
371 | while (pages--) { |
372 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
373 | SET_LEAK(iommu_page); |
374 | addr += PAGE_SIZE; | |
375 | iommu_page++; | |
0d541064 | 376 | } |
05fccb0e IM |
377 | } |
378 | BUG_ON(iommu_page - iommu_start != pages); | |
379 | ||
1da177e4 LT |
380 | return 0; |
381 | } | |
382 | ||
05fccb0e | 383 | static inline int |
fde9a109 FT |
384 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
385 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 386 | { |
9ee1bea4 JA |
387 | if (!need) { |
388 | BUG_ON(nelems != 1); | |
e88a39de | 389 | sout->dma_address = start->dma_address; |
9ee1bea4 | 390 | sout->dma_length = start->length; |
1da177e4 | 391 | return 0; |
9ee1bea4 | 392 | } |
fde9a109 | 393 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 394 | } |
05fccb0e | 395 | |
1da177e4 LT |
396 | /* |
397 | * DMA map all entries in a scatterlist. | |
05fccb0e | 398 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 399 | */ |
05fccb0e IM |
400 | static int |
401 | gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
1da177e4 | 402 | { |
9ee1bea4 | 403 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
404 | int need = 0, nextneed, i, out, start; |
405 | unsigned long pages = 0; | |
42d00284 FT |
406 | unsigned int seg_size; |
407 | unsigned int max_seg_size; | |
1da177e4 | 408 | |
05fccb0e | 409 | if (nents == 0) |
1da177e4 LT |
410 | return 0; |
411 | ||
1da177e4 | 412 | if (!dev) |
6c505ce3 | 413 | dev = &x86_dma_fallback_dev; |
1da177e4 LT |
414 | |
415 | out = 0; | |
416 | start = 0; | |
9ee1bea4 | 417 | start_sg = sgmap = sg; |
42d00284 FT |
418 | seg_size = 0; |
419 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
420 | ps = NULL; /* shut up gcc */ |
421 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 422 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 423 | |
1da177e4 | 424 | s->dma_address = addr; |
05fccb0e | 425 | BUG_ON(s->length == 0); |
1da177e4 | 426 | |
05fccb0e | 427 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
428 | |
429 | /* Handle the previous not yet processed entries */ | |
430 | if (i > start) { | |
05fccb0e IM |
431 | /* |
432 | * Can only merge when the last chunk ends on a | |
433 | * page boundary and the new one doesn't have an | |
434 | * offset. | |
435 | */ | |
1da177e4 | 436 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 437 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 438 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
439 | if (dma_map_cont(dev, start_sg, i - start, |
440 | sgmap, pages, need) < 0) | |
1da177e4 LT |
441 | goto error; |
442 | out++; | |
42d00284 | 443 | seg_size = 0; |
9ee1bea4 | 444 | sgmap = sg_next(sgmap); |
1da177e4 | 445 | pages = 0; |
9ee1bea4 JA |
446 | start = i; |
447 | start_sg = s; | |
1da177e4 LT |
448 | } |
449 | } | |
450 | ||
42d00284 | 451 | seg_size += s->length; |
1da177e4 | 452 | need = nextneed; |
87e39ea5 | 453 | pages += iommu_num_pages(s->offset, s->length); |
9ee1bea4 | 454 | ps = s; |
1da177e4 | 455 | } |
fde9a109 | 456 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
457 | goto error; |
458 | out++; | |
a32073bf | 459 | flush_gart(); |
9ee1bea4 JA |
460 | if (out < nents) { |
461 | sgmap = sg_next(sgmap); | |
462 | sgmap->dma_length = 0; | |
463 | } | |
1da177e4 LT |
464 | return out; |
465 | ||
466 | error: | |
a32073bf | 467 | flush_gart(); |
5336940d | 468 | gart_unmap_sg(dev, sg, out, dir); |
05fccb0e | 469 | |
a1002a48 KV |
470 | /* When it was forced or merged try again in a dumb way */ |
471 | if (force_iommu || iommu_merge) { | |
472 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
473 | if (out > 0) | |
474 | return out; | |
475 | } | |
1da177e4 LT |
476 | if (panic_on_overflow) |
477 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 478 | |
17a941d8 | 479 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
480 | for_each_sg(sg, s, nents, i) |
481 | s->dma_address = bad_dma_address; | |
1da177e4 | 482 | return 0; |
05fccb0e | 483 | } |
1da177e4 | 484 | |
94581094 JR |
485 | /* allocate and map a coherent mapping */ |
486 | static void * | |
487 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
488 | gfp_t flag) | |
489 | { | |
f6a32a36 | 490 | dma_addr_t paddr; |
421076e2 | 491 | unsigned long align_mask; |
1d990882 FT |
492 | struct page *page; |
493 | ||
494 | if (force_iommu && !(flag & GFP_DMA)) { | |
495 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
496 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
497 | if (!page) | |
498 | return NULL; | |
499 | ||
500 | align_mask = (1UL << get_order(size)) - 1; | |
501 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
502 | DMA_BIDIRECTIONAL, align_mask); | |
503 | ||
504 | flush_gart(); | |
505 | if (paddr != bad_dma_address) { | |
506 | *dma_addr = paddr; | |
507 | return page_address(page); | |
508 | } | |
509 | __free_pages(page, get_order(size)); | |
510 | } else | |
511 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag); | |
94581094 JR |
512 | |
513 | return NULL; | |
514 | } | |
515 | ||
43a5a5a0 JR |
516 | /* free a coherent mapping */ |
517 | static void | |
518 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
519 | dma_addr_t dma_addr) | |
520 | { | |
521 | gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL); | |
522 | free_pages((unsigned long)vaddr, get_order(size)); | |
523 | } | |
524 | ||
17a941d8 | 525 | static int no_agp; |
1da177e4 LT |
526 | |
527 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
528 | { |
529 | unsigned long a; | |
530 | ||
531 | if (!iommu_size) { | |
532 | iommu_size = aper_size; | |
533 | if (!no_agp) | |
534 | iommu_size /= 2; | |
535 | } | |
536 | ||
537 | a = aper + iommu_size; | |
31422c51 | 538 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 539 | |
05fccb0e | 540 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 541 | printk(KERN_WARNING |
05fccb0e IM |
542 | "PCI-DMA: Warning: Small IOMMU %luMB." |
543 | " Consider increasing the AGP aperture in BIOS\n", | |
544 | iommu_size >> 20); | |
545 | } | |
546 | ||
1da177e4 | 547 | return iommu_size; |
05fccb0e | 548 | } |
1da177e4 | 549 | |
05fccb0e IM |
550 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
551 | { | |
552 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 553 | u64 aper_base; |
1da177e4 | 554 | |
3bb6fbf9 PM |
555 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
556 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 557 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 558 | |
05fccb0e | 559 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
560 | aper_base <<= 25; |
561 | ||
05fccb0e IM |
562 | aper_size = (32 * 1024 * 1024) << aper_order; |
563 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
564 | aper_base = 0; |
565 | ||
566 | *size = aper_size; | |
567 | return aper_base; | |
05fccb0e | 568 | } |
1da177e4 | 569 | |
6703f6d1 RW |
570 | static void enable_gart_translations(void) |
571 | { | |
572 | int i; | |
573 | ||
574 | for (i = 0; i < num_k8_northbridges; i++) { | |
575 | struct pci_dev *dev = k8_northbridges[i]; | |
576 | ||
577 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
578 | } | |
579 | } | |
580 | ||
581 | /* | |
582 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
583 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
584 | */ | |
585 | static bool fix_up_north_bridges; | |
586 | static u32 aperture_order; | |
587 | static u32 aperture_alloc; | |
588 | ||
589 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
590 | { | |
591 | fix_up_north_bridges = true; | |
592 | aperture_order = aper_order; | |
593 | aperture_alloc = aper_alloc; | |
594 | } | |
595 | ||
cd76374e PM |
596 | static int gart_resume(struct sys_device *dev) |
597 | { | |
6703f6d1 RW |
598 | printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n"); |
599 | ||
600 | if (fix_up_north_bridges) { | |
601 | int i; | |
602 | ||
603 | printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n"); | |
604 | ||
605 | for (i = 0; i < num_k8_northbridges; i++) { | |
606 | struct pci_dev *dev = k8_northbridges[i]; | |
607 | ||
608 | /* | |
609 | * Don't enable translations just yet. That is the next | |
610 | * step. Restore the pre-suspend aperture settings. | |
611 | */ | |
612 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, | |
613 | aperture_order << 1); | |
614 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, | |
615 | aperture_alloc >> 25); | |
616 | } | |
617 | } | |
618 | ||
619 | enable_gart_translations(); | |
620 | ||
cd76374e PM |
621 | return 0; |
622 | } | |
623 | ||
624 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
625 | { | |
6703f6d1 | 626 | return 0; |
cd76374e PM |
627 | } |
628 | ||
629 | static struct sysdev_class gart_sysdev_class = { | |
630 | .name = "gart", | |
631 | .suspend = gart_suspend, | |
632 | .resume = gart_resume, | |
633 | ||
634 | }; | |
635 | ||
636 | static struct sys_device device_gart = { | |
637 | .id = 0, | |
638 | .cls = &gart_sysdev_class, | |
639 | }; | |
640 | ||
05fccb0e | 641 | /* |
1da177e4 | 642 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 643 | * AGP driver for some reason. |
1da177e4 LT |
644 | */ |
645 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
646 | { |
647 | unsigned aper_size, gatt_size, new_aper_size; | |
648 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
649 | struct pci_dev *dev; |
650 | void *gatt; | |
cd76374e | 651 | int i, error; |
7ab073b6 | 652 | unsigned long start_pfn, end_pfn; |
a32073bf | 653 | |
1da177e4 LT |
654 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
655 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
656 | dev = NULL; |
657 | for (i = 0; i < num_k8_northbridges; i++) { | |
658 | dev = k8_northbridges[i]; | |
05fccb0e IM |
659 | new_aper_base = read_aperture(dev, &new_aper_size); |
660 | if (!new_aper_base) | |
661 | goto nommu; | |
662 | ||
663 | if (!aper_base) { | |
1da177e4 LT |
664 | aper_size = new_aper_size; |
665 | aper_base = new_aper_base; | |
05fccb0e IM |
666 | } |
667 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
668 | goto nommu; |
669 | } | |
670 | if (!aper_base) | |
05fccb0e | 671 | goto nommu; |
1da177e4 | 672 | info->aper_base = aper_base; |
05fccb0e | 673 | info->aper_size = aper_size >> 20; |
1da177e4 | 674 | |
05fccb0e IM |
675 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
676 | gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size)); | |
677 | if (!gatt) | |
cf6387da | 678 | panic("Cannot allocate GATT table"); |
6d238cc4 | 679 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 680 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 681 | |
05fccb0e | 682 | memset(gatt, 0, gatt_size); |
1da177e4 | 683 | agp_gatt_table = gatt; |
a32073bf | 684 | |
6703f6d1 | 685 | enable_gart_translations(); |
cd76374e PM |
686 | |
687 | error = sysdev_class_register(&gart_sysdev_class); | |
688 | if (!error) | |
689 | error = sysdev_register(&device_gart); | |
690 | if (error) | |
691 | panic("Could not register gart_sysdev -- would corrupt data on next suspend"); | |
6703f6d1 | 692 | |
a32073bf | 693 | flush_gart(); |
05fccb0e IM |
694 | |
695 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
696 | aper_base, aper_size>>10); | |
7ab073b6 YL |
697 | |
698 | /* need to map that range */ | |
699 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
700 | if (end_pfn > max_low_pfn_mapped) { | |
32b23e9a YL |
701 | start_pfn = (aper_base>>PAGE_SHIFT); |
702 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
7ab073b6 | 703 | } |
1da177e4 LT |
704 | return 0; |
705 | ||
706 | nommu: | |
05fccb0e | 707 | /* Should not happen anymore */ |
8f59610d PM |
708 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
709 | KERN_WARNING "falling back to iommu=soft.\n"); | |
05fccb0e IM |
710 | return -1; |
711 | } | |
1da177e4 LT |
712 | |
713 | extern int agp_amd64_init(void); | |
714 | ||
8d8bb39b | 715 | static struct dma_mapping_ops gart_dma_ops = { |
05fccb0e | 716 | .map_single = gart_map_single, |
05fccb0e | 717 | .unmap_single = gart_unmap_single, |
05fccb0e IM |
718 | .map_sg = gart_map_sg, |
719 | .unmap_sg = gart_unmap_sg, | |
94581094 | 720 | .alloc_coherent = gart_alloc_coherent, |
43a5a5a0 | 721 | .free_coherent = gart_free_coherent, |
17a941d8 MBY |
722 | }; |
723 | ||
bc2cea6a YL |
724 | void gart_iommu_shutdown(void) |
725 | { | |
726 | struct pci_dev *dev; | |
727 | int i; | |
728 | ||
729 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
730 | return; | |
731 | ||
05fccb0e IM |
732 | for (i = 0; i < num_k8_northbridges; i++) { |
733 | u32 ctl; | |
bc2cea6a | 734 | |
05fccb0e | 735 | dev = k8_northbridges[i]; |
3bb6fbf9 | 736 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 737 | |
3bb6fbf9 | 738 | ctl &= ~GARTEN; |
bc2cea6a | 739 | |
3bb6fbf9 | 740 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 741 | } |
bc2cea6a YL |
742 | } |
743 | ||
0dc243ae | 744 | void __init gart_iommu_init(void) |
05fccb0e | 745 | { |
1da177e4 | 746 | struct agp_kern_info info; |
1da177e4 | 747 | unsigned long iommu_start; |
05fccb0e | 748 | unsigned long aper_size; |
1da177e4 LT |
749 | unsigned long scratch; |
750 | long i; | |
751 | ||
a32073bf AK |
752 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) { |
753 | printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n"); | |
0dc243ae | 754 | return; |
a32073bf AK |
755 | } |
756 | ||
1da177e4 | 757 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 758 | no_agp = 1; |
1da177e4 LT |
759 | #else |
760 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
761 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
762 | no_agp = no_agp || |
763 | (agp_amd64_init() < 0) || | |
1da177e4 | 764 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 765 | #endif |
1da177e4 | 766 | |
60b08c67 | 767 | if (swiotlb) |
0dc243ae | 768 | return; |
60b08c67 | 769 | |
8d4f6b93 | 770 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 771 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 772 | return; |
8d4f6b93 | 773 | |
1da177e4 | 774 | if (no_iommu || |
c987d12f | 775 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 776 | !gart_iommu_aperture || |
1da177e4 | 777 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 778 | if (max_pfn > MAX_DMA32_PFN) { |
8f59610d PM |
779 | printk(KERN_WARNING "More than 4GB of memory " |
780 | "but GART IOMMU not available.\n" | |
781 | KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 782 | } |
0dc243ae | 783 | return; |
1da177e4 LT |
784 | } |
785 | ||
5b7b644c | 786 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
787 | aper_size = info.aper_size * 1024 * 1024; |
788 | iommu_size = check_iommu_size(info.aper_base, aper_size); | |
789 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
790 | ||
791 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL, | |
792 | get_order(iommu_pages/8)); | |
793 | if (!iommu_gart_bitmap) | |
794 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
795 | memset(iommu_gart_bitmap, 0, iommu_pages/8); |
796 | ||
797 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e IM |
798 | if (leak_trace) { |
799 | iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL, | |
1da177e4 | 800 | get_order(iommu_pages*sizeof(void *))); |
05fccb0e IM |
801 | if (iommu_leak_tab) |
802 | memset(iommu_leak_tab, 0, iommu_pages * 8); | |
1da177e4 | 803 | else |
05fccb0e IM |
804 | printk(KERN_DEBUG |
805 | "PCI-DMA: Cannot allocate leak trace area\n"); | |
806 | } | |
1da177e4 LT |
807 | #endif |
808 | ||
05fccb0e | 809 | /* |
1da177e4 | 810 | * Out of IOMMU space handling. |
05fccb0e IM |
811 | * Reserve some invalid pages at the beginning of the GART. |
812 | */ | |
d26dbc5c | 813 | iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 814 | |
05fccb0e | 815 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
816 | printk(KERN_INFO |
817 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 818 | iommu_size >> 20); |
1da177e4 | 819 | |
05fccb0e IM |
820 | iommu_start = aper_size - iommu_size; |
821 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
822 | bad_dma_address = iommu_bus_base; |
823 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
824 | ||
05fccb0e | 825 | /* |
1da177e4 LT |
826 | * Unmap the IOMMU part of the GART. The alias of the page is |
827 | * always mapped with cache enabled and there is no full cache | |
828 | * coherency across the GART remapping. The unmapping avoids | |
829 | * automatic prefetches from the CPU allocating cache lines in | |
830 | * there. All CPU accesses are done via the direct mapping to | |
831 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 832 | * devices. |
1da177e4 | 833 | */ |
28d6ee41 AK |
834 | set_memory_np((unsigned long)__va(iommu_bus_base), |
835 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
836 | /* |
837 | * Tricky. The GART table remaps the physical memory range, | |
838 | * so the CPU wont notice potential aliases and if the memory | |
839 | * is remapped to UC later on, we might surprise the PCI devices | |
840 | * with a stray writeout of a cacheline. So play it sure and | |
841 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
842 | * the pages as Not-Present: | |
843 | */ | |
844 | wbinvd(); | |
1da177e4 | 845 | |
05fccb0e | 846 | /* |
fa3d319a | 847 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 848 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 849 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 850 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 851 | */ |
05fccb0e IM |
852 | scratch = get_zeroed_page(GFP_KERNEL); |
853 | if (!scratch) | |
1da177e4 LT |
854 | panic("Cannot allocate iommu scratch page"); |
855 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 856 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
857 | iommu_gatt_base[i] = gart_unmapped_entry; |
858 | ||
a32073bf | 859 | flush_gart(); |
17a941d8 | 860 | dma_ops = &gart_dma_ops; |
05fccb0e | 861 | } |
1da177e4 | 862 | |
43999d9e | 863 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
864 | { |
865 | int arg; | |
866 | ||
1da177e4 | 867 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 868 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
869 | leak_trace = 1; |
870 | p += 4; | |
871 | if (*p == '=') ++p; | |
872 | if (isdigit(*p) && get_option(&p, &arg)) | |
873 | iommu_leak_pages = arg; | |
874 | } | |
1da177e4 | 875 | #endif |
17a941d8 MBY |
876 | if (isdigit(*p) && get_option(&p, &arg)) |
877 | iommu_size = arg; | |
afa9fdc2 FT |
878 | if (!strncmp(p, "fullflush", 8)) |
879 | iommu_fullflush = 1; | |
880 | if (!strncmp(p, "nofullflush", 11)) | |
881 | iommu_fullflush = 0; | |
05fccb0e | 882 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 883 | no_agp = 1; |
05fccb0e | 884 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
885 | fix_aperture = 0; |
886 | /* duplicated from pci-dma.c */ | |
05fccb0e | 887 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 888 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 889 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 890 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
891 | if (!strncmp(p, "memaper", 7)) { |
892 | fallback_aper_force = 1; | |
893 | p += 7; | |
894 | if (*p == '=') { | |
895 | ++p; | |
896 | if (get_option(&p, &arg)) | |
897 | fallback_aper_order = arg; | |
898 | } | |
899 | } | |
900 | } |