Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 LT |
7 | * |
8 | * See Documentation/DMA-mapping.txt for the interface specification. | |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
1da177e4 LT |
29 | #include <asm/atomic.h> |
30 | #include <asm/io.h> | |
31 | #include <asm/mtrr.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/proto.h> | |
395624fc | 34 | #include <asm/gart.h> |
1da177e4 | 35 | #include <asm/cacheflush.h> |
17a941d8 MBY |
36 | #include <asm/swiotlb.h> |
37 | #include <asm/dma.h> | |
a32073bf | 38 | #include <asm/k8.h> |
1da177e4 | 39 | |
79da0874 | 40 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 41 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
42 | static unsigned long iommu_pages; /* .. and in pages */ |
43 | ||
05fccb0e | 44 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 45 | |
05fccb0e IM |
46 | /* |
47 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
48 | * of only flushing when an mapping is reused. With it true the GART is | |
49 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
50 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
51 | * has been also also seen with Qlogic at least). | |
52 | */ | |
1da177e4 LT |
53 | int iommu_fullflush = 1; |
54 | ||
05fccb0e | 55 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 56 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
57 | /* Guarded by iommu_bitmap_lock: */ |
58 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 59 | |
05fccb0e | 60 | static u32 gart_unmapped_entry; |
1da177e4 LT |
61 | |
62 | #define GPTE_VALID 1 | |
63 | #define GPTE_COHERENT 2 | |
64 | #define GPTE_ENCODE(x) \ | |
65 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
66 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
67 | ||
05fccb0e | 68 | #define to_pages(addr, size) \ |
1da177e4 LT |
69 | (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) |
70 | ||
05fccb0e | 71 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
72 | |
73 | #ifdef CONFIG_AGP | |
74 | #define AGPEXTERN extern | |
75 | #else | |
76 | #define AGPEXTERN | |
77 | #endif | |
78 | ||
79 | /* backdoor interface to AGP driver */ | |
80 | AGPEXTERN int agp_memory_reserved; | |
81 | AGPEXTERN __u32 *agp_gatt_table; | |
82 | ||
83 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
05fccb0e | 84 | static int need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 85 | |
fde9a109 | 86 | static unsigned long alloc_iommu(struct device *dev, int size) |
05fccb0e | 87 | { |
1da177e4 | 88 | unsigned long offset, flags; |
fde9a109 FT |
89 | unsigned long boundary_size; |
90 | unsigned long base_index; | |
91 | ||
92 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
93 | PAGE_SIZE) >> PAGE_SHIFT; | |
94 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
95 | PAGE_SIZE) >> PAGE_SHIFT; | |
1da177e4 | 96 | |
05fccb0e | 97 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 FT |
98 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
99 | size, base_index, boundary_size, 0); | |
1da177e4 LT |
100 | if (offset == -1) { |
101 | need_flush = 1; | |
fde9a109 FT |
102 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
103 | size, base_index, boundary_size, 0); | |
1da177e4 | 104 | } |
05fccb0e IM |
105 | if (offset != -1) { |
106 | set_bit_string(iommu_gart_bitmap, offset, size); | |
107 | next_bit = offset+size; | |
108 | if (next_bit >= iommu_pages) { | |
1da177e4 LT |
109 | next_bit = 0; |
110 | need_flush = 1; | |
05fccb0e IM |
111 | } |
112 | } | |
1da177e4 LT |
113 | if (iommu_fullflush) |
114 | need_flush = 1; | |
05fccb0e IM |
115 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
116 | ||
1da177e4 | 117 | return offset; |
05fccb0e | 118 | } |
1da177e4 LT |
119 | |
120 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 121 | { |
1da177e4 | 122 | unsigned long flags; |
05fccb0e | 123 | |
1da177e4 | 124 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 125 | iommu_area_free(iommu_gart_bitmap, offset, size); |
1da177e4 | 126 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 127 | } |
1da177e4 | 128 | |
05fccb0e | 129 | /* |
1da177e4 LT |
130 | * Use global flush state to avoid races with multiple flushers. |
131 | */ | |
a32073bf | 132 | static void flush_gart(void) |
05fccb0e | 133 | { |
1da177e4 | 134 | unsigned long flags; |
05fccb0e | 135 | |
1da177e4 | 136 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
137 | if (need_flush) { |
138 | k8_flush_garts(); | |
1da177e4 | 139 | need_flush = 0; |
05fccb0e | 140 | } |
1da177e4 | 141 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 142 | } |
1da177e4 | 143 | |
1da177e4 LT |
144 | #ifdef CONFIG_IOMMU_LEAK |
145 | ||
05fccb0e IM |
146 | #define SET_LEAK(x) \ |
147 | do { \ | |
148 | if (iommu_leak_tab) \ | |
149 | iommu_leak_tab[x] = __builtin_return_address(0);\ | |
150 | } while (0) | |
151 | ||
152 | #define CLEAR_LEAK(x) \ | |
153 | do { \ | |
154 | if (iommu_leak_tab) \ | |
155 | iommu_leak_tab[x] = NULL; \ | |
156 | } while (0) | |
1da177e4 LT |
157 | |
158 | /* Debugging aid for drivers that don't free their IOMMU tables */ | |
05fccb0e | 159 | static void **iommu_leak_tab; |
1da177e4 | 160 | static int leak_trace; |
79da0874 | 161 | static int iommu_leak_pages = 20; |
05fccb0e | 162 | |
79da0874 | 163 | static void dump_leak(void) |
1da177e4 LT |
164 | { |
165 | int i; | |
05fccb0e IM |
166 | static int dump; |
167 | ||
168 | if (dump || !iommu_leak_tab) | |
169 | return; | |
1da177e4 | 170 | dump = 1; |
05fccb0e IM |
171 | show_stack(NULL, NULL); |
172 | ||
173 | /* Very crude. dump some from the end of the table too */ | |
174 | printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n", | |
175 | iommu_leak_pages); | |
176 | for (i = 0; i < iommu_leak_pages; i += 2) { | |
177 | printk(KERN_DEBUG "%lu: ", iommu_pages-i); | |
bc850d6b | 178 | printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0); |
05fccb0e IM |
179 | printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' '); |
180 | } | |
181 | printk(KERN_DEBUG "\n"); | |
1da177e4 LT |
182 | } |
183 | #else | |
05fccb0e IM |
184 | # define SET_LEAK(x) |
185 | # define CLEAR_LEAK(x) | |
1da177e4 LT |
186 | #endif |
187 | ||
17a941d8 | 188 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 189 | { |
05fccb0e | 190 | /* |
1da177e4 LT |
191 | * Ran out of IOMMU space for this operation. This is very bad. |
192 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 193 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
194 | * let the Northbridge deal with it. This will result in garbage |
195 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 196 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 197 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
198 | */ |
199 | ||
200 | printk(KERN_ERR | |
201 | "PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n", | |
202 | size, dev->bus_id); | |
1da177e4 | 203 | |
17a941d8 | 204 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
205 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
206 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
207 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
208 | panic(KERN_ERR | |
209 | "PCI-DMA: Random memory would be DMAed\n"); | |
210 | } | |
1da177e4 | 211 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 212 | dump_leak(); |
1da177e4 | 213 | #endif |
05fccb0e | 214 | } |
1da177e4 | 215 | |
05fccb0e IM |
216 | static inline int |
217 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
218 | { | |
1da177e4 | 219 | u64 mask = *dev->dma_mask; |
00edefae | 220 | int high = addr + size > mask; |
1da177e4 | 221 | int mmu = high; |
05fccb0e IM |
222 | |
223 | if (force_iommu) | |
224 | mmu = 1; | |
225 | ||
226 | return mmu; | |
1da177e4 LT |
227 | } |
228 | ||
05fccb0e IM |
229 | static inline int |
230 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
231 | { | |
1da177e4 | 232 | u64 mask = *dev->dma_mask; |
00edefae | 233 | int high = addr + size > mask; |
1da177e4 | 234 | int mmu = high; |
05fccb0e IM |
235 | |
236 | return mmu; | |
1da177e4 LT |
237 | } |
238 | ||
239 | /* Map a single continuous physical area into the IOMMU. | |
240 | * Caller needs to check if the iommu is needed and flush. | |
241 | */ | |
17a941d8 MBY |
242 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
243 | size_t size, int dir) | |
05fccb0e | 244 | { |
1da177e4 | 245 | unsigned long npages = to_pages(phys_mem, size); |
fde9a109 | 246 | unsigned long iommu_page = alloc_iommu(dev, npages); |
1da177e4 | 247 | int i; |
05fccb0e | 248 | |
1da177e4 LT |
249 | if (iommu_page == -1) { |
250 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 251 | return phys_mem; |
1da177e4 LT |
252 | if (panic_on_overflow) |
253 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 254 | iommu_full(dev, size, dir); |
1da177e4 LT |
255 | return bad_dma_address; |
256 | } | |
257 | ||
258 | for (i = 0; i < npages; i++) { | |
259 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
260 | SET_LEAK(iommu_page + i); | |
261 | phys_mem += PAGE_SIZE; | |
262 | } | |
263 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
264 | } | |
265 | ||
05fccb0e | 266 | static dma_addr_t |
2be62149 | 267 | gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir) |
17a941d8 | 268 | { |
2be62149 | 269 | dma_addr_t map = dma_map_area(dev, paddr, size, dir); |
05fccb0e | 270 | |
a32073bf | 271 | flush_gart(); |
05fccb0e | 272 | |
17a941d8 MBY |
273 | return map; |
274 | } | |
275 | ||
1da177e4 | 276 | /* Map a single area into the IOMMU */ |
05fccb0e | 277 | static dma_addr_t |
2be62149 | 278 | gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir) |
1da177e4 | 279 | { |
2be62149 | 280 | unsigned long bus; |
1da177e4 | 281 | |
1da177e4 LT |
282 | if (!dev) |
283 | dev = &fallback_dev; | |
284 | ||
2be62149 IM |
285 | if (!need_iommu(dev, paddr, size)) |
286 | return paddr; | |
1da177e4 | 287 | |
2be62149 | 288 | bus = gart_map_simple(dev, paddr, size, dir); |
05fccb0e IM |
289 | |
290 | return bus; | |
17a941d8 MBY |
291 | } |
292 | ||
7c2d9cd2 JM |
293 | /* |
294 | * Free a DMA mapping. | |
295 | */ | |
1048fa52 | 296 | static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, |
05fccb0e | 297 | size_t size, int direction) |
7c2d9cd2 JM |
298 | { |
299 | unsigned long iommu_page; | |
300 | int npages; | |
301 | int i; | |
302 | ||
303 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
304 | dma_addr >= iommu_bus_base + iommu_size) | |
305 | return; | |
05fccb0e | 306 | |
7c2d9cd2 JM |
307 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
308 | npages = to_pages(dma_addr, size); | |
309 | for (i = 0; i < npages; i++) { | |
310 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
311 | CLEAR_LEAK(iommu_page + i); | |
312 | } | |
313 | free_iommu(iommu_page, npages); | |
314 | } | |
315 | ||
17a941d8 MBY |
316 | /* |
317 | * Wrapper for pci_unmap_single working with scatterlists. | |
318 | */ | |
05fccb0e IM |
319 | static void |
320 | gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
17a941d8 | 321 | { |
9ee1bea4 | 322 | struct scatterlist *s; |
17a941d8 MBY |
323 | int i; |
324 | ||
9ee1bea4 | 325 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 326 | if (!s->dma_length || !s->length) |
17a941d8 | 327 | break; |
7c2d9cd2 | 328 | gart_unmap_single(dev, s->dma_address, s->dma_length, dir); |
17a941d8 MBY |
329 | } |
330 | } | |
1da177e4 LT |
331 | |
332 | /* Fallback for dma_map_sg in case of overflow */ | |
333 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
334 | int nents, int dir) | |
335 | { | |
9ee1bea4 | 336 | struct scatterlist *s; |
1da177e4 LT |
337 | int i; |
338 | ||
339 | #ifdef CONFIG_IOMMU_DEBUG | |
340 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
341 | #endif | |
342 | ||
9ee1bea4 | 343 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 344 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
345 | |
346 | if (nonforced_iommu(dev, addr, s->length)) { | |
17a941d8 | 347 | addr = dma_map_area(dev, addr, s->length, dir); |
05fccb0e IM |
348 | if (addr == bad_dma_address) { |
349 | if (i > 0) | |
17a941d8 | 350 | gart_unmap_sg(dev, sg, i, dir); |
05fccb0e | 351 | nents = 0; |
1da177e4 LT |
352 | sg[0].dma_length = 0; |
353 | break; | |
354 | } | |
355 | } | |
356 | s->dma_address = addr; | |
357 | s->dma_length = s->length; | |
358 | } | |
a32073bf | 359 | flush_gart(); |
05fccb0e | 360 | |
1da177e4 LT |
361 | return nents; |
362 | } | |
363 | ||
364 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
365 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
366 | int nelems, struct scatterlist *sout, | |
367 | unsigned long pages) | |
1da177e4 | 368 | { |
fde9a109 | 369 | unsigned long iommu_start = alloc_iommu(dev, pages); |
05fccb0e | 370 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 371 | struct scatterlist *s; |
1da177e4 LT |
372 | int i; |
373 | ||
374 | if (iommu_start == -1) | |
375 | return -1; | |
9ee1bea4 JA |
376 | |
377 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
378 | unsigned long pages, addr; |
379 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 380 | |
9ee1bea4 JA |
381 | BUG_ON(s != start && s->offset); |
382 | if (s == start) { | |
1da177e4 LT |
383 | sout->dma_address = iommu_bus_base; |
384 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
385 | sout->dma_length = s->length; | |
05fccb0e IM |
386 | } else { |
387 | sout->dma_length += s->length; | |
1da177e4 LT |
388 | } |
389 | ||
390 | addr = phys_addr; | |
05fccb0e IM |
391 | pages = to_pages(s->offset, s->length); |
392 | while (pages--) { | |
393 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
394 | SET_LEAK(iommu_page); |
395 | addr += PAGE_SIZE; | |
396 | iommu_page++; | |
0d541064 | 397 | } |
05fccb0e IM |
398 | } |
399 | BUG_ON(iommu_page - iommu_start != pages); | |
400 | ||
1da177e4 LT |
401 | return 0; |
402 | } | |
403 | ||
05fccb0e | 404 | static inline int |
fde9a109 FT |
405 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
406 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 407 | { |
9ee1bea4 JA |
408 | if (!need) { |
409 | BUG_ON(nelems != 1); | |
e88a39de | 410 | sout->dma_address = start->dma_address; |
9ee1bea4 | 411 | sout->dma_length = start->length; |
1da177e4 | 412 | return 0; |
9ee1bea4 | 413 | } |
fde9a109 | 414 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 415 | } |
05fccb0e | 416 | |
1da177e4 LT |
417 | /* |
418 | * DMA map all entries in a scatterlist. | |
05fccb0e | 419 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 420 | */ |
05fccb0e IM |
421 | static int |
422 | gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
1da177e4 | 423 | { |
9ee1bea4 | 424 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
425 | int need = 0, nextneed, i, out, start; |
426 | unsigned long pages = 0; | |
42d00284 FT |
427 | unsigned int seg_size; |
428 | unsigned int max_seg_size; | |
1da177e4 | 429 | |
05fccb0e | 430 | if (nents == 0) |
1da177e4 LT |
431 | return 0; |
432 | ||
1da177e4 LT |
433 | if (!dev) |
434 | dev = &fallback_dev; | |
435 | ||
436 | out = 0; | |
437 | start = 0; | |
9ee1bea4 | 438 | start_sg = sgmap = sg; |
42d00284 FT |
439 | seg_size = 0; |
440 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
441 | ps = NULL; /* shut up gcc */ |
442 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 443 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 444 | |
1da177e4 | 445 | s->dma_address = addr; |
05fccb0e | 446 | BUG_ON(s->length == 0); |
1da177e4 | 447 | |
05fccb0e | 448 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
449 | |
450 | /* Handle the previous not yet processed entries */ | |
451 | if (i > start) { | |
05fccb0e IM |
452 | /* |
453 | * Can only merge when the last chunk ends on a | |
454 | * page boundary and the new one doesn't have an | |
455 | * offset. | |
456 | */ | |
1da177e4 | 457 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 458 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 459 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
460 | if (dma_map_cont(dev, start_sg, i - start, |
461 | sgmap, pages, need) < 0) | |
1da177e4 LT |
462 | goto error; |
463 | out++; | |
42d00284 | 464 | seg_size = 0; |
9ee1bea4 | 465 | sgmap = sg_next(sgmap); |
1da177e4 | 466 | pages = 0; |
9ee1bea4 JA |
467 | start = i; |
468 | start_sg = s; | |
1da177e4 LT |
469 | } |
470 | } | |
471 | ||
42d00284 | 472 | seg_size += s->length; |
1da177e4 LT |
473 | need = nextneed; |
474 | pages += to_pages(s->offset, s->length); | |
9ee1bea4 | 475 | ps = s; |
1da177e4 | 476 | } |
fde9a109 | 477 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
478 | goto error; |
479 | out++; | |
a32073bf | 480 | flush_gart(); |
9ee1bea4 JA |
481 | if (out < nents) { |
482 | sgmap = sg_next(sgmap); | |
483 | sgmap->dma_length = 0; | |
484 | } | |
1da177e4 LT |
485 | return out; |
486 | ||
487 | error: | |
a32073bf | 488 | flush_gart(); |
5336940d | 489 | gart_unmap_sg(dev, sg, out, dir); |
05fccb0e | 490 | |
a1002a48 KV |
491 | /* When it was forced or merged try again in a dumb way */ |
492 | if (force_iommu || iommu_merge) { | |
493 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
494 | if (out > 0) | |
495 | return out; | |
496 | } | |
1da177e4 LT |
497 | if (panic_on_overflow) |
498 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 499 | |
17a941d8 | 500 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
501 | for_each_sg(sg, s, nents, i) |
502 | s->dma_address = bad_dma_address; | |
1da177e4 | 503 | return 0; |
05fccb0e | 504 | } |
1da177e4 | 505 | |
17a941d8 | 506 | static int no_agp; |
1da177e4 LT |
507 | |
508 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
509 | { |
510 | unsigned long a; | |
511 | ||
512 | if (!iommu_size) { | |
513 | iommu_size = aper_size; | |
514 | if (!no_agp) | |
515 | iommu_size /= 2; | |
516 | } | |
517 | ||
518 | a = aper + iommu_size; | |
31422c51 | 519 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 520 | |
05fccb0e | 521 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 522 | printk(KERN_WARNING |
05fccb0e IM |
523 | "PCI-DMA: Warning: Small IOMMU %luMB." |
524 | " Consider increasing the AGP aperture in BIOS\n", | |
525 | iommu_size >> 20); | |
526 | } | |
527 | ||
1da177e4 | 528 | return iommu_size; |
05fccb0e | 529 | } |
1da177e4 | 530 | |
05fccb0e IM |
531 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
532 | { | |
533 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 534 | u64 aper_base; |
1da177e4 | 535 | |
05fccb0e | 536 | pci_read_config_dword(dev, 0x94, &aper_base_32); |
1da177e4 | 537 | pci_read_config_dword(dev, 0x90, &aper_order); |
05fccb0e | 538 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 539 | |
05fccb0e | 540 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
541 | aper_base <<= 25; |
542 | ||
05fccb0e IM |
543 | aper_size = (32 * 1024 * 1024) << aper_order; |
544 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
545 | aper_base = 0; |
546 | ||
547 | *size = aper_size; | |
548 | return aper_base; | |
05fccb0e | 549 | } |
1da177e4 | 550 | |
05fccb0e | 551 | /* |
1da177e4 | 552 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 553 | * AGP driver for some reason. |
1da177e4 LT |
554 | */ |
555 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
556 | { |
557 | unsigned aper_size, gatt_size, new_aper_size; | |
558 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
559 | struct pci_dev *dev; |
560 | void *gatt; | |
a32073bf AK |
561 | int i; |
562 | ||
1da177e4 LT |
563 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
564 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
565 | dev = NULL; |
566 | for (i = 0; i < num_k8_northbridges; i++) { | |
567 | dev = k8_northbridges[i]; | |
05fccb0e IM |
568 | new_aper_base = read_aperture(dev, &new_aper_size); |
569 | if (!new_aper_base) | |
570 | goto nommu; | |
571 | ||
572 | if (!aper_base) { | |
1da177e4 LT |
573 | aper_size = new_aper_size; |
574 | aper_base = new_aper_base; | |
05fccb0e IM |
575 | } |
576 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
577 | goto nommu; |
578 | } | |
579 | if (!aper_base) | |
05fccb0e | 580 | goto nommu; |
1da177e4 | 581 | info->aper_base = aper_base; |
05fccb0e | 582 | info->aper_size = aper_size >> 20; |
1da177e4 | 583 | |
05fccb0e IM |
584 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
585 | gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size)); | |
586 | if (!gatt) | |
cf6387da | 587 | panic("Cannot allocate GATT table"); |
6d238cc4 | 588 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 589 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 590 | |
05fccb0e | 591 | memset(gatt, 0, gatt_size); |
1da177e4 | 592 | agp_gatt_table = gatt; |
a32073bf AK |
593 | |
594 | for (i = 0; i < num_k8_northbridges; i++) { | |
05fccb0e IM |
595 | u32 gatt_reg; |
596 | u32 ctl; | |
1da177e4 | 597 | |
a32073bf | 598 | dev = k8_northbridges[i]; |
05fccb0e IM |
599 | gatt_reg = __pa(gatt) >> 12; |
600 | gatt_reg <<= 4; | |
1da177e4 | 601 | pci_write_config_dword(dev, 0x98, gatt_reg); |
05fccb0e | 602 | pci_read_config_dword(dev, 0x90, &ctl); |
1da177e4 LT |
603 | |
604 | ctl |= 1; | |
605 | ctl &= ~((1<<4) | (1<<5)); | |
606 | ||
05fccb0e | 607 | pci_write_config_dword(dev, 0x90, ctl); |
1da177e4 | 608 | } |
a32073bf | 609 | flush_gart(); |
05fccb0e IM |
610 | |
611 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
612 | aper_base, aper_size>>10); | |
1da177e4 LT |
613 | return 0; |
614 | ||
615 | nommu: | |
05fccb0e | 616 | /* Should not happen anymore */ |
8f59610d PM |
617 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
618 | KERN_WARNING "falling back to iommu=soft.\n"); | |
05fccb0e IM |
619 | return -1; |
620 | } | |
1da177e4 LT |
621 | |
622 | extern int agp_amd64_init(void); | |
623 | ||
e6584504 | 624 | static const struct dma_mapping_ops gart_dma_ops = { |
05fccb0e IM |
625 | .mapping_error = NULL, |
626 | .map_single = gart_map_single, | |
627 | .map_simple = gart_map_simple, | |
628 | .unmap_single = gart_unmap_single, | |
629 | .sync_single_for_cpu = NULL, | |
630 | .sync_single_for_device = NULL, | |
631 | .sync_single_range_for_cpu = NULL, | |
632 | .sync_single_range_for_device = NULL, | |
633 | .sync_sg_for_cpu = NULL, | |
634 | .sync_sg_for_device = NULL, | |
635 | .map_sg = gart_map_sg, | |
636 | .unmap_sg = gart_unmap_sg, | |
17a941d8 MBY |
637 | }; |
638 | ||
bc2cea6a YL |
639 | void gart_iommu_shutdown(void) |
640 | { | |
641 | struct pci_dev *dev; | |
642 | int i; | |
643 | ||
644 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
645 | return; | |
646 | ||
05fccb0e IM |
647 | for (i = 0; i < num_k8_northbridges; i++) { |
648 | u32 ctl; | |
bc2cea6a | 649 | |
05fccb0e IM |
650 | dev = k8_northbridges[i]; |
651 | pci_read_config_dword(dev, 0x90, &ctl); | |
bc2cea6a | 652 | |
05fccb0e | 653 | ctl &= ~1; |
bc2cea6a | 654 | |
05fccb0e IM |
655 | pci_write_config_dword(dev, 0x90, ctl); |
656 | } | |
bc2cea6a YL |
657 | } |
658 | ||
0dc243ae | 659 | void __init gart_iommu_init(void) |
05fccb0e | 660 | { |
1da177e4 | 661 | struct agp_kern_info info; |
1da177e4 | 662 | unsigned long iommu_start; |
05fccb0e | 663 | unsigned long aper_size; |
1da177e4 LT |
664 | unsigned long scratch; |
665 | long i; | |
666 | ||
a32073bf AK |
667 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) { |
668 | printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n"); | |
0dc243ae | 669 | return; |
a32073bf AK |
670 | } |
671 | ||
1da177e4 | 672 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 673 | no_agp = 1; |
1da177e4 LT |
674 | #else |
675 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
676 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
677 | no_agp = no_agp || |
678 | (agp_amd64_init() < 0) || | |
1da177e4 | 679 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 680 | #endif |
1da177e4 | 681 | |
60b08c67 | 682 | if (swiotlb) |
0dc243ae | 683 | return; |
60b08c67 | 684 | |
8d4f6b93 | 685 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 686 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 687 | return; |
8d4f6b93 | 688 | |
1da177e4 | 689 | if (no_iommu || |
17a941d8 | 690 | (!force_iommu && end_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 691 | !gart_iommu_aperture || |
1da177e4 | 692 | (no_agp && init_k8_gatt(&info) < 0)) { |
5b7b644c | 693 | if (end_pfn > MAX_DMA32_PFN) { |
8f59610d PM |
694 | printk(KERN_WARNING "More than 4GB of memory " |
695 | "but GART IOMMU not available.\n" | |
696 | KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 697 | } |
0dc243ae | 698 | return; |
1da177e4 LT |
699 | } |
700 | ||
5b7b644c | 701 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
702 | aper_size = info.aper_size * 1024 * 1024; |
703 | iommu_size = check_iommu_size(info.aper_base, aper_size); | |
704 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
705 | ||
706 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL, | |
707 | get_order(iommu_pages/8)); | |
708 | if (!iommu_gart_bitmap) | |
709 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
710 | memset(iommu_gart_bitmap, 0, iommu_pages/8); |
711 | ||
712 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e IM |
713 | if (leak_trace) { |
714 | iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL, | |
1da177e4 | 715 | get_order(iommu_pages*sizeof(void *))); |
05fccb0e IM |
716 | if (iommu_leak_tab) |
717 | memset(iommu_leak_tab, 0, iommu_pages * 8); | |
1da177e4 | 718 | else |
05fccb0e IM |
719 | printk(KERN_DEBUG |
720 | "PCI-DMA: Cannot allocate leak trace area\n"); | |
721 | } | |
1da177e4 LT |
722 | #endif |
723 | ||
05fccb0e | 724 | /* |
1da177e4 | 725 | * Out of IOMMU space handling. |
05fccb0e IM |
726 | * Reserve some invalid pages at the beginning of the GART. |
727 | */ | |
728 | set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES); | |
1da177e4 | 729 | |
05fccb0e | 730 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
731 | printk(KERN_INFO |
732 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 733 | iommu_size >> 20); |
1da177e4 | 734 | |
05fccb0e IM |
735 | iommu_start = aper_size - iommu_size; |
736 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
737 | bad_dma_address = iommu_bus_base; |
738 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
739 | ||
05fccb0e | 740 | /* |
1da177e4 LT |
741 | * Unmap the IOMMU part of the GART. The alias of the page is |
742 | * always mapped with cache enabled and there is no full cache | |
743 | * coherency across the GART remapping. The unmapping avoids | |
744 | * automatic prefetches from the CPU allocating cache lines in | |
745 | * there. All CPU accesses are done via the direct mapping to | |
746 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 747 | * devices. |
1da177e4 | 748 | */ |
28d6ee41 AK |
749 | set_memory_np((unsigned long)__va(iommu_bus_base), |
750 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
751 | /* |
752 | * Tricky. The GART table remaps the physical memory range, | |
753 | * so the CPU wont notice potential aliases and if the memory | |
754 | * is remapped to UC later on, we might surprise the PCI devices | |
755 | * with a stray writeout of a cacheline. So play it sure and | |
756 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
757 | * the pages as Not-Present: | |
758 | */ | |
759 | wbinvd(); | |
1da177e4 | 760 | |
05fccb0e IM |
761 | /* |
762 | * Try to workaround a bug (thanks to BenH) | |
763 | * Set unmapped entries to a scratch page instead of 0. | |
1da177e4 LT |
764 | * Any prefetches that hit unmapped entries won't get an bus abort |
765 | * then. | |
766 | */ | |
05fccb0e IM |
767 | scratch = get_zeroed_page(GFP_KERNEL); |
768 | if (!scratch) | |
1da177e4 LT |
769 | panic("Cannot allocate iommu scratch page"); |
770 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 771 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
772 | iommu_gatt_base[i] = gart_unmapped_entry; |
773 | ||
a32073bf | 774 | flush_gart(); |
17a941d8 | 775 | dma_ops = &gart_dma_ops; |
05fccb0e | 776 | } |
1da177e4 | 777 | |
43999d9e | 778 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
779 | { |
780 | int arg; | |
781 | ||
1da177e4 | 782 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 783 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
784 | leak_trace = 1; |
785 | p += 4; | |
786 | if (*p == '=') ++p; | |
787 | if (isdigit(*p) && get_option(&p, &arg)) | |
788 | iommu_leak_pages = arg; | |
789 | } | |
1da177e4 | 790 | #endif |
17a941d8 MBY |
791 | if (isdigit(*p) && get_option(&p, &arg)) |
792 | iommu_size = arg; | |
05fccb0e | 793 | if (!strncmp(p, "fullflush", 8)) |
17a941d8 | 794 | iommu_fullflush = 1; |
05fccb0e | 795 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 796 | iommu_fullflush = 0; |
05fccb0e | 797 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 798 | no_agp = 1; |
05fccb0e | 799 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
800 | fix_aperture = 0; |
801 | /* duplicated from pci-dma.c */ | |
05fccb0e | 802 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 803 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 804 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 805 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
806 | if (!strncmp(p, "memaper", 7)) { |
807 | fallback_aper_force = 1; | |
808 | p += 7; | |
809 | if (*p == '=') { | |
810 | ++p; | |
811 | if (get_option(&p, &arg)) | |
812 | fallback_aper_order = arg; | |
813 | } | |
814 | } | |
815 | } |