Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
162a688e | 12 | #include <linux/tick.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
b253149b | 27 | #include <asm/mwait.h> |
78f7f1e5 | 28 | #include <asm/fpu/internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 | 30 | #include <asm/nmi.h> |
375074cc | 31 | #include <asm/tlbflush.h> |
8838eb6c | 32 | #include <asm/mce.h> |
9fda6a06 | 33 | #include <asm/vm86.h> |
90e24014 | 34 | |
45046892 TG |
35 | /* |
36 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
37 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
38 | * so they are allowed to end up in the .data..cacheline_aligned | |
39 | * section. Since TSS's are completely CPU-local, we want them | |
40 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
41 | */ | |
d0a0de21 AL |
42 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
43 | .x86_tss = { | |
d9e05cc5 | 44 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
45 | #ifdef CONFIG_X86_32 |
46 | .ss0 = __KERNEL_DS, | |
47 | .ss1 = __KERNEL_CS, | |
48 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
49 | #endif | |
50 | }, | |
51 | #ifdef CONFIG_X86_32 | |
52 | /* | |
53 | * Note that the .io_bitmap member must be extra-big. This is because | |
54 | * the CPU will access an additional byte beyond the end of the IO | |
55 | * permission bitmap. The extra byte must be all 1 bits, and must | |
56 | * be within the limit. | |
57 | */ | |
58 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
59 | #endif | |
60 | }; | |
de71ad2c | 61 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 62 | |
90e24014 RW |
63 | #ifdef CONFIG_X86_64 |
64 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
65 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
66 | ||
67 | void idle_notifier_register(struct notifier_block *n) | |
68 | { | |
69 | atomic_notifier_chain_register(&idle_notifier, n); | |
70 | } | |
71 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
72 | ||
73 | void idle_notifier_unregister(struct notifier_block *n) | |
74 | { | |
75 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
76 | } | |
77 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
78 | #endif | |
c1e3b377 | 79 | |
55ccf3fe SS |
80 | /* |
81 | * this gets called so that we can store lazy state into memory and copy the | |
82 | * current task into the new thread. | |
83 | */ | |
61c4628b SS |
84 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
85 | { | |
5aaeb5c0 | 86 | memcpy(dst, src, arch_task_struct_size); |
f1853505 | 87 | |
c69e098b | 88 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 89 | } |
7f424a8b | 90 | |
389d1fb1 JF |
91 | /* |
92 | * Free current thread data structures etc.. | |
93 | */ | |
94 | void exit_thread(void) | |
95 | { | |
96 | struct task_struct *me = current; | |
97 | struct thread_struct *t = &me->thread; | |
250981e6 | 98 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 99 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 100 | |
250981e6 | 101 | if (bp) { |
24933b82 | 102 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 103 | |
389d1fb1 JF |
104 | t->io_bitmap_ptr = NULL; |
105 | clear_thread_flag(TIF_IO_BITMAP); | |
106 | /* | |
107 | * Careful, clear this in the TSS too: | |
108 | */ | |
109 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
110 | t->io_bitmap_max = 0; | |
111 | put_cpu(); | |
250981e6 | 112 | kfree(bp); |
389d1fb1 | 113 | } |
1dcc8d7b | 114 | |
9fda6a06 BG |
115 | free_vm86(t); |
116 | ||
50338615 | 117 | fpu__drop(fpu); |
389d1fb1 JF |
118 | } |
119 | ||
120 | void flush_thread(void) | |
121 | { | |
122 | struct task_struct *tsk = current; | |
123 | ||
24f1e32c | 124 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 125 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 126 | |
04c8e01d | 127 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
128 | } |
129 | ||
130 | static void hard_disable_TSC(void) | |
131 | { | |
375074cc | 132 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
133 | } |
134 | ||
135 | void disable_TSC(void) | |
136 | { | |
137 | preempt_disable(); | |
138 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
139 | /* | |
140 | * Must flip the CPU state synchronously with | |
141 | * TIF_NOTSC in the current running context. | |
142 | */ | |
143 | hard_disable_TSC(); | |
144 | preempt_enable(); | |
145 | } | |
146 | ||
147 | static void hard_enable_TSC(void) | |
148 | { | |
375074cc | 149 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
150 | } |
151 | ||
152 | static void enable_TSC(void) | |
153 | { | |
154 | preempt_disable(); | |
155 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
156 | /* | |
157 | * Must flip the CPU state synchronously with | |
158 | * TIF_NOTSC in the current running context. | |
159 | */ | |
160 | hard_enable_TSC(); | |
161 | preempt_enable(); | |
162 | } | |
163 | ||
164 | int get_tsc_mode(unsigned long adr) | |
165 | { | |
166 | unsigned int val; | |
167 | ||
168 | if (test_thread_flag(TIF_NOTSC)) | |
169 | val = PR_TSC_SIGSEGV; | |
170 | else | |
171 | val = PR_TSC_ENABLE; | |
172 | ||
173 | return put_user(val, (unsigned int __user *)adr); | |
174 | } | |
175 | ||
176 | int set_tsc_mode(unsigned int val) | |
177 | { | |
178 | if (val == PR_TSC_SIGSEGV) | |
179 | disable_TSC(); | |
180 | else if (val == PR_TSC_ENABLE) | |
181 | enable_TSC(); | |
182 | else | |
183 | return -EINVAL; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
189 | struct tss_struct *tss) | |
190 | { | |
191 | struct thread_struct *prev, *next; | |
192 | ||
193 | prev = &prev_p->thread; | |
194 | next = &next_p->thread; | |
195 | ||
ea8e61b7 PZ |
196 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
197 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
198 | unsigned long debugctl = get_debugctlmsr(); | |
199 | ||
200 | debugctl &= ~DEBUGCTLMSR_BTF; | |
201 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
202 | debugctl |= DEBUGCTLMSR_BTF; | |
203 | ||
204 | update_debugctlmsr(debugctl); | |
205 | } | |
389d1fb1 | 206 | |
389d1fb1 JF |
207 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
208 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
209 | /* prev and next are different */ | |
210 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
211 | hard_disable_TSC(); | |
212 | else | |
213 | hard_enable_TSC(); | |
214 | } | |
215 | ||
216 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
217 | /* | |
218 | * Copy the relevant range of the IO bitmap. | |
219 | * Normally this is 128 bytes or less: | |
220 | */ | |
221 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
222 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
223 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
224 | /* | |
225 | * Clear any possible leftover bits: | |
226 | */ | |
227 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
228 | } | |
7c68af6e | 229 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
230 | } |
231 | ||
00dba564 TG |
232 | /* |
233 | * Idle related variables and functions | |
234 | */ | |
d1896049 | 235 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
236 | EXPORT_SYMBOL(boot_option_idle_override); |
237 | ||
a476bda3 | 238 | static void (*x86_idle)(void); |
00dba564 | 239 | |
90e24014 RW |
240 | #ifndef CONFIG_SMP |
241 | static inline void play_dead(void) | |
242 | { | |
243 | BUG(); | |
244 | } | |
245 | #endif | |
246 | ||
247 | #ifdef CONFIG_X86_64 | |
248 | void enter_idle(void) | |
249 | { | |
c6ae41e7 | 250 | this_cpu_write(is_idle, 1); |
90e24014 RW |
251 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
252 | } | |
253 | ||
254 | static void __exit_idle(void) | |
255 | { | |
256 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
257 | return; | |
258 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
259 | } | |
260 | ||
261 | /* Called from interrupts to signify idle end */ | |
262 | void exit_idle(void) | |
263 | { | |
264 | /* idle loop has pid 0 */ | |
265 | if (current->pid) | |
266 | return; | |
267 | __exit_idle(); | |
268 | } | |
269 | #endif | |
270 | ||
7d1a9417 TG |
271 | void arch_cpu_idle_enter(void) |
272 | { | |
273 | local_touch_nmi(); | |
274 | enter_idle(); | |
275 | } | |
90e24014 | 276 | |
7d1a9417 TG |
277 | void arch_cpu_idle_exit(void) |
278 | { | |
279 | __exit_idle(); | |
280 | } | |
90e24014 | 281 | |
7d1a9417 TG |
282 | void arch_cpu_idle_dead(void) |
283 | { | |
284 | play_dead(); | |
285 | } | |
90e24014 | 286 | |
7d1a9417 TG |
287 | /* |
288 | * Called from the generic idle code. | |
289 | */ | |
290 | void arch_cpu_idle(void) | |
291 | { | |
16f8b05a | 292 | x86_idle(); |
90e24014 RW |
293 | } |
294 | ||
00dba564 | 295 | /* |
7d1a9417 | 296 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
297 | */ |
298 | void default_idle(void) | |
299 | { | |
4d0e42cc | 300 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 301 | safe_halt(); |
4d0e42cc | 302 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 303 | } |
60b8b1de | 304 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
305 | EXPORT_SYMBOL(default_idle); |
306 | #endif | |
307 | ||
6a377ddc LB |
308 | #ifdef CONFIG_XEN |
309 | bool xen_set_default_idle(void) | |
e5fd47bf | 310 | { |
a476bda3 | 311 | bool ret = !!x86_idle; |
e5fd47bf | 312 | |
a476bda3 | 313 | x86_idle = default_idle; |
e5fd47bf KRW |
314 | |
315 | return ret; | |
316 | } | |
6a377ddc | 317 | #endif |
d3ec5cae IV |
318 | void stop_this_cpu(void *dummy) |
319 | { | |
320 | local_irq_disable(); | |
321 | /* | |
322 | * Remove this CPU: | |
323 | */ | |
4f062896 | 324 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 325 | disable_local_APIC(); |
8838eb6c | 326 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 327 | |
27be4570 LB |
328 | for (;;) |
329 | halt(); | |
7f424a8b PZ |
330 | } |
331 | ||
02c68a02 LB |
332 | bool amd_e400_c1e_detected; |
333 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 334 | |
02c68a02 | 335 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 336 | |
02c68a02 | 337 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 338 | { |
02c68a02 LB |
339 | if (amd_e400_c1e_mask != NULL) |
340 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
341 | } |
342 | ||
aa276e1c | 343 | /* |
02c68a02 | 344 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
345 | * pending message MSR. If we detect C1E, then we handle it the same |
346 | * way as C3 power states (local apic timer and TSC stop) | |
347 | */ | |
02c68a02 | 348 | static void amd_e400_idle(void) |
aa276e1c | 349 | { |
02c68a02 | 350 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
351 | u32 lo, hi; |
352 | ||
353 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 354 | |
aa276e1c | 355 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 356 | amd_e400_c1e_detected = true; |
40fb1715 | 357 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 358 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 359 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
360 | } |
361 | } | |
362 | ||
02c68a02 | 363 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
364 | int cpu = smp_processor_id(); |
365 | ||
02c68a02 LB |
366 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
367 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
162a688e TG |
368 | /* Force broadcast so ACPI can not interfere. */ |
369 | tick_broadcast_force(); | |
c767a54b | 370 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c | 371 | } |
435c350e | 372 | tick_broadcast_enter(); |
0beefa20 | 373 | |
aa276e1c | 374 | default_idle(); |
0beefa20 TG |
375 | |
376 | /* | |
377 | * The switch back from broadcast mode needs to be | |
378 | * called with interrupts disabled. | |
379 | */ | |
ea811747 | 380 | local_irq_disable(); |
435c350e | 381 | tick_broadcast_exit(); |
ea811747 | 382 | local_irq_enable(); |
aa276e1c TG |
383 | } else |
384 | default_idle(); | |
385 | } | |
386 | ||
b253149b LB |
387 | /* |
388 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
389 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
390 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
391 | * | |
392 | * Some AMD machines are the opposite, they depend on using HALT. | |
393 | * | |
394 | * So for default C1, which is used during boot until cpuidle loads, | |
395 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
396 | */ | |
397 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
398 | { | |
399 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
400 | return 0; | |
401 | ||
402 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
403 | return 0; | |
404 | ||
405 | return 1; | |
406 | } | |
407 | ||
408 | /* | |
0fb0328d HR |
409 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
410 | * with interrupts enabled and no flags, which is backwards compatible with the | |
411 | * original MWAIT implementation. | |
b253149b | 412 | */ |
b253149b LB |
413 | static void mwait_idle(void) |
414 | { | |
f8e617f4 | 415 | if (!current_set_polling_and_test()) { |
e43d0189 | 416 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 MG |
417 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
418 | smp_mb(); /* quirk */ | |
b253149b | 419 | clflush((void *)¤t_thread_info()->flags); |
f8e617f4 MG |
420 | smp_mb(); /* quirk */ |
421 | } | |
b253149b LB |
422 | |
423 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
424 | if (!need_resched()) |
425 | __sti_mwait(0, 0); | |
426 | else | |
427 | local_irq_enable(); | |
e43d0189 | 428 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 429 | } else { |
b253149b | 430 | local_irq_enable(); |
f8e617f4 MG |
431 | } |
432 | __current_clr_polling(); | |
b253149b LB |
433 | } |
434 | ||
148f9bb8 | 435 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 436 | { |
3e5095d1 | 437 | #ifdef CONFIG_SMP |
7d1a9417 | 438 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 439 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 440 | #endif |
7d1a9417 | 441 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
442 | return; |
443 | ||
7d7dc116 | 444 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 445 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 446 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 447 | x86_idle = amd_e400_idle; |
b253149b LB |
448 | } else if (prefer_mwait_c1_over_halt(c)) { |
449 | pr_info("using mwait in idle threads\n"); | |
450 | x86_idle = mwait_idle; | |
6ddd2a27 | 451 | } else |
a476bda3 | 452 | x86_idle = default_idle; |
7f424a8b PZ |
453 | } |
454 | ||
02c68a02 | 455 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 456 | { |
02c68a02 | 457 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 458 | if (x86_idle == amd_e400_idle) |
02c68a02 | 459 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
460 | } |
461 | ||
7f424a8b PZ |
462 | static int __init idle_setup(char *str) |
463 | { | |
ab6bc3e3 CG |
464 | if (!str) |
465 | return -EINVAL; | |
466 | ||
7f424a8b | 467 | if (!strcmp(str, "poll")) { |
c767a54b | 468 | pr_info("using polling idle threads\n"); |
d1896049 | 469 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 470 | cpu_idle_poll_ctrl(true); |
d1896049 | 471 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
472 | /* |
473 | * When the boot option of idle=halt is added, halt is | |
474 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
475 | * won't be used again. | |
476 | * To continue to load the CPU idle driver, don't touch | |
477 | * the boot_option_idle_override. | |
478 | */ | |
a476bda3 | 479 | x86_idle = default_idle; |
d1896049 | 480 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
481 | } else if (!strcmp(str, "nomwait")) { |
482 | /* | |
483 | * If the boot option of "idle=nomwait" is added, | |
484 | * it means that mwait will be disabled for CPU C2/C3 | |
485 | * states. In such case it won't touch the variable | |
486 | * of boot_option_idle_override. | |
487 | */ | |
d1896049 | 488 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 489 | } else |
7f424a8b PZ |
490 | return -1; |
491 | ||
7f424a8b PZ |
492 | return 0; |
493 | } | |
494 | early_param("idle", idle_setup); | |
495 | ||
9d62dcdf AW |
496 | unsigned long arch_align_stack(unsigned long sp) |
497 | { | |
498 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
499 | sp -= get_random_int() % 8192; | |
500 | return sp & ~0xf; | |
501 | } | |
502 | ||
503 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
504 | { | |
505 | unsigned long range_end = mm->brk + 0x02000000; | |
506 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
507 | } | |
508 |