Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
27 | #include <asm/i387.h> | |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 RW |
30 | #include <asm/nmi.h> |
31 | ||
45046892 TG |
32 | /* |
33 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
34 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
35 | * so they are allowed to end up in the .data..cacheline_aligned | |
36 | * section. Since TSS's are completely CPU-local, we want them | |
37 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
38 | */ | |
277d5b40 | 39 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; |
45046892 | 40 | |
90e24014 RW |
41 | #ifdef CONFIG_X86_64 |
42 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
43 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
44 | ||
45 | void idle_notifier_register(struct notifier_block *n) | |
46 | { | |
47 | atomic_notifier_chain_register(&idle_notifier, n); | |
48 | } | |
49 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
50 | ||
51 | void idle_notifier_unregister(struct notifier_block *n) | |
52 | { | |
53 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
54 | } | |
55 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
56 | #endif | |
c1e3b377 | 57 | |
aa283f49 | 58 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 59 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 60 | |
55ccf3fe SS |
61 | /* |
62 | * this gets called so that we can store lazy state into memory and copy the | |
63 | * current task into the new thread. | |
64 | */ | |
61c4628b SS |
65 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
66 | { | |
67 | *dst = *src; | |
f1853505 | 68 | |
dc56c0f9 | 69 | dst->thread.fpu_counter = 0; |
5e23fee2 ON |
70 | dst->thread.fpu.has_fpu = 0; |
71 | dst->thread.fpu.last_cpu = ~0; | |
72 | dst->thread.fpu.state = NULL; | |
f1853505 ON |
73 | if (tsk_used_math(src)) { |
74 | int err = fpu_alloc(&dst->thread.fpu); | |
75 | if (err) | |
76 | return err; | |
304bceda | 77 | fpu_copy(dst, src); |
aa283f49 | 78 | } |
61c4628b SS |
79 | return 0; |
80 | } | |
81 | ||
aa283f49 | 82 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 83 | { |
86603283 | 84 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
85 | } |
86 | ||
38e7c572 | 87 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 88 | { |
38e7c572 | 89 | free_thread_xstate(tsk); |
61c4628b SS |
90 | } |
91 | ||
92 | void arch_task_cache_init(void) | |
93 | { | |
94 | task_xstate_cachep = | |
95 | kmem_cache_create("task_xstate", xstate_size, | |
96 | __alignof__(union thread_xstate), | |
2dff4405 | 97 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
7496d645 | 98 | setup_xstate_comp(); |
61c4628b | 99 | } |
7f424a8b | 100 | |
389d1fb1 JF |
101 | /* |
102 | * Free current thread data structures etc.. | |
103 | */ | |
104 | void exit_thread(void) | |
105 | { | |
106 | struct task_struct *me = current; | |
107 | struct thread_struct *t = &me->thread; | |
250981e6 | 108 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 109 | |
250981e6 | 110 | if (bp) { |
389d1fb1 JF |
111 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
112 | ||
389d1fb1 JF |
113 | t->io_bitmap_ptr = NULL; |
114 | clear_thread_flag(TIF_IO_BITMAP); | |
115 | /* | |
116 | * Careful, clear this in the TSS too: | |
117 | */ | |
118 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
119 | t->io_bitmap_max = 0; | |
120 | put_cpu(); | |
250981e6 | 121 | kfree(bp); |
389d1fb1 | 122 | } |
1dcc8d7b SS |
123 | |
124 | drop_fpu(me); | |
389d1fb1 JF |
125 | } |
126 | ||
127 | void flush_thread(void) | |
128 | { | |
129 | struct task_struct *tsk = current; | |
130 | ||
24f1e32c | 131 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 132 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
304bceda SS |
133 | drop_init_fpu(tsk); |
134 | /* | |
135 | * Free the FPU state for non xsave platforms. They get reallocated | |
136 | * lazily at the first use. | |
137 | */ | |
5d2bd700 | 138 | if (!use_eager_fpu()) |
304bceda | 139 | free_thread_xstate(tsk); |
389d1fb1 JF |
140 | } |
141 | ||
142 | static void hard_disable_TSC(void) | |
143 | { | |
144 | write_cr4(read_cr4() | X86_CR4_TSD); | |
145 | } | |
146 | ||
147 | void disable_TSC(void) | |
148 | { | |
149 | preempt_disable(); | |
150 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
151 | /* | |
152 | * Must flip the CPU state synchronously with | |
153 | * TIF_NOTSC in the current running context. | |
154 | */ | |
155 | hard_disable_TSC(); | |
156 | preempt_enable(); | |
157 | } | |
158 | ||
159 | static void hard_enable_TSC(void) | |
160 | { | |
161 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
162 | } | |
163 | ||
164 | static void enable_TSC(void) | |
165 | { | |
166 | preempt_disable(); | |
167 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
168 | /* | |
169 | * Must flip the CPU state synchronously with | |
170 | * TIF_NOTSC in the current running context. | |
171 | */ | |
172 | hard_enable_TSC(); | |
173 | preempt_enable(); | |
174 | } | |
175 | ||
176 | int get_tsc_mode(unsigned long adr) | |
177 | { | |
178 | unsigned int val; | |
179 | ||
180 | if (test_thread_flag(TIF_NOTSC)) | |
181 | val = PR_TSC_SIGSEGV; | |
182 | else | |
183 | val = PR_TSC_ENABLE; | |
184 | ||
185 | return put_user(val, (unsigned int __user *)adr); | |
186 | } | |
187 | ||
188 | int set_tsc_mode(unsigned int val) | |
189 | { | |
190 | if (val == PR_TSC_SIGSEGV) | |
191 | disable_TSC(); | |
192 | else if (val == PR_TSC_ENABLE) | |
193 | enable_TSC(); | |
194 | else | |
195 | return -EINVAL; | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
201 | struct tss_struct *tss) | |
202 | { | |
203 | struct thread_struct *prev, *next; | |
204 | ||
205 | prev = &prev_p->thread; | |
206 | next = &next_p->thread; | |
207 | ||
ea8e61b7 PZ |
208 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
209 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
210 | unsigned long debugctl = get_debugctlmsr(); | |
211 | ||
212 | debugctl &= ~DEBUGCTLMSR_BTF; | |
213 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
214 | debugctl |= DEBUGCTLMSR_BTF; | |
215 | ||
216 | update_debugctlmsr(debugctl); | |
217 | } | |
389d1fb1 | 218 | |
389d1fb1 JF |
219 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
220 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
221 | /* prev and next are different */ | |
222 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
223 | hard_disable_TSC(); | |
224 | else | |
225 | hard_enable_TSC(); | |
226 | } | |
227 | ||
228 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
229 | /* | |
230 | * Copy the relevant range of the IO bitmap. | |
231 | * Normally this is 128 bytes or less: | |
232 | */ | |
233 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
234 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
235 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
236 | /* | |
237 | * Clear any possible leftover bits: | |
238 | */ | |
239 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
240 | } | |
7c68af6e | 241 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
242 | } |
243 | ||
00dba564 TG |
244 | /* |
245 | * Idle related variables and functions | |
246 | */ | |
d1896049 | 247 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
248 | EXPORT_SYMBOL(boot_option_idle_override); |
249 | ||
a476bda3 | 250 | static void (*x86_idle)(void); |
00dba564 | 251 | |
90e24014 RW |
252 | #ifndef CONFIG_SMP |
253 | static inline void play_dead(void) | |
254 | { | |
255 | BUG(); | |
256 | } | |
257 | #endif | |
258 | ||
259 | #ifdef CONFIG_X86_64 | |
260 | void enter_idle(void) | |
261 | { | |
c6ae41e7 | 262 | this_cpu_write(is_idle, 1); |
90e24014 RW |
263 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
264 | } | |
265 | ||
266 | static void __exit_idle(void) | |
267 | { | |
268 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
269 | return; | |
270 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
271 | } | |
272 | ||
273 | /* Called from interrupts to signify idle end */ | |
274 | void exit_idle(void) | |
275 | { | |
276 | /* idle loop has pid 0 */ | |
277 | if (current->pid) | |
278 | return; | |
279 | __exit_idle(); | |
280 | } | |
281 | #endif | |
282 | ||
7d1a9417 TG |
283 | void arch_cpu_idle_enter(void) |
284 | { | |
285 | local_touch_nmi(); | |
286 | enter_idle(); | |
287 | } | |
90e24014 | 288 | |
7d1a9417 TG |
289 | void arch_cpu_idle_exit(void) |
290 | { | |
291 | __exit_idle(); | |
292 | } | |
90e24014 | 293 | |
7d1a9417 TG |
294 | void arch_cpu_idle_dead(void) |
295 | { | |
296 | play_dead(); | |
297 | } | |
90e24014 | 298 | |
7d1a9417 TG |
299 | /* |
300 | * Called from the generic idle code. | |
301 | */ | |
302 | void arch_cpu_idle(void) | |
303 | { | |
16f8b05a | 304 | x86_idle(); |
90e24014 RW |
305 | } |
306 | ||
00dba564 | 307 | /* |
7d1a9417 | 308 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
309 | */ |
310 | void default_idle(void) | |
311 | { | |
4d0e42cc | 312 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 313 | safe_halt(); |
4d0e42cc | 314 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 315 | } |
60b8b1de | 316 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
317 | EXPORT_SYMBOL(default_idle); |
318 | #endif | |
319 | ||
6a377ddc LB |
320 | #ifdef CONFIG_XEN |
321 | bool xen_set_default_idle(void) | |
e5fd47bf | 322 | { |
a476bda3 | 323 | bool ret = !!x86_idle; |
e5fd47bf | 324 | |
a476bda3 | 325 | x86_idle = default_idle; |
e5fd47bf KRW |
326 | |
327 | return ret; | |
328 | } | |
6a377ddc | 329 | #endif |
d3ec5cae IV |
330 | void stop_this_cpu(void *dummy) |
331 | { | |
332 | local_irq_disable(); | |
333 | /* | |
334 | * Remove this CPU: | |
335 | */ | |
4f062896 | 336 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
337 | disable_local_APIC(); |
338 | ||
27be4570 LB |
339 | for (;;) |
340 | halt(); | |
7f424a8b PZ |
341 | } |
342 | ||
02c68a02 LB |
343 | bool amd_e400_c1e_detected; |
344 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 345 | |
02c68a02 | 346 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 347 | |
02c68a02 | 348 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 349 | { |
02c68a02 LB |
350 | if (amd_e400_c1e_mask != NULL) |
351 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
352 | } |
353 | ||
aa276e1c | 354 | /* |
02c68a02 | 355 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
356 | * pending message MSR. If we detect C1E, then we handle it the same |
357 | * way as C3 power states (local apic timer and TSC stop) | |
358 | */ | |
02c68a02 | 359 | static void amd_e400_idle(void) |
aa276e1c | 360 | { |
02c68a02 | 361 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
362 | u32 lo, hi; |
363 | ||
364 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 365 | |
aa276e1c | 366 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 367 | amd_e400_c1e_detected = true; |
40fb1715 | 368 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 369 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 370 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
371 | } |
372 | } | |
373 | ||
02c68a02 | 374 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
375 | int cpu = smp_processor_id(); |
376 | ||
02c68a02 LB |
377 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
378 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 379 | /* |
f833bab8 | 380 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 381 | */ |
aa276e1c TG |
382 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
383 | &cpu); | |
c767a54b | 384 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
385 | } |
386 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 387 | |
aa276e1c | 388 | default_idle(); |
0beefa20 TG |
389 | |
390 | /* | |
391 | * The switch back from broadcast mode needs to be | |
392 | * called with interrupts disabled. | |
393 | */ | |
ea811747 PZ |
394 | local_irq_disable(); |
395 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
396 | local_irq_enable(); | |
aa276e1c TG |
397 | } else |
398 | default_idle(); | |
399 | } | |
400 | ||
148f9bb8 | 401 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 402 | { |
3e5095d1 | 403 | #ifdef CONFIG_SMP |
7d1a9417 | 404 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 405 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 406 | #endif |
7d1a9417 | 407 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
408 | return; |
409 | ||
7d7dc116 | 410 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 411 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 412 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 413 | x86_idle = amd_e400_idle; |
6ddd2a27 | 414 | } else |
a476bda3 | 415 | x86_idle = default_idle; |
7f424a8b PZ |
416 | } |
417 | ||
02c68a02 | 418 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 419 | { |
02c68a02 | 420 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 421 | if (x86_idle == amd_e400_idle) |
02c68a02 | 422 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
423 | } |
424 | ||
7f424a8b PZ |
425 | static int __init idle_setup(char *str) |
426 | { | |
ab6bc3e3 CG |
427 | if (!str) |
428 | return -EINVAL; | |
429 | ||
7f424a8b | 430 | if (!strcmp(str, "poll")) { |
c767a54b | 431 | pr_info("using polling idle threads\n"); |
d1896049 | 432 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 433 | cpu_idle_poll_ctrl(true); |
d1896049 | 434 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
435 | /* |
436 | * When the boot option of idle=halt is added, halt is | |
437 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
438 | * won't be used again. | |
439 | * To continue to load the CPU idle driver, don't touch | |
440 | * the boot_option_idle_override. | |
441 | */ | |
a476bda3 | 442 | x86_idle = default_idle; |
d1896049 | 443 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
444 | } else if (!strcmp(str, "nomwait")) { |
445 | /* | |
446 | * If the boot option of "idle=nomwait" is added, | |
447 | * it means that mwait will be disabled for CPU C2/C3 | |
448 | * states. In such case it won't touch the variable | |
449 | * of boot_option_idle_override. | |
450 | */ | |
d1896049 | 451 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 452 | } else |
7f424a8b PZ |
453 | return -1; |
454 | ||
7f424a8b PZ |
455 | return 0; |
456 | } | |
457 | early_param("idle", idle_setup); | |
458 | ||
9d62dcdf AW |
459 | unsigned long arch_align_stack(unsigned long sp) |
460 | { | |
461 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
462 | sp -= get_random_int() % 8192; | |
463 | return sp & ~0xf; | |
464 | } | |
465 | ||
466 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
467 | { | |
468 | unsigned long range_end = mm->brk + 0x02000000; | |
469 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
470 | } | |
471 |