Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
162a688e | 12 | #include <linux/tick.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
b253149b | 27 | #include <asm/mwait.h> |
78f7f1e5 | 28 | #include <asm/fpu/internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 | 30 | #include <asm/nmi.h> |
375074cc | 31 | #include <asm/tlbflush.h> |
8838eb6c | 32 | #include <asm/mce.h> |
9fda6a06 | 33 | #include <asm/vm86.h> |
90e24014 | 34 | |
45046892 TG |
35 | /* |
36 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
37 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
38 | * so they are allowed to end up in the .data..cacheline_aligned | |
39 | * section. Since TSS's are completely CPU-local, we want them | |
40 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
41 | */ | |
d0a0de21 AL |
42 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
43 | .x86_tss = { | |
d9e05cc5 | 44 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
45 | #ifdef CONFIG_X86_32 |
46 | .ss0 = __KERNEL_DS, | |
47 | .ss1 = __KERNEL_CS, | |
48 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
49 | #endif | |
50 | }, | |
51 | #ifdef CONFIG_X86_32 | |
52 | /* | |
53 | * Note that the .io_bitmap member must be extra-big. This is because | |
54 | * the CPU will access an additional byte beyond the end of the IO | |
55 | * permission bitmap. The extra byte must be all 1 bits, and must | |
56 | * be within the limit. | |
57 | */ | |
58 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
59 | #endif | |
2a41aa4f AL |
60 | #ifdef CONFIG_X86_32 |
61 | .SYSENTER_stack_canary = STACK_END_MAGIC, | |
62 | #endif | |
d0a0de21 | 63 | }; |
de71ad2c | 64 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 65 | |
90e24014 RW |
66 | #ifdef CONFIG_X86_64 |
67 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
68 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
69 | ||
70 | void idle_notifier_register(struct notifier_block *n) | |
71 | { | |
72 | atomic_notifier_chain_register(&idle_notifier, n); | |
73 | } | |
74 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
75 | ||
76 | void idle_notifier_unregister(struct notifier_block *n) | |
77 | { | |
78 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
79 | } | |
80 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
81 | #endif | |
c1e3b377 | 82 | |
55ccf3fe SS |
83 | /* |
84 | * this gets called so that we can store lazy state into memory and copy the | |
85 | * current task into the new thread. | |
86 | */ | |
61c4628b SS |
87 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
88 | { | |
5aaeb5c0 | 89 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
90 | #ifdef CONFIG_VM86 |
91 | dst->thread.vm86 = NULL; | |
92 | #endif | |
f1853505 | 93 | |
c69e098b | 94 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 95 | } |
7f424a8b | 96 | |
389d1fb1 JF |
97 | /* |
98 | * Free current thread data structures etc.. | |
99 | */ | |
e6464694 | 100 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 101 | { |
e6464694 | 102 | struct thread_struct *t = &tsk->thread; |
250981e6 | 103 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 104 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 105 | |
250981e6 | 106 | if (bp) { |
24933b82 | 107 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 108 | |
389d1fb1 JF |
109 | t->io_bitmap_ptr = NULL; |
110 | clear_thread_flag(TIF_IO_BITMAP); | |
111 | /* | |
112 | * Careful, clear this in the TSS too: | |
113 | */ | |
114 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
115 | t->io_bitmap_max = 0; | |
116 | put_cpu(); | |
250981e6 | 117 | kfree(bp); |
389d1fb1 | 118 | } |
1dcc8d7b | 119 | |
9fda6a06 BG |
120 | free_vm86(t); |
121 | ||
50338615 | 122 | fpu__drop(fpu); |
389d1fb1 JF |
123 | } |
124 | ||
125 | void flush_thread(void) | |
126 | { | |
127 | struct task_struct *tsk = current; | |
128 | ||
24f1e32c | 129 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 130 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 131 | |
04c8e01d | 132 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
133 | } |
134 | ||
135 | static void hard_disable_TSC(void) | |
136 | { | |
375074cc | 137 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
138 | } |
139 | ||
140 | void disable_TSC(void) | |
141 | { | |
142 | preempt_disable(); | |
143 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
144 | /* | |
145 | * Must flip the CPU state synchronously with | |
146 | * TIF_NOTSC in the current running context. | |
147 | */ | |
148 | hard_disable_TSC(); | |
149 | preempt_enable(); | |
150 | } | |
151 | ||
152 | static void hard_enable_TSC(void) | |
153 | { | |
375074cc | 154 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
155 | } |
156 | ||
157 | static void enable_TSC(void) | |
158 | { | |
159 | preempt_disable(); | |
160 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
161 | /* | |
162 | * Must flip the CPU state synchronously with | |
163 | * TIF_NOTSC in the current running context. | |
164 | */ | |
165 | hard_enable_TSC(); | |
166 | preempt_enable(); | |
167 | } | |
168 | ||
169 | int get_tsc_mode(unsigned long adr) | |
170 | { | |
171 | unsigned int val; | |
172 | ||
173 | if (test_thread_flag(TIF_NOTSC)) | |
174 | val = PR_TSC_SIGSEGV; | |
175 | else | |
176 | val = PR_TSC_ENABLE; | |
177 | ||
178 | return put_user(val, (unsigned int __user *)adr); | |
179 | } | |
180 | ||
181 | int set_tsc_mode(unsigned int val) | |
182 | { | |
183 | if (val == PR_TSC_SIGSEGV) | |
184 | disable_TSC(); | |
185 | else if (val == PR_TSC_ENABLE) | |
186 | enable_TSC(); | |
187 | else | |
188 | return -EINVAL; | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
194 | struct tss_struct *tss) | |
195 | { | |
196 | struct thread_struct *prev, *next; | |
197 | ||
198 | prev = &prev_p->thread; | |
199 | next = &next_p->thread; | |
200 | ||
ea8e61b7 PZ |
201 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
202 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
203 | unsigned long debugctl = get_debugctlmsr(); | |
204 | ||
205 | debugctl &= ~DEBUGCTLMSR_BTF; | |
206 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
207 | debugctl |= DEBUGCTLMSR_BTF; | |
208 | ||
209 | update_debugctlmsr(debugctl); | |
210 | } | |
389d1fb1 | 211 | |
389d1fb1 JF |
212 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
213 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
214 | /* prev and next are different */ | |
215 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
216 | hard_disable_TSC(); | |
217 | else | |
218 | hard_enable_TSC(); | |
219 | } | |
220 | ||
221 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
222 | /* | |
223 | * Copy the relevant range of the IO bitmap. | |
224 | * Normally this is 128 bytes or less: | |
225 | */ | |
226 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
227 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
228 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
229 | /* | |
230 | * Clear any possible leftover bits: | |
231 | */ | |
232 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
233 | } | |
7c68af6e | 234 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
235 | } |
236 | ||
00dba564 TG |
237 | /* |
238 | * Idle related variables and functions | |
239 | */ | |
d1896049 | 240 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
241 | EXPORT_SYMBOL(boot_option_idle_override); |
242 | ||
a476bda3 | 243 | static void (*x86_idle)(void); |
00dba564 | 244 | |
90e24014 RW |
245 | #ifndef CONFIG_SMP |
246 | static inline void play_dead(void) | |
247 | { | |
248 | BUG(); | |
249 | } | |
250 | #endif | |
251 | ||
252 | #ifdef CONFIG_X86_64 | |
253 | void enter_idle(void) | |
254 | { | |
c6ae41e7 | 255 | this_cpu_write(is_idle, 1); |
90e24014 RW |
256 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
257 | } | |
258 | ||
259 | static void __exit_idle(void) | |
260 | { | |
261 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
262 | return; | |
263 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
264 | } | |
265 | ||
266 | /* Called from interrupts to signify idle end */ | |
267 | void exit_idle(void) | |
268 | { | |
269 | /* idle loop has pid 0 */ | |
270 | if (current->pid) | |
271 | return; | |
272 | __exit_idle(); | |
273 | } | |
274 | #endif | |
275 | ||
7d1a9417 TG |
276 | void arch_cpu_idle_enter(void) |
277 | { | |
278 | local_touch_nmi(); | |
279 | enter_idle(); | |
280 | } | |
90e24014 | 281 | |
7d1a9417 TG |
282 | void arch_cpu_idle_exit(void) |
283 | { | |
284 | __exit_idle(); | |
285 | } | |
90e24014 | 286 | |
7d1a9417 TG |
287 | void arch_cpu_idle_dead(void) |
288 | { | |
289 | play_dead(); | |
290 | } | |
90e24014 | 291 | |
7d1a9417 TG |
292 | /* |
293 | * Called from the generic idle code. | |
294 | */ | |
295 | void arch_cpu_idle(void) | |
296 | { | |
16f8b05a | 297 | x86_idle(); |
90e24014 RW |
298 | } |
299 | ||
00dba564 | 300 | /* |
7d1a9417 | 301 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
302 | */ |
303 | void default_idle(void) | |
304 | { | |
4d0e42cc | 305 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 306 | safe_halt(); |
4d0e42cc | 307 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 308 | } |
60b8b1de | 309 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
310 | EXPORT_SYMBOL(default_idle); |
311 | #endif | |
312 | ||
6a377ddc LB |
313 | #ifdef CONFIG_XEN |
314 | bool xen_set_default_idle(void) | |
e5fd47bf | 315 | { |
a476bda3 | 316 | bool ret = !!x86_idle; |
e5fd47bf | 317 | |
a476bda3 | 318 | x86_idle = default_idle; |
e5fd47bf KRW |
319 | |
320 | return ret; | |
321 | } | |
6a377ddc | 322 | #endif |
d3ec5cae IV |
323 | void stop_this_cpu(void *dummy) |
324 | { | |
325 | local_irq_disable(); | |
326 | /* | |
327 | * Remove this CPU: | |
328 | */ | |
4f062896 | 329 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 330 | disable_local_APIC(); |
8838eb6c | 331 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 332 | |
27be4570 LB |
333 | for (;;) |
334 | halt(); | |
7f424a8b PZ |
335 | } |
336 | ||
02c68a02 LB |
337 | bool amd_e400_c1e_detected; |
338 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 339 | |
02c68a02 | 340 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 341 | |
02c68a02 | 342 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 343 | { |
02c68a02 LB |
344 | if (amd_e400_c1e_mask != NULL) |
345 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
346 | } |
347 | ||
aa276e1c | 348 | /* |
02c68a02 | 349 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
350 | * pending message MSR. If we detect C1E, then we handle it the same |
351 | * way as C3 power states (local apic timer and TSC stop) | |
352 | */ | |
02c68a02 | 353 | static void amd_e400_idle(void) |
aa276e1c | 354 | { |
02c68a02 | 355 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
356 | u32 lo, hi; |
357 | ||
358 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 359 | |
aa276e1c | 360 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 361 | amd_e400_c1e_detected = true; |
40fb1715 | 362 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 363 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 364 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
365 | } |
366 | } | |
367 | ||
02c68a02 | 368 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
369 | int cpu = smp_processor_id(); |
370 | ||
02c68a02 LB |
371 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
372 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
162a688e TG |
373 | /* Force broadcast so ACPI can not interfere. */ |
374 | tick_broadcast_force(); | |
c767a54b | 375 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c | 376 | } |
435c350e | 377 | tick_broadcast_enter(); |
0beefa20 | 378 | |
aa276e1c | 379 | default_idle(); |
0beefa20 TG |
380 | |
381 | /* | |
382 | * The switch back from broadcast mode needs to be | |
383 | * called with interrupts disabled. | |
384 | */ | |
ea811747 | 385 | local_irq_disable(); |
435c350e | 386 | tick_broadcast_exit(); |
ea811747 | 387 | local_irq_enable(); |
aa276e1c TG |
388 | } else |
389 | default_idle(); | |
390 | } | |
391 | ||
b253149b LB |
392 | /* |
393 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
394 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
395 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
396 | * | |
397 | * Some AMD machines are the opposite, they depend on using HALT. | |
398 | * | |
399 | * So for default C1, which is used during boot until cpuidle loads, | |
400 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
401 | */ | |
402 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
403 | { | |
404 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
405 | return 0; | |
406 | ||
407 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
408 | return 0; | |
409 | ||
410 | return 1; | |
411 | } | |
412 | ||
413 | /* | |
0fb0328d HR |
414 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
415 | * with interrupts enabled and no flags, which is backwards compatible with the | |
416 | * original MWAIT implementation. | |
b253149b | 417 | */ |
b253149b LB |
418 | static void mwait_idle(void) |
419 | { | |
f8e617f4 | 420 | if (!current_set_polling_and_test()) { |
e43d0189 | 421 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 422 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 423 | mb(); /* quirk */ |
b253149b | 424 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 425 | mb(); /* quirk */ |
f8e617f4 | 426 | } |
b253149b LB |
427 | |
428 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
429 | if (!need_resched()) |
430 | __sti_mwait(0, 0); | |
431 | else | |
432 | local_irq_enable(); | |
e43d0189 | 433 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 434 | } else { |
b253149b | 435 | local_irq_enable(); |
f8e617f4 MG |
436 | } |
437 | __current_clr_polling(); | |
b253149b LB |
438 | } |
439 | ||
148f9bb8 | 440 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 441 | { |
3e5095d1 | 442 | #ifdef CONFIG_SMP |
7d1a9417 | 443 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 444 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 445 | #endif |
7d1a9417 | 446 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
447 | return; |
448 | ||
7d7dc116 | 449 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 450 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 451 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 452 | x86_idle = amd_e400_idle; |
b253149b LB |
453 | } else if (prefer_mwait_c1_over_halt(c)) { |
454 | pr_info("using mwait in idle threads\n"); | |
455 | x86_idle = mwait_idle; | |
6ddd2a27 | 456 | } else |
a476bda3 | 457 | x86_idle = default_idle; |
7f424a8b PZ |
458 | } |
459 | ||
02c68a02 | 460 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 461 | { |
02c68a02 | 462 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 463 | if (x86_idle == amd_e400_idle) |
02c68a02 | 464 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
465 | } |
466 | ||
7f424a8b PZ |
467 | static int __init idle_setup(char *str) |
468 | { | |
ab6bc3e3 CG |
469 | if (!str) |
470 | return -EINVAL; | |
471 | ||
7f424a8b | 472 | if (!strcmp(str, "poll")) { |
c767a54b | 473 | pr_info("using polling idle threads\n"); |
d1896049 | 474 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 475 | cpu_idle_poll_ctrl(true); |
d1896049 | 476 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
477 | /* |
478 | * When the boot option of idle=halt is added, halt is | |
479 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
480 | * won't be used again. | |
481 | * To continue to load the CPU idle driver, don't touch | |
482 | * the boot_option_idle_override. | |
483 | */ | |
a476bda3 | 484 | x86_idle = default_idle; |
d1896049 | 485 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
486 | } else if (!strcmp(str, "nomwait")) { |
487 | /* | |
488 | * If the boot option of "idle=nomwait" is added, | |
489 | * it means that mwait will be disabled for CPU C2/C3 | |
490 | * states. In such case it won't touch the variable | |
491 | * of boot_option_idle_override. | |
492 | */ | |
d1896049 | 493 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 494 | } else |
7f424a8b PZ |
495 | return -1; |
496 | ||
7f424a8b PZ |
497 | return 0; |
498 | } | |
499 | early_param("idle", idle_setup); | |
500 | ||
9d62dcdf AW |
501 | unsigned long arch_align_stack(unsigned long sp) |
502 | { | |
503 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
504 | sp -= get_random_int() % 8192; | |
505 | return sp & ~0xf; | |
506 | } | |
507 | ||
508 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
509 | { | |
510 | unsigned long range_end = mm->brk + 0x02000000; | |
511 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
512 | } | |
513 | ||
7ba78053 TG |
514 | /* |
515 | * Called from fs/proc with a reference on @p to find the function | |
516 | * which called into schedule(). This needs to be done carefully | |
517 | * because the task might wake up and we might look at a stack | |
518 | * changing under us. | |
519 | */ | |
520 | unsigned long get_wchan(struct task_struct *p) | |
521 | { | |
522 | unsigned long start, bottom, top, sp, fp, ip; | |
523 | int count = 0; | |
524 | ||
525 | if (!p || p == current || p->state == TASK_RUNNING) | |
526 | return 0; | |
527 | ||
528 | start = (unsigned long)task_stack_page(p); | |
529 | if (!start) | |
530 | return 0; | |
531 | ||
532 | /* | |
533 | * Layout of the stack page: | |
534 | * | |
535 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
536 | * PADDING | |
537 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
538 | * stack | |
539 | * ----------- bottom = start + sizeof(thread_info) | |
540 | * thread_info | |
541 | * ----------- start | |
542 | * | |
543 | * The tasks stack pointer points at the location where the | |
544 | * framepointer is stored. The data on the stack is: | |
545 | * ... IP FP ... IP FP | |
546 | * | |
547 | * We need to read FP and IP, so we need to adjust the upper | |
548 | * bound by another unsigned long. | |
549 | */ | |
550 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
551 | top -= 2 * sizeof(unsigned long); | |
552 | bottom = start + sizeof(struct thread_info); | |
553 | ||
554 | sp = READ_ONCE(p->thread.sp); | |
555 | if (sp < bottom || sp > top) | |
556 | return 0; | |
557 | ||
f7d27c35 | 558 | fp = READ_ONCE_NOCHECK(*(unsigned long *)sp); |
7ba78053 TG |
559 | do { |
560 | if (fp < bottom || fp > top) | |
561 | return 0; | |
f7d27c35 | 562 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
7ba78053 TG |
563 | if (!in_sched_functions(ip)) |
564 | return ip; | |
f7d27c35 | 565 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 TG |
566 | } while (count++ < 16 && p->state != TASK_RUNNING); |
567 | return 0; | |
568 | } |