[deliverable/linux.git] / arch / x86 / kernel / quirks.c

/*
 * This file contains work-arounds for x86 and x86_64 platform bugs.
 */
#include <linux/pci.h>
#include <linux/irq.h>

#include <asm/hpet.h>

#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)

static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
{
	u8 config, rev;
	u16 word;

	/* BIOS may enable hardware IRQ balancing for
	 * E7520/E7320/E7525(revision ID 0x9 and below)
	 * based platforms.
	 * Disable SW irqbalance/affinity on those platforms.
	 */
	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
	if (rev > 0x9)
		return;

	/* enable access to config space*/
	pci_read_config_byte(dev, 0xf4, &config);
	pci_write_config_byte(dev, 0xf4, config|0x2);

	/*
	 * read xTPR register.  We may not have a pci_dev for device 8
	 * because it might be hidden until the above write.
	 */
	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);

	if (!(word & (1 << 13))) {
		dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
			"disabling irq balancing and affinity\n");
		noirqdebug_setup("");
#ifdef CONFIG_PROC_FS
		no_irq_affinity = 1;
#endif
	}

	/* put back the original value for config space*/
	if (!(config & 0x2))
		pci_write_config_byte(dev, 0xf4, config);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
			quirk_intel_irqbalance);
#endif

#if defined(CONFIG_HPET_TIMER)
unsigned long force_hpet_address;

static enum {
	NONE_FORCE_HPET_RESUME,
	OLD_ICH_FORCE_HPET_RESUME,
	ICH_FORCE_HPET_RESUME,
	VT8237_FORCE_HPET_RESUME,
	NVIDIA_FORCE_HPET_RESUME,
	ATI_FORCE_HPET_RESUME,
} force_hpet_resume_type;

static void __iomem *rcba_base;

static void ich_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address)
		return;

	if (rcba_base == NULL)
		BUG();

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		/* HPET disabled in HPTC. Trying to enable */
		writel(val | 0x80, rcba_base + 0x3404);
	}

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80))
		BUG();
	else
		printk(KERN_DEBUG "Force enabled HPET at resume\n");

	return;
}

static void ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(rcba);
	int err = 0;

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xF0, &rcba);
	rcba &= 0xFFFFC000;
	if (rcba == 0) {
		dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
			"cannot force enable HPET\n");
		return;
	}

	/* use bits 31:14, 16 kB aligned */
	rcba_base = ioremap_nocache(rcba, 0x4000);
	if (rcba_base == NULL) {
		dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
			"cannot force enable HPET\n");
		return;
	}

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);

	if (val & 0x80) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		iounmap(rcba_base);
		return;
	}

	/* HPET disabled in HPTC. Trying to enable */
	writel(val | 0x80, rcba_base + 0x3404);

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		err = 1;
	} else {
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
	}

	if (err) {
		force_hpet_address = 0;
		iounmap(rcba_base);
		dev_printk(KERN_DEBUG, &dev->dev,
			"Failed to force enable HPET\n");
	} else {
		force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
			 ich_force_enable_hpet);


static struct pci_dev *cached_dev;

static void hpet_print_force_info(void)
{
	printk(KERN_INFO "HPET not enabled in BIOS. "
	       "You might try hpet=force boot option\n");
}

static void old_ich_force_hpet_resume(void)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (!force_hpet_address || !cached_dev)
		return;

	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);

	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val == 0x4)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void old_ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	/*
	 * Bit 17 is HPET enable bit.
	 * Bit 16:15 control the HPET base address.
	 */
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);
	pci_write_config_dword(dev, 0xD0, gen_cntl);

	pci_read_config_dword(dev, 0xD0, &gen_cntl);

	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

/*
 * Undocumented chipset features. Make sure that the user enforced
 * this.
 */
static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
{
	if (hpet_force_user)
		old_ich_force_enable_hpet(dev);
	else
		hpet_print_force_info();
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
			 old_ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
			 old_ich_force_enable_hpet);


static void vt8237_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address || !cached_dev)
		return;

	val = 0xfed00000 | 0x80;
	pci_write_config_dword(cached_dev, 0x68, val);

	pci_read_config_dword(cached_dev, 0x68, &val);
	if (val & 0x80)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void vt8237_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	pci_read_config_dword(dev, 0x68, &val);
	/*
	 * Bit 7 is HPET enable bit.
	 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
	 */
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	val = 0xfed00000 | 0x80;
	pci_write_config_dword(dev, 0x68, val);

	pci_read_config_dword(dev, 0x68, &val);
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
			 vt8237_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
			 vt8237_force_enable_hpet);

static void ati_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static u32 ati_ixp4x0_rev(struct pci_dev *dev)
{
	u32 d;
	u8  b;

	pci_read_config_byte(dev, 0xac, &b);
	b &= ~(1<<5);
	pci_write_config_byte(dev, 0xac, b);
	pci_read_config_dword(dev, 0x70, &d);
	d |= 1<<8;
	pci_write_config_dword(dev, 0x70, d);
	pci_read_config_dword(dev, 0x8, &d);
	d &= 0xff;
	dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
	return d;
}

static void ati_force_enable_hpet(struct pci_dev *dev)
{
	u32 d, val;
	u8  b;

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	d = ati_ixp4x0_rev(dev);
	if (d  < 0x82)
		return;

	/* base address */
	pci_write_config_dword(dev, 0x14, 0xfed00000);
	pci_read_config_dword(dev, 0x14, &val);

	/* enable interrupt */
	outb(0x72, 0xcd6); b = inb(0xcd7);
	b |= 0x1;
	outb(0x72, 0xcd6); outb(b, 0xcd7);
	outb(0x72, 0xcd6); b = inb(0xcd7);
	if (!(b & 0x1))
		return;
	pci_read_config_dword(dev, 0x64, &d);
	d |= (1<<10);
	pci_write_config_dword(dev, 0x64, d);
	pci_read_config_dword(dev, 0x64, &d);
	if (!(d & (1<<10)))
		return;

	force_hpet_address = val;
	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		   force_hpet_address);
	cached_dev = dev;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
			 ati_force_enable_hpet);

/*
 * Undocumented chipset feature taken from LinuxBIOS.
 */
static void nvidia_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static void nvidia_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	pci_write_config_dword(dev, 0x44, 0xfed00001);
	pci_read_config_dword(dev, 0x44, &val);
	force_hpet_address = val & 0xfffffffe;
	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		force_hpet_address);
	cached_dev = dev;
	return;
}

/* ISA Bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
			nvidia_force_enable_hpet);

/* LPC bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
			nvidia_force_enable_hpet);

void force_hpet_resume(void)
{
	switch (force_hpet_resume_type) {
	case ICH_FORCE_HPET_RESUME:
		ich_force_hpet_resume();
		return;
	case OLD_ICH_FORCE_HPET_RESUME:
		old_ich_force_hpet_resume();
		return;
	case VT8237_FORCE_HPET_RESUME:
		vt8237_force_hpet_resume();
		return;
	case NVIDIA_FORCE_HPET_RESUME:
		nvidia_force_hpet_resume();
		return;
	case ATI_FORCE_HPET_RESUME:
		ati_force_hpet_resume();
		return;
	default:
		break;
	}
}

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains work-arounds for x86 and x86_64 platform bugs.
	3	*/
1da177e4 LT	4	#include <linux/pci.h>
	5	#include <linux/irq.h>
	6
d54bd57d VP	7	#include <asm/hpet.h>
d54bd57d VP	8
1da177e4 LT	9	#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
1da177e4 LT	10
a86f34b4	11	static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
1da177e4 LT	12	{
1da177e4 LT	13	u8 config, rev;
9585ca02	14	u16 word;
1da177e4 LT	15
	16	/* BIOS may enable hardware IRQ balancing for
	17	* E7520/E7320/E7525(revision ID 0x9 and below)
	18	* based platforms.
	19	* Disable SW irqbalance/affinity on those platforms.
	20	*/
a86f34b4	21	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
1da177e4 LT	22	if (rev > 0x9)
	23	return;
	24
a86f34b4 AM	25	/* enable access to config space*/
	26	pci_read_config_byte(dev, 0xf4, &config);
	27	pci_write_config_byte(dev, 0xf4, config\|0x2);
1da177e4	28
9585ca02 MW	29	/*
	30	* read xTPR register. We may not have a pci_dev for device 8
	31	* because it might be hidden until the above write.
	32	*/
	33	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
1da177e4 LT	34
1da177e4 LT	35	if (!(word & (1 << 13))) {
9ed88554	36	dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
9ed88554	37	"disabling irq balancing and affinity\n");
1da177e4 LT	38	noirqdebug_setup("");
	39	#ifdef CONFIG_PROC_FS
	40	no_irq_affinity = 1;
	41	#endif
	42	}
	43
a86f34b4	44	/* put back the original value for config space*/
da9bb1d2	45	if (!(config & 0x2))
a86f34b4	46	pci_write_config_byte(dev, 0xf4, config);
1da177e4	47	}
76492237 TG	48	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
	49	quirk_intel_irqbalance);
	50	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
	51	quirk_intel_irqbalance);
	52	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
	53	quirk_intel_irqbalance);
1da177e4	54	#endif
d54bd57d VP	55
	56	#if defined(CONFIG_HPET_TIMER)
	57	unsigned long force_hpet_address;
	58
bfe0c1cc VP	59	static enum {
	60	NONE_FORCE_HPET_RESUME,
	61	OLD_ICH_FORCE_HPET_RESUME,
b196884e	62	ICH_FORCE_HPET_RESUME,
d79a5f80 CC	63	VT8237_FORCE_HPET_RESUME,
d79a5f80 CC	64	NVIDIA_FORCE_HPET_RESUME,
e8aa4667	65	ATI_FORCE_HPET_RESUME,
bfe0c1cc VP	66	} force_hpet_resume_type;
bfe0c1cc VP	67
d54bd57d VP	68	static void __iomem *rcba_base;
d54bd57d VP	69
bfe0c1cc	70	static void ich_force_hpet_resume(void)
d54bd57d VP	71	{
	72	u32 val;
	73
	74	if (!force_hpet_address)
	75	return;
	76
	77	if (rcba_base == NULL)
	78	BUG();
	79
	80	/* read the Function Disable register, dword mode only */
	81	val = readl(rcba_base + 0x3404);
	82	if (!(val & 0x80)) {
	83	/* HPET disabled in HPTC. Trying to enable */
	84	writel(val \| 0x80, rcba_base + 0x3404);
	85	}
	86
	87	val = readl(rcba_base + 0x3404);
	88	if (!(val & 0x80))
	89	BUG();
	90	else
	91	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	92
	93	return;
	94	}
	95
	96	static void ich_force_enable_hpet(struct pci_dev *dev)
	97	{
	98	u32 val;
	99	u32 uninitialized_var(rcba);
	100	int err = 0;
	101
	102	if (hpet_address \|\| force_hpet_address)
	103	return;
	104
	105	pci_read_config_dword(dev, 0xF0, &rcba);
	106	rcba &= 0xFFFFC000;
	107	if (rcba == 0) {
9ed88554	108	dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
9ed88554	109	"cannot force enable HPET\n");
d54bd57d VP	110	return;
	111	}
	112
	113	/* use bits 31:14, 16 kB aligned */
	114	rcba_base = ioremap_nocache(rcba, 0x4000);
	115	if (rcba_base == NULL) {
9ed88554	116	dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
9ed88554	117	"cannot force enable HPET\n");
d54bd57d VP	118	return;
	119	}
	120
	121	/* read the Function Disable register, dword mode only */
	122	val = readl(rcba_base + 0x3404);
	123
	124	if (val & 0x80) {
	125	/* HPET is enabled in HPTC. Just not reported by BIOS */
	126	val = val & 0x3;
	127	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	128	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	129	"0x%lx\n", force_hpet_address);
d54bd57d VP	130	iounmap(rcba_base);
	131	return;
	132	}
	133
	134	/* HPET disabled in HPTC. Trying to enable */
	135	writel(val \| 0x80, rcba_base + 0x3404);
	136
	137	val = readl(rcba_base + 0x3404);
	138	if (!(val & 0x80)) {
	139	err = 1;
	140	} else {
	141	val = val & 0x3;
	142	force_hpet_address = 0xFED00000 \| (val << 12);
	143	}
	144
	145	if (err) {
	146	force_hpet_address = 0;
	147	iounmap(rcba_base);
9ed88554	148	dev_printk(KERN_DEBUG, &dev->dev,
9ed88554	149	"Failed to force enable HPET\n");
d54bd57d	150	} else {
bfe0c1cc	151	force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
9ed88554	152	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	153	"0x%lx\n", force_hpet_address);
d54bd57d VP	154	}
	155	}
	156
	157	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
76492237	158	ich_force_enable_hpet);
74e411cb KO	159	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
74e411cb KO	160	ich_force_enable_hpet);
d54bd57d	161	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
76492237	162	ich_force_enable_hpet);
ed6fb174	163	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
76492237	164	ich_force_enable_hpet);
d54bd57d	165	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
76492237	166	ich_force_enable_hpet);
d54bd57d	167	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
76492237	168	ich_force_enable_hpet);
d54bd57d	169	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
76492237	170	ich_force_enable_hpet);
dff244af AJS	171	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
dff244af AJS	172	ich_force_enable_hpet);
bfe0c1cc VP	173
	174
	175	static struct pci_dev *cached_dev;
	176
7c4728f4 TG	177	static void hpet_print_force_info(void)
	178	{
	179	printk(KERN_INFO "HPET not enabled in BIOS. "
	180	"You might try hpet=force boot option\n");
	181	}
	182
bfe0c1cc VP	183	static void old_ich_force_hpet_resume(void)
	184	{
	185	u32 val;
	186	u32 uninitialized_var(gen_cntl);
	187
	188	if (!force_hpet_address \|\| !cached_dev)
	189	return;
	190
	191	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	192	gen_cntl &= (~(0x7 << 15));
	193	gen_cntl \|= (0x4 << 15);
	194
	195	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	196	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	197	val = gen_cntl >> 15;
	198	val &= 0x7;
	199	if (val == 0x4)
	200	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	201	else
	202	BUG();
	203	}
	204
	205	static void old_ich_force_enable_hpet(struct pci_dev *dev)
	206	{
	207	u32 val;
	208	u32 uninitialized_var(gen_cntl);
	209
	210	if (hpet_address \|\| force_hpet_address)
	211	return;
	212
	213	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	214	/*
	215	* Bit 17 is HPET enable bit.
	216	* Bit 16:15 control the HPET base address.
	217	*/
	218	val = gen_cntl >> 15;
	219	val &= 0x7;
	220	if (val & 0x4) {
	221	val &= 0x3;
	222	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	223	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	224	force_hpet_address);
bfe0c1cc VP	225	return;
	226	}
	227
	228	/*
	229	* HPET is disabled. Trying enabling at FED00000 and check
	230	* whether it sticks
	231	*/
	232	gen_cntl &= (~(0x7 << 15));
	233	gen_cntl \|= (0x4 << 15);
	234	pci_write_config_dword(dev, 0xD0, gen_cntl);
	235
	236	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	237
	238	val = gen_cntl >> 15;
	239	val &= 0x7;
	240	if (val & 0x4) {
	241	/* HPET is enabled in HPTC. Just not reported by BIOS */
	242	val &= 0x3;
	243	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	244	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	245	"0x%lx\n", force_hpet_address);
32a2da64	246	cached_dev = dev;
bfe0c1cc VP	247	force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
	248	return;
	249	}
	250
9ed88554	251	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
bfe0c1cc VP	252	}
bfe0c1cc VP	253
158ad326 US	254	/*
	255	* Undocumented chipset features. Make sure that the user enforced
	256	* this.
	257	*/
	258	static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
	259	{
	260	if (hpet_force_user)
	261	old_ich_force_enable_hpet(dev);
7c4728f4 TG	262	else
7c4728f4 TG	263	hpet_print_force_info();
158ad326 US	264	}
158ad326 US	265
4c2a997c JB	266	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
4c2a997c JB	267	old_ich_force_enable_hpet_user);
158ad326 US	268	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
	269	old_ich_force_enable_hpet_user);
	270	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
	271	old_ich_force_enable_hpet_user);
	272	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	273	old_ich_force_enable_hpet_user);
	274	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
	275	old_ich_force_enable_hpet_user);
bfe0c1cc	276	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
76492237	277	old_ich_force_enable_hpet);
bfe0c1cc	278	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
76492237	279	old_ich_force_enable_hpet);
bfe0c1cc	280
b196884e US	281
	282	static void vt8237_force_hpet_resume(void)
	283	{
	284	u32 val;
	285
	286	if (!force_hpet_address \|\| !cached_dev)
	287	return;
	288
	289	val = 0xfed00000 \| 0x80;
	290	pci_write_config_dword(cached_dev, 0x68, val);
	291
	292	pci_read_config_dword(cached_dev, 0x68, &val);
	293	if (val & 0x80)
	294	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	295	else
	296	BUG();
	297	}
	298
	299	static void vt8237_force_enable_hpet(struct pci_dev *dev)
	300	{
	301	u32 uninitialized_var(val);
	302
7c4728f4 TG	303	if (hpet_address \|\| force_hpet_address)
	304	return;
	305
	306	if (!hpet_force_user) {
	307	hpet_print_force_info();
b196884e	308	return;
7c4728f4	309	}
b196884e US	310
	311	pci_read_config_dword(dev, 0x68, &val);
	312	/*
	313	* Bit 7 is HPET enable bit.
	314	* Bit 31:10 is HPET base address (contrary to what datasheet claims)
	315	*/
	316	if (val & 0x80) {
	317	force_hpet_address = (val & ~0x3ff);
9ed88554	318	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	319	force_hpet_address);
b196884e US	320	return;
	321	}
	322
	323	/*
	324	* HPET is disabled. Trying enabling at FED00000 and check
	325	* whether it sticks
	326	*/
	327	val = 0xfed00000 \| 0x80;
	328	pci_write_config_dword(dev, 0x68, val);
	329
	330	pci_read_config_dword(dev, 0x68, &val);
	331	if (val & 0x80) {
	332	force_hpet_address = (val & ~0x3ff);
9ed88554	333	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	334	"0x%lx\n", force_hpet_address);
b196884e US	335	cached_dev = dev;
	336	force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
	337	return;
	338	}
	339
9ed88554	340	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
b196884e US	341	}
	342
	343	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
	344	vt8237_force_enable_hpet);
	345	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	346	vt8237_force_enable_hpet);
	347
e8aa4667 AH	348	static void ati_force_hpet_resume(void)
	349	{
	350	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	351	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	352	}
	353
e7250b8a AH	354	static u32 ati_ixp4x0_rev(struct pci_dev *dev)
	355	{
	356	u32 d;
	357	u8 b;
	358
	359	pci_read_config_byte(dev, 0xac, &b);
	360	b &= ~(1<<5);
	361	pci_write_config_byte(dev, 0xac, b);
	362	pci_read_config_dword(dev, 0x70, &d);
	363	d \|= 1<<8;
	364	pci_write_config_dword(dev, 0x70, d);
	365	pci_read_config_dword(dev, 0x8, &d);
	366	d &= 0xff;
	367	dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
	368	return d;
	369	}
	370
e8aa4667 AH	371	static void ati_force_enable_hpet(struct pci_dev *dev)
e8aa4667 AH	372	{
e7250b8a AH	373	u32 d, val;
e7250b8a AH	374	u8 b;
e8aa4667	375
7c4728f4 TG	376	if (hpet_address \|\| force_hpet_address)
	377	return;
	378
	379	if (!hpet_force_user) {
	380	hpet_print_force_info();
e8aa4667	381	return;
7c4728f4	382	}
e8aa4667	383
e7250b8a AH	384	d = ati_ixp4x0_rev(dev);
	385	if (d < 0x82)
	386	return;
	387
	388	/* base address */
e8aa4667 AH	389	pci_write_config_dword(dev, 0x14, 0xfed00000);
e8aa4667 AH	390	pci_read_config_dword(dev, 0x14, &val);
e7250b8a AH	391
	392	/* enable interrupt */
	393	outb(0x72, 0xcd6); b = inb(0xcd7);
	394	b \|= 0x1;
	395	outb(0x72, 0xcd6); outb(b, 0xcd7);
	396	outb(0x72, 0xcd6); b = inb(0xcd7);
	397	if (!(b & 0x1))
	398	return;
	399	pci_read_config_dword(dev, 0x64, &d);
	400	d \|= (1<<10);
	401	pci_write_config_dword(dev, 0x64, d);
	402	pci_read_config_dword(dev, 0x64, &d);
	403	if (!(d & (1<<10)))
	404	return;
	405
e8aa4667 AH	406	force_hpet_address = val;
	407	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	408	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
	409	force_hpet_address);
	410	cached_dev = dev;
e8aa4667 AH	411	}
	412	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
	413	ati_force_enable_hpet);
	414
d79a5f80 CC	415	/*
	416	* Undocumented chipset feature taken from LinuxBIOS.
	417	*/
	418	static void nvidia_force_hpet_resume(void)
	419	{
	420	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	421	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	422	}
	423
	424	static void nvidia_force_enable_hpet(struct pci_dev *dev)
	425	{
	426	u32 uninitialized_var(val);
	427
7c4728f4 TG	428	if (hpet_address \|\| force_hpet_address)
	429	return;
	430
	431	if (!hpet_force_user) {
	432	hpet_print_force_info();
d79a5f80	433	return;
7c4728f4	434	}
d79a5f80 CC	435
	436	pci_write_config_dword(dev, 0x44, 0xfed00001);
	437	pci_read_config_dword(dev, 0x44, &val);
	438	force_hpet_address = val & 0xfffffffe;
	439	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
9ed88554	440	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
d79a5f80 CC	441	force_hpet_address);
	442	cached_dev = dev;
	443	return;
	444	}
	445
	446	/* ISA Bridges */
	447	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
	448	nvidia_force_enable_hpet);
	449	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
	450	nvidia_force_enable_hpet);
b196884e	451
1b82ba6e	452	/* LPC bridges */
96bcf458 ZL	453	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
96bcf458 ZL	454	nvidia_force_enable_hpet);
1b82ba6e CC	455	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
	456	nvidia_force_enable_hpet);
	457	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
	458	nvidia_force_enable_hpet);
	459	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
	460	nvidia_force_enable_hpet);
	461	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
	462	nvidia_force_enable_hpet);
	463	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
	464	nvidia_force_enable_hpet);
	465	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
	466	nvidia_force_enable_hpet);
	467	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
	468	nvidia_force_enable_hpet);
	469	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
	470	nvidia_force_enable_hpet);
	471
bfe0c1cc VP	472	void force_hpet_resume(void)
	473	{
	474	switch (force_hpet_resume_type) {
4a5a77d1 HH	475	case ICH_FORCE_HPET_RESUME:
	476	ich_force_hpet_resume();
	477	return;
	478	case OLD_ICH_FORCE_HPET_RESUME:
	479	old_ich_force_hpet_resume();
	480	return;
	481	case VT8237_FORCE_HPET_RESUME:
	482	vt8237_force_hpet_resume();
	483	return;
	484	case NVIDIA_FORCE_HPET_RESUME:
	485	nvidia_force_hpet_resume();
	486	return;
e8aa4667 AH	487	case ATI_FORCE_HPET_RESUME:
	488	ati_force_hpet_resume();
	489	return;
4a5a77d1	490	default:
bfe0c1cc VP	491	break;
	492	}
	493	}
	494
d54bd57d	495	#endif