Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for x86 and x86_64 platform bugs. | |
3 | */ | |
1da177e4 LT |
4 | #include <linux/pci.h> |
5 | #include <linux/irq.h> | |
6 | ||
d54bd57d VP |
7 | #include <asm/hpet.h> |
8 | ||
1da177e4 LT |
9 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) |
10 | ||
a86f34b4 | 11 | static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) |
1da177e4 LT |
12 | { |
13 | u8 config, rev; | |
14 | u32 word; | |
15 | ||
16 | /* BIOS may enable hardware IRQ balancing for | |
17 | * E7520/E7320/E7525(revision ID 0x9 and below) | |
18 | * based platforms. | |
19 | * Disable SW irqbalance/affinity on those platforms. | |
20 | */ | |
a86f34b4 | 21 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
1da177e4 LT |
22 | if (rev > 0x9) |
23 | return; | |
24 | ||
a86f34b4 AM |
25 | /* enable access to config space*/ |
26 | pci_read_config_byte(dev, 0xf4, &config); | |
27 | pci_write_config_byte(dev, 0xf4, config|0x2); | |
1da177e4 LT |
28 | |
29 | /* read xTPR register */ | |
a86f34b4 | 30 | raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word); |
1da177e4 LT |
31 | |
32 | if (!(word & (1 << 13))) { | |
38377be8 DJ |
33 | printk(KERN_INFO "Intel E7520/7320/7525 detected. " |
34 | "Disabling irq balancing and affinity\n"); | |
1da177e4 LT |
35 | #ifdef CONFIG_IRQBALANCE |
36 | irqbalance_disable(""); | |
37 | #endif | |
38 | noirqdebug_setup(""); | |
39 | #ifdef CONFIG_PROC_FS | |
40 | no_irq_affinity = 1; | |
41 | #endif | |
42 | } | |
43 | ||
a86f34b4 | 44 | /* put back the original value for config space*/ |
da9bb1d2 | 45 | if (!(config & 0x2)) |
a86f34b4 | 46 | pci_write_config_byte(dev, 0xf4, config); |
1da177e4 | 47 | } |
a86f34b4 AM |
48 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_intel_irqbalance); |
49 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_intel_irqbalance); | |
50 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_intel_irqbalance); | |
1da177e4 | 51 | #endif |
d54bd57d VP |
52 | |
53 | #if defined(CONFIG_HPET_TIMER) | |
54 | unsigned long force_hpet_address; | |
55 | ||
56 | static void __iomem *rcba_base; | |
57 | ||
58 | void ich_force_hpet_resume(void) | |
59 | { | |
60 | u32 val; | |
61 | ||
62 | if (!force_hpet_address) | |
63 | return; | |
64 | ||
65 | if (rcba_base == NULL) | |
66 | BUG(); | |
67 | ||
68 | /* read the Function Disable register, dword mode only */ | |
69 | val = readl(rcba_base + 0x3404); | |
70 | if (!(val & 0x80)) { | |
71 | /* HPET disabled in HPTC. Trying to enable */ | |
72 | writel(val | 0x80, rcba_base + 0x3404); | |
73 | } | |
74 | ||
75 | val = readl(rcba_base + 0x3404); | |
76 | if (!(val & 0x80)) | |
77 | BUG(); | |
78 | else | |
79 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); | |
80 | ||
81 | return; | |
82 | } | |
83 | ||
84 | static void ich_force_enable_hpet(struct pci_dev *dev) | |
85 | { | |
86 | u32 val; | |
87 | u32 uninitialized_var(rcba); | |
88 | int err = 0; | |
89 | ||
90 | if (hpet_address || force_hpet_address) | |
91 | return; | |
92 | ||
93 | pci_read_config_dword(dev, 0xF0, &rcba); | |
94 | rcba &= 0xFFFFC000; | |
95 | if (rcba == 0) { | |
96 | printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n"); | |
97 | return; | |
98 | } | |
99 | ||
100 | /* use bits 31:14, 16 kB aligned */ | |
101 | rcba_base = ioremap_nocache(rcba, 0x4000); | |
102 | if (rcba_base == NULL) { | |
103 | printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n"); | |
104 | return; | |
105 | } | |
106 | ||
107 | /* read the Function Disable register, dword mode only */ | |
108 | val = readl(rcba_base + 0x3404); | |
109 | ||
110 | if (val & 0x80) { | |
111 | /* HPET is enabled in HPTC. Just not reported by BIOS */ | |
112 | val = val & 0x3; | |
113 | force_hpet_address = 0xFED00000 | (val << 12); | |
114 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | |
115 | force_hpet_address); | |
116 | iounmap(rcba_base); | |
117 | return; | |
118 | } | |
119 | ||
120 | /* HPET disabled in HPTC. Trying to enable */ | |
121 | writel(val | 0x80, rcba_base + 0x3404); | |
122 | ||
123 | val = readl(rcba_base + 0x3404); | |
124 | if (!(val & 0x80)) { | |
125 | err = 1; | |
126 | } else { | |
127 | val = val & 0x3; | |
128 | force_hpet_address = 0xFED00000 | (val << 12); | |
129 | } | |
130 | ||
131 | if (err) { | |
132 | force_hpet_address = 0; | |
133 | iounmap(rcba_base); | |
134 | printk(KERN_DEBUG "Failed to force enable HPET\n"); | |
135 | } else { | |
136 | printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", | |
137 | force_hpet_address); | |
138 | } | |
139 | } | |
140 | ||
141 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, | |
142 | ich_force_enable_hpet); | |
143 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, | |
144 | ich_force_enable_hpet); | |
145 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, | |
146 | ich_force_enable_hpet); | |
147 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, | |
148 | ich_force_enable_hpet); | |
149 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, | |
150 | ich_force_enable_hpet); | |
151 | #endif |