Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/module.h> |
cd6ed525 | 2 | #include <linux/reboot.h> |
4d022e35 MB |
3 | #include <linux/init.h> |
4 | #include <linux/pm.h> | |
5 | #include <linux/efi.h> | |
6 | #include <acpi/reboot.h> | |
7 | #include <asm/io.h> | |
1da177e4 | 8 | #include <asm/apic.h> |
4d37e7e3 | 9 | #include <asm/desc.h> |
4d022e35 | 10 | #include <asm/hpet.h> |
68db065c | 11 | #include <asm/pgtable.h> |
4412620f | 12 | #include <asm/proto.h> |
973efae2 | 13 | #include <asm/reboot_fixups.h> |
07f3331c | 14 | #include <asm/reboot.h> |
82487711 | 15 | #include <asm/pci_x86.h> |
d176720d | 16 | #include <asm/virtext.h> |
1da177e4 | 17 | |
4d022e35 MB |
18 | #ifdef CONFIG_X86_32 |
19 | # include <linux/dmi.h> | |
20 | # include <linux/ctype.h> | |
21 | # include <linux/mc146818rtc.h> | |
4d022e35 MB |
22 | #else |
23 | # include <asm/iommu.h> | |
24 | #endif | |
25 | ||
2ddded21 | 26 | #include <mach_ipi.h> |
2ddded21 | 27 | |
1da177e4 LT |
28 | /* |
29 | * Power off function, if any | |
30 | */ | |
31 | void (*pm_power_off)(void); | |
129f6946 | 32 | EXPORT_SYMBOL(pm_power_off); |
1da177e4 | 33 | |
ebdd561a | 34 | static const struct desc_ptr no_idt = {}; |
1da177e4 | 35 | static int reboot_mode; |
8d00450d | 36 | enum reboot_type reboot_type = BOOT_KBD; |
4d022e35 | 37 | int reboot_force; |
1da177e4 | 38 | |
4d022e35 | 39 | #if defined(CONFIG_X86_32) && defined(CONFIG_SMP) |
1da177e4 | 40 | static int reboot_cpu = -1; |
1da177e4 | 41 | #endif |
4d022e35 | 42 | |
d176720d EH |
43 | /* This is set if we need to go through the 'emergency' path. |
44 | * When machine_emergency_restart() is called, we may be on | |
45 | * an inconsistent state and won't be able to do a clean cleanup | |
46 | */ | |
47 | static int reboot_emergency; | |
48 | ||
14d7ca5c PA |
49 | /* This is set by the PCI code if either type 1 or type 2 PCI is detected */ |
50 | bool port_cf9_safe = false; | |
51 | ||
52 | /* reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci] | |
4d022e35 MB |
53 | warm Don't set the cold reboot flag |
54 | cold Set the cold reboot flag | |
55 | bios Reboot by jumping through the BIOS (only for X86_32) | |
56 | smp Reboot by executing reset on BSP or other CPU (only for X86_32) | |
57 | triple Force a triple fault (init) | |
58 | kbd Use the keyboard controller. cold reset (default) | |
59 | acpi Use the RESET_REG in the FADT | |
60 | efi Use efi reset_system runtime service | |
14d7ca5c | 61 | pci Use the so-called "PCI reset register", CF9 |
4d022e35 MB |
62 | force Avoid anything that could hang. |
63 | */ | |
1da177e4 LT |
64 | static int __init reboot_setup(char *str) |
65 | { | |
4d022e35 | 66 | for (;;) { |
1da177e4 | 67 | switch (*str) { |
4d022e35 | 68 | case 'w': |
1da177e4 LT |
69 | reboot_mode = 0x1234; |
70 | break; | |
4d022e35 MB |
71 | |
72 | case 'c': | |
73 | reboot_mode = 0; | |
1da177e4 | 74 | break; |
4d022e35 MB |
75 | |
76 | #ifdef CONFIG_X86_32 | |
1da177e4 | 77 | #ifdef CONFIG_SMP |
4d022e35 | 78 | case 's': |
6f673d83 | 79 | if (isdigit(*(str+1))) { |
1da177e4 | 80 | reboot_cpu = (int) (*(str+1) - '0'); |
6f673d83 | 81 | if (isdigit(*(str+2))) |
1da177e4 LT |
82 | reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0'); |
83 | } | |
4d022e35 MB |
84 | /* we will leave sorting out the final value |
85 | when we are ready to reboot, since we might not | |
86 | have set up boot_cpu_id or smp_num_cpu */ | |
1da177e4 | 87 | break; |
4d022e35 MB |
88 | #endif /* CONFIG_SMP */ |
89 | ||
90 | case 'b': | |
1da177e4 | 91 | #endif |
4d022e35 MB |
92 | case 'a': |
93 | case 'k': | |
94 | case 't': | |
95 | case 'e': | |
14d7ca5c | 96 | case 'p': |
4d022e35 MB |
97 | reboot_type = *str; |
98 | break; | |
99 | ||
100 | case 'f': | |
101 | reboot_force = 1; | |
102 | break; | |
1da177e4 | 103 | } |
4d022e35 MB |
104 | |
105 | str = strchr(str, ','); | |
106 | if (str) | |
1da177e4 LT |
107 | str++; |
108 | else | |
109 | break; | |
110 | } | |
111 | return 1; | |
112 | } | |
113 | ||
114 | __setup("reboot=", reboot_setup); | |
115 | ||
4d022e35 MB |
116 | |
117 | #ifdef CONFIG_X86_32 | |
1da177e4 LT |
118 | /* |
119 | * Reboot options and system auto-detection code provided by | |
120 | * Dell Inc. so their systems "just work". :-) | |
121 | */ | |
122 | ||
123 | /* | |
4d022e35 MB |
124 | * Some machines require the "reboot=b" commandline option, |
125 | * this quirk makes that automatic. | |
1da177e4 | 126 | */ |
1855256c | 127 | static int __init set_bios_reboot(const struct dmi_system_id *d) |
1da177e4 | 128 | { |
4d022e35 MB |
129 | if (reboot_type != BOOT_BIOS) { |
130 | reboot_type = BOOT_BIOS; | |
1da177e4 LT |
131 | printk(KERN_INFO "%s series board detected. Selecting BIOS-method for reboots.\n", d->ident); |
132 | } | |
133 | return 0; | |
134 | } | |
135 | ||
1da177e4 | 136 | static struct dmi_system_id __initdata reboot_dmi_table[] = { |
b9e82af8 TG |
137 | { /* Handle problems with rebooting on Dell E520's */ |
138 | .callback = set_bios_reboot, | |
139 | .ident = "Dell E520", | |
140 | .matches = { | |
141 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
142 | DMI_MATCH(DMI_PRODUCT_NAME, "Dell DM061"), | |
143 | }, | |
144 | }, | |
1da177e4 | 145 | { /* Handle problems with rebooting on Dell 1300's */ |
dd2a1305 | 146 | .callback = set_bios_reboot, |
1da177e4 LT |
147 | .ident = "Dell PowerEdge 1300", |
148 | .matches = { | |
149 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"), | |
150 | DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1300/"), | |
151 | }, | |
152 | }, | |
153 | { /* Handle problems with rebooting on Dell 300's */ | |
154 | .callback = set_bios_reboot, | |
155 | .ident = "Dell PowerEdge 300", | |
156 | .matches = { | |
157 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"), | |
158 | DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 300/"), | |
159 | }, | |
160 | }, | |
df2edcf3 JJ |
161 | { /* Handle problems with rebooting on Dell Optiplex 745's SFF*/ |
162 | .callback = set_bios_reboot, | |
163 | .ident = "Dell OptiPlex 745", | |
164 | .matches = { | |
165 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
166 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 745"), | |
df2edcf3 JJ |
167 | }, |
168 | }, | |
fc115bf1 CK |
169 | { /* Handle problems with rebooting on Dell Optiplex 745's DFF*/ |
170 | .callback = set_bios_reboot, | |
171 | .ident = "Dell OptiPlex 745", | |
172 | .matches = { | |
173 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
174 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 745"), | |
175 | DMI_MATCH(DMI_BOARD_NAME, "0MM599"), | |
176 | }, | |
177 | }, | |
fc1c8925 HAA |
178 | { /* Handle problems with rebooting on Dell Optiplex 745 with 0KW626 */ |
179 | .callback = set_bios_reboot, | |
180 | .ident = "Dell OptiPlex 745", | |
181 | .matches = { | |
182 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
183 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 745"), | |
184 | DMI_MATCH(DMI_BOARD_NAME, "0KW626"), | |
185 | }, | |
186 | }, | |
093bac15 SC |
187 | { /* Handle problems with rebooting on Dell Optiplex 330 with 0KP561 */ |
188 | .callback = set_bios_reboot, | |
189 | .ident = "Dell OptiPlex 330", | |
190 | .matches = { | |
191 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
192 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 330"), | |
193 | DMI_MATCH(DMI_BOARD_NAME, "0KP561"), | |
194 | }, | |
195 | }, | |
1da177e4 LT |
196 | { /* Handle problems with rebooting on Dell 2400's */ |
197 | .callback = set_bios_reboot, | |
198 | .ident = "Dell PowerEdge 2400", | |
199 | .matches = { | |
200 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"), | |
201 | DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2400"), | |
202 | }, | |
203 | }, | |
fab3b58d IM |
204 | { /* Handle problems with rebooting on Dell T5400's */ |
205 | .callback = set_bios_reboot, | |
206 | .ident = "Dell Precision T5400", | |
207 | .matches = { | |
208 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
209 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision WorkStation T5400"), | |
210 | }, | |
211 | }, | |
766c3f94 | 212 | { /* Handle problems with rebooting on HP laptops */ |
d91b14c4 | 213 | .callback = set_bios_reboot, |
766c3f94 | 214 | .ident = "HP Compaq Laptop", |
d91b14c4 TV |
215 | .matches = { |
216 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
766c3f94 | 217 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), |
d91b14c4 TV |
218 | }, |
219 | }, | |
1da177e4 LT |
220 | { } |
221 | }; | |
222 | ||
223 | static int __init reboot_init(void) | |
224 | { | |
225 | dmi_check_system(reboot_dmi_table); | |
226 | return 0; | |
227 | } | |
1da177e4 LT |
228 | core_initcall(reboot_init); |
229 | ||
230 | /* The following code and data reboots the machine by switching to real | |
231 | mode and jumping to the BIOS reset entry point, as if the CPU has | |
232 | really been reset. The previous version asked the keyboard | |
233 | controller to pulse the CPU reset line, which is more thorough, but | |
234 | doesn't work with at least one type of 486 motherboard. It is easy | |
235 | to stop this code working; hence the copious comments. */ | |
ebdd561a | 236 | static const unsigned long long |
1da177e4 LT |
237 | real_mode_gdt_entries [3] = |
238 | { | |
239 | 0x0000000000000000ULL, /* Null descriptor */ | |
ebdd561a JB |
240 | 0x00009b000000ffffULL, /* 16-bit real-mode 64k code at 0x00000000 */ |
241 | 0x000093000100ffffULL /* 16-bit real-mode 64k data at 0x00000100 */ | |
1da177e4 LT |
242 | }; |
243 | ||
ebdd561a | 244 | static const struct desc_ptr |
05f4a3ec | 245 | real_mode_gdt = { sizeof (real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries }, |
4d022e35 | 246 | real_mode_idt = { 0x3ff, 0 }; |
1da177e4 LT |
247 | |
248 | /* This is 16-bit protected mode code to disable paging and the cache, | |
249 | switch to real mode and jump to the BIOS reset code. | |
250 | ||
251 | The instruction that switches to real mode by writing to CR0 must be | |
252 | followed immediately by a far jump instruction, which set CS to a | |
253 | valid value for real mode, and flushes the prefetch queue to avoid | |
254 | running instructions that have already been decoded in protected | |
255 | mode. | |
256 | ||
257 | Clears all the flags except ET, especially PG (paging), PE | |
258 | (protected-mode enable) and TS (task switch for coprocessor state | |
259 | save). Flushes the TLB after paging has been disabled. Sets CD and | |
260 | NW, to disable the cache on a 486, and invalidates the cache. This | |
261 | is more like the state of a 486 after reset. I don't know if | |
262 | something else should be done for other chips. | |
263 | ||
264 | More could be done here to set up the registers as if a CPU reset had | |
265 | occurred; hopefully real BIOSs don't assume much. */ | |
ebdd561a | 266 | static const unsigned char real_mode_switch [] = |
1da177e4 LT |
267 | { |
268 | 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ | |
269 | 0x66, 0x83, 0xe0, 0x11, /* andl $0x00000011,%eax */ | |
270 | 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ | |
271 | 0x66, 0x0f, 0x22, 0xc0, /* movl %eax,%cr0 */ | |
272 | 0x66, 0x0f, 0x22, 0xd8, /* movl %eax,%cr3 */ | |
273 | 0x66, 0x0f, 0x20, 0xc3, /* movl %cr0,%ebx */ | |
274 | 0x66, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x60, /* andl $0x60000000,%ebx */ | |
275 | 0x74, 0x02, /* jz f */ | |
276 | 0x0f, 0x09, /* wbinvd */ | |
277 | 0x24, 0x10, /* f: andb $0x10,al */ | |
278 | 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ | |
279 | }; | |
ebdd561a | 280 | static const unsigned char jump_to_bios [] = |
1da177e4 LT |
281 | { |
282 | 0xea, 0x00, 0x00, 0xff, 0xff /* ljmp $0xffff,$0x0000 */ | |
283 | }; | |
284 | ||
285 | /* | |
286 | * Switch to real mode and then execute the code | |
287 | * specified by the code and length parameters. | |
288 | * We assume that length will aways be less that 100! | |
289 | */ | |
ebdd561a | 290 | void machine_real_restart(const unsigned char *code, int length) |
1da177e4 | 291 | { |
1da177e4 LT |
292 | local_irq_disable(); |
293 | ||
294 | /* Write zero to CMOS register number 0x0f, which the BIOS POST | |
295 | routine will recognize as telling it to do a proper reboot. (Well | |
296 | that's what this book in front of me says -- it may only apply to | |
297 | the Phoenix BIOS though, it's not clear). At the same time, | |
298 | disable NMIs by setting the top bit in the CMOS address register, | |
299 | as we're about to do peculiar things to the CPU. I'm not sure if | |
300 | `outb_p' is needed instead of just `outb'. Use it to be on the | |
301 | safe side. (Yes, CMOS_WRITE does outb_p's. - Paul G.) | |
302 | */ | |
62dbc210 | 303 | spin_lock(&rtc_lock); |
1da177e4 | 304 | CMOS_WRITE(0x00, 0x8f); |
62dbc210 | 305 | spin_unlock(&rtc_lock); |
1da177e4 LT |
306 | |
307 | /* Remap the kernel at virtual address zero, as well as offset zero | |
308 | from the kernel segment. This assumes the kernel segment starts at | |
309 | virtual address PAGE_OFFSET. */ | |
68db065c | 310 | memcpy(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
4d022e35 | 311 | sizeof(swapper_pg_dir [0]) * KERNEL_PGD_PTRS); |
1da177e4 LT |
312 | |
313 | /* | |
314 | * Use `swapper_pg_dir' as our page directory. | |
315 | */ | |
316 | load_cr3(swapper_pg_dir); | |
317 | ||
318 | /* Write 0x1234 to absolute memory location 0x472. The BIOS reads | |
319 | this on booting to tell it to "Bypass memory test (also warm | |
320 | boot)". This seems like a fairly standard thing that gets set by | |
321 | REBOOT.COM programs, and the previous reset routine did this | |
322 | too. */ | |
1da177e4 LT |
323 | *((unsigned short *)0x472) = reboot_mode; |
324 | ||
325 | /* For the switch to real mode, copy some code to low memory. It has | |
326 | to be in the first 64k because it is running in 16-bit mode, and it | |
327 | has to have the same physical and virtual address, because it turns | |
328 | off paging. Copy it near the end of the first page, out of the way | |
329 | of BIOS variables. */ | |
4d022e35 | 330 | memcpy((void *)(0x1000 - sizeof(real_mode_switch) - 100), |
1da177e4 | 331 | real_mode_switch, sizeof (real_mode_switch)); |
4d022e35 | 332 | memcpy((void *)(0x1000 - 100), code, length); |
1da177e4 LT |
333 | |
334 | /* Set up the IDT for real mode. */ | |
4d37e7e3 | 335 | load_idt(&real_mode_idt); |
1da177e4 LT |
336 | |
337 | /* Set up a GDT from which we can load segment descriptors for real | |
338 | mode. The GDT is not used in real mode; it is just needed here to | |
339 | prepare the descriptors. */ | |
4d37e7e3 | 340 | load_gdt(&real_mode_gdt); |
1da177e4 LT |
341 | |
342 | /* Load the data segment registers, and thus the descriptors ready for | |
343 | real mode. The base address of each segment is 0x100, 16 times the | |
344 | selector value being loaded here. This is so that the segment | |
345 | registers don't have to be reloaded after switching to real mode: | |
346 | the values are consistent for real mode operation already. */ | |
1da177e4 LT |
347 | __asm__ __volatile__ ("movl $0x0010,%%eax\n" |
348 | "\tmovl %%eax,%%ds\n" | |
349 | "\tmovl %%eax,%%es\n" | |
350 | "\tmovl %%eax,%%fs\n" | |
351 | "\tmovl %%eax,%%gs\n" | |
352 | "\tmovl %%eax,%%ss" : : : "eax"); | |
353 | ||
354 | /* Jump to the 16-bit code that we copied earlier. It disables paging | |
355 | and the cache, switches to real mode, and jumps to the BIOS reset | |
356 | entry point. */ | |
1da177e4 LT |
357 | __asm__ __volatile__ ("ljmp $0x0008,%0" |
358 | : | |
4d022e35 | 359 | : "i" ((void *)(0x1000 - sizeof (real_mode_switch) - 100))); |
1da177e4 | 360 | } |
129f6946 AD |
361 | #ifdef CONFIG_APM_MODULE |
362 | EXPORT_SYMBOL(machine_real_restart); | |
363 | #endif | |
1da177e4 | 364 | |
4d022e35 MB |
365 | #endif /* CONFIG_X86_32 */ |
366 | ||
367 | static inline void kb_wait(void) | |
368 | { | |
369 | int i; | |
370 | ||
c84d6af8 AC |
371 | for (i = 0; i < 0x10000; i++) { |
372 | if ((inb(0x64) & 0x02) == 0) | |
4d022e35 | 373 | break; |
c84d6af8 AC |
374 | udelay(2); |
375 | } | |
4d022e35 MB |
376 | } |
377 | ||
d176720d EH |
378 | static void vmxoff_nmi(int cpu, struct die_args *args) |
379 | { | |
380 | cpu_emergency_vmxoff(); | |
381 | } | |
382 | ||
383 | /* Use NMIs as IPIs to tell all CPUs to disable virtualization | |
384 | */ | |
385 | static void emergency_vmx_disable_all(void) | |
386 | { | |
387 | /* Just make sure we won't change CPUs while doing this */ | |
388 | local_irq_disable(); | |
389 | ||
390 | /* We need to disable VMX on all CPUs before rebooting, otherwise | |
391 | * we risk hanging up the machine, because the CPU ignore INIT | |
392 | * signals when VMX is enabled. | |
393 | * | |
394 | * We can't take any locks and we may be on an inconsistent | |
395 | * state, so we use NMIs as IPIs to tell the other CPUs to disable | |
396 | * VMX and halt. | |
397 | * | |
398 | * For safety, we will avoid running the nmi_shootdown_cpus() | |
399 | * stuff unnecessarily, but we don't have a way to check | |
400 | * if other CPUs have VMX enabled. So we will call it only if the | |
401 | * CPU we are running on has VMX enabled. | |
402 | * | |
403 | * We will miss cases where VMX is not enabled on all CPUs. This | |
404 | * shouldn't do much harm because KVM always enable VMX on all | |
405 | * CPUs anyway. But we can miss it on the small window where KVM | |
406 | * is still enabling VMX. | |
407 | */ | |
408 | if (cpu_has_vmx() && cpu_vmx_enabled()) { | |
409 | /* Disable VMX on this CPU. | |
410 | */ | |
411 | cpu_vmxoff(); | |
412 | ||
413 | /* Halt and disable VMX on the other CPUs */ | |
414 | nmi_shootdown_cpus(vmxoff_nmi); | |
415 | ||
416 | } | |
417 | } | |
418 | ||
419 | ||
7432d149 IM |
420 | void __attribute__((weak)) mach_reboot_fixups(void) |
421 | { | |
422 | } | |
423 | ||
416e2d63 | 424 | static void native_machine_emergency_restart(void) |
1da177e4 | 425 | { |
4d022e35 MB |
426 | int i; |
427 | ||
d176720d EH |
428 | if (reboot_emergency) |
429 | emergency_vmx_disable_all(); | |
430 | ||
4d022e35 MB |
431 | /* Tell the BIOS if we want cold or warm reboot */ |
432 | *((unsigned short *)__va(0x472)) = reboot_mode; | |
433 | ||
434 | for (;;) { | |
435 | /* Could also try the reset bit in the Hammer NB */ | |
436 | switch (reboot_type) { | |
437 | case BOOT_KBD: | |
7432d149 IM |
438 | mach_reboot_fixups(); /* for board specific fixups */ |
439 | ||
4d022e35 MB |
440 | for (i = 0; i < 10; i++) { |
441 | kb_wait(); | |
442 | udelay(50); | |
443 | outb(0xfe, 0x64); /* pulse reset low */ | |
444 | udelay(50); | |
445 | } | |
446 | ||
447 | case BOOT_TRIPLE: | |
ebdd561a | 448 | load_idt(&no_idt); |
4d022e35 MB |
449 | __asm__ __volatile__("int3"); |
450 | ||
451 | reboot_type = BOOT_KBD; | |
452 | break; | |
453 | ||
454 | #ifdef CONFIG_X86_32 | |
455 | case BOOT_BIOS: | |
456 | machine_real_restart(jump_to_bios, sizeof(jump_to_bios)); | |
457 | ||
458 | reboot_type = BOOT_KBD; | |
459 | break; | |
460 | #endif | |
461 | ||
462 | case BOOT_ACPI: | |
463 | acpi_reboot(); | |
464 | reboot_type = BOOT_KBD; | |
465 | break; | |
466 | ||
4d022e35 MB |
467 | case BOOT_EFI: |
468 | if (efi_enabled) | |
14d7ca5c PA |
469 | efi.reset_system(reboot_mode ? |
470 | EFI_RESET_WARM : | |
471 | EFI_RESET_COLD, | |
4d022e35 | 472 | EFI_SUCCESS, 0, NULL); |
b47b9288 | 473 | reboot_type = BOOT_KBD; |
14d7ca5c | 474 | break; |
4d022e35 | 475 | |
14d7ca5c PA |
476 | case BOOT_CF9: |
477 | port_cf9_safe = true; | |
478 | /* fall through */ | |
4d022e35 | 479 | |
14d7ca5c PA |
480 | case BOOT_CF9_COND: |
481 | if (port_cf9_safe) { | |
482 | u8 cf9 = inb(0xcf9) & ~6; | |
483 | outb(cf9|2, 0xcf9); /* Request hard reset */ | |
484 | udelay(50); | |
485 | outb(cf9|6, 0xcf9); /* Actually do the reset */ | |
486 | udelay(50); | |
487 | } | |
4d022e35 MB |
488 | reboot_type = BOOT_KBD; |
489 | break; | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
3c62c625 | 494 | void native_machine_shutdown(void) |
4d022e35 MB |
495 | { |
496 | /* Stop the cpus and apics */ | |
1da177e4 | 497 | #ifdef CONFIG_SMP |
dd2a1305 EB |
498 | |
499 | /* The boot cpu is always logical cpu 0 */ | |
65c01184 | 500 | int reboot_cpu_id = 0; |
dd2a1305 | 501 | |
4d022e35 | 502 | #ifdef CONFIG_X86_32 |
dd2a1305 | 503 | /* See if there has been given a command line override */ |
d8e392e7 | 504 | if ((reboot_cpu != -1) && (reboot_cpu < NR_CPUS) && |
0bc3cc03 | 505 | cpu_online(reboot_cpu)) |
dd2a1305 | 506 | reboot_cpu_id = reboot_cpu; |
4d022e35 | 507 | #endif |
1da177e4 | 508 | |
4d022e35 | 509 | /* Make certain the cpu I'm about to reboot on is online */ |
0bc3cc03 | 510 | if (!cpu_online(reboot_cpu_id)) |
dd2a1305 | 511 | reboot_cpu_id = smp_processor_id(); |
dd2a1305 EB |
512 | |
513 | /* Make certain I only run on the appropriate processor */ | |
0bc3cc03 | 514 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(reboot_cpu_id)); |
dd2a1305 | 515 | |
4d022e35 MB |
516 | /* O.K Now that I'm on the appropriate processor, |
517 | * stop all of the others. | |
1da177e4 LT |
518 | */ |
519 | smp_send_stop(); | |
4d022e35 | 520 | #endif |
1da177e4 LT |
521 | |
522 | lapic_shutdown(); | |
523 | ||
524 | #ifdef CONFIG_X86_IO_APIC | |
525 | disable_IO_APIC(); | |
526 | #endif | |
4d022e35 | 527 | |
c86c7fbc OH |
528 | #ifdef CONFIG_HPET_TIMER |
529 | hpet_disable(); | |
530 | #endif | |
dd2a1305 | 531 | |
4d022e35 MB |
532 | #ifdef CONFIG_X86_64 |
533 | pci_iommu_shutdown(); | |
534 | #endif | |
973efae2 JF |
535 | } |
536 | ||
d176720d EH |
537 | static void __machine_emergency_restart(int emergency) |
538 | { | |
539 | reboot_emergency = emergency; | |
540 | machine_ops.emergency_restart(); | |
541 | } | |
542 | ||
416e2d63 | 543 | static void native_machine_restart(char *__unused) |
dd2a1305 | 544 | { |
4d022e35 | 545 | printk("machine restart\n"); |
1da177e4 | 546 | |
4d022e35 MB |
547 | if (!reboot_force) |
548 | machine_shutdown(); | |
d176720d | 549 | __machine_emergency_restart(0); |
4a1421f8 EB |
550 | } |
551 | ||
416e2d63 | 552 | static void native_machine_halt(void) |
1da177e4 | 553 | { |
d3ec5cae IV |
554 | /* stop other cpus and apics */ |
555 | machine_shutdown(); | |
556 | ||
557 | /* stop this cpu */ | |
558 | stop_this_cpu(NULL); | |
1da177e4 LT |
559 | } |
560 | ||
416e2d63 | 561 | static void native_machine_power_off(void) |
1da177e4 | 562 | { |
6e3fbee5 | 563 | if (pm_power_off) { |
4d022e35 MB |
564 | if (!reboot_force) |
565 | machine_shutdown(); | |
1da177e4 | 566 | pm_power_off(); |
6e3fbee5 | 567 | } |
1da177e4 LT |
568 | } |
569 | ||
07f3331c | 570 | struct machine_ops machine_ops = { |
416e2d63 JB |
571 | .power_off = native_machine_power_off, |
572 | .shutdown = native_machine_shutdown, | |
573 | .emergency_restart = native_machine_emergency_restart, | |
574 | .restart = native_machine_restart, | |
ed23dc6f GC |
575 | .halt = native_machine_halt, |
576 | #ifdef CONFIG_KEXEC | |
577 | .crash_shutdown = native_machine_crash_shutdown, | |
578 | #endif | |
07f3331c | 579 | }; |
416e2d63 JB |
580 | |
581 | void machine_power_off(void) | |
582 | { | |
583 | machine_ops.power_off(); | |
584 | } | |
585 | ||
586 | void machine_shutdown(void) | |
587 | { | |
588 | machine_ops.shutdown(); | |
589 | } | |
590 | ||
591 | void machine_emergency_restart(void) | |
592 | { | |
d176720d | 593 | __machine_emergency_restart(1); |
416e2d63 JB |
594 | } |
595 | ||
596 | void machine_restart(char *cmd) | |
597 | { | |
598 | machine_ops.restart(cmd); | |
599 | } | |
600 | ||
601 | void machine_halt(void) | |
602 | { | |
603 | machine_ops.halt(); | |
604 | } | |
605 | ||
ed23dc6f GC |
606 | #ifdef CONFIG_KEXEC |
607 | void machine_crash_shutdown(struct pt_regs *regs) | |
608 | { | |
609 | machine_ops.crash_shutdown(regs); | |
610 | } | |
611 | #endif | |
2ddded21 EH |
612 | |
613 | ||
bb8dd270 | 614 | #if defined(CONFIG_SMP) |
2ddded21 EH |
615 | |
616 | /* This keeps a track of which one is crashing cpu. */ | |
617 | static int crashing_cpu; | |
618 | static nmi_shootdown_cb shootdown_callback; | |
619 | ||
620 | static atomic_t waiting_for_crash_ipi; | |
621 | ||
622 | static int crash_nmi_callback(struct notifier_block *self, | |
623 | unsigned long val, void *data) | |
624 | { | |
625 | int cpu; | |
626 | ||
627 | if (val != DIE_NMI_IPI) | |
628 | return NOTIFY_OK; | |
629 | ||
630 | cpu = raw_smp_processor_id(); | |
631 | ||
632 | /* Don't do anything if this handler is invoked on crashing cpu. | |
633 | * Otherwise, system will completely hang. Crashing cpu can get | |
634 | * an NMI if system was initially booted with nmi_watchdog parameter. | |
635 | */ | |
636 | if (cpu == crashing_cpu) | |
637 | return NOTIFY_STOP; | |
638 | local_irq_disable(); | |
639 | ||
640 | shootdown_callback(cpu, (struct die_args *)data); | |
641 | ||
642 | atomic_dec(&waiting_for_crash_ipi); | |
643 | /* Assume hlt works */ | |
644 | halt(); | |
645 | for (;;) | |
646 | cpu_relax(); | |
647 | ||
648 | return 1; | |
649 | } | |
650 | ||
651 | static void smp_send_nmi_allbutself(void) | |
652 | { | |
855caa37 | 653 | send_IPI_allbutself(NMI_VECTOR); |
2ddded21 EH |
654 | } |
655 | ||
656 | static struct notifier_block crash_nmi_nb = { | |
657 | .notifier_call = crash_nmi_callback, | |
658 | }; | |
659 | ||
bb8dd270 EH |
660 | /* Halt all other CPUs, calling the specified function on each of them |
661 | * | |
662 | * This function can be used to halt all other CPUs on crash | |
663 | * or emergency reboot time. The function passed as parameter | |
664 | * will be called inside a NMI handler on all CPUs. | |
665 | */ | |
2ddded21 EH |
666 | void nmi_shootdown_cpus(nmi_shootdown_cb callback) |
667 | { | |
668 | unsigned long msecs; | |
c415b3dc | 669 | local_irq_disable(); |
2ddded21 EH |
670 | |
671 | /* Make a note of crashing cpu. Will be used in NMI callback.*/ | |
672 | crashing_cpu = safe_smp_processor_id(); | |
673 | ||
674 | shootdown_callback = callback; | |
675 | ||
676 | atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); | |
677 | /* Would it be better to replace the trap vector here? */ | |
678 | if (register_die_notifier(&crash_nmi_nb)) | |
679 | return; /* return what? */ | |
680 | /* Ensure the new callback function is set before sending | |
681 | * out the NMI | |
682 | */ | |
683 | wmb(); | |
684 | ||
685 | smp_send_nmi_allbutself(); | |
686 | ||
687 | msecs = 1000; /* Wait at most a second for the other cpus to stop */ | |
688 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { | |
689 | mdelay(1); | |
690 | msecs--; | |
691 | } | |
692 | ||
693 | /* Leave the nmi callback set */ | |
694 | } | |
bb8dd270 EH |
695 | #else /* !CONFIG_SMP */ |
696 | void nmi_shootdown_cpus(nmi_shootdown_cb callback) | |
697 | { | |
698 | /* No other CPUs to shoot down */ | |
699 | } | |
2ddded21 | 700 | #endif |