Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995 Linus Torvalds |
1da177e4 LT |
3 | */ |
4 | ||
5 | /* | |
6 | * This file handles the architecture-dependent parts of initialization | |
7 | */ | |
8 | ||
9 | #include <linux/errno.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/mm.h> | |
13 | #include <linux/stddef.h> | |
14 | #include <linux/unistd.h> | |
15 | #include <linux/ptrace.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/user.h> | |
18 | #include <linux/a.out.h> | |
894673ee | 19 | #include <linux/screen_info.h> |
1da177e4 LT |
20 | #include <linux/ioport.h> |
21 | #include <linux/delay.h> | |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/initrd.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/bootmem.h> | |
26 | #include <linux/module.h> | |
27 | #include <asm/processor.h> | |
28 | #include <linux/console.h> | |
29 | #include <linux/seq_file.h> | |
aac04b32 | 30 | #include <linux/crash_dump.h> |
1da177e4 LT |
31 | #include <linux/root_dev.h> |
32 | #include <linux/pci.h> | |
5b83683f | 33 | #include <linux/efi.h> |
1da177e4 LT |
34 | #include <linux/acpi.h> |
35 | #include <linux/kallsyms.h> | |
36 | #include <linux/edd.h> | |
bbfceef4 | 37 | #include <linux/mmzone.h> |
5f5609df | 38 | #include <linux/kexec.h> |
95235ca2 | 39 | #include <linux/cpufreq.h> |
e9928674 | 40 | #include <linux/dmi.h> |
17a941d8 | 41 | #include <linux/dma-mapping.h> |
681558fd | 42 | #include <linux/ctype.h> |
746ef0cd | 43 | #include <linux/uaccess.h> |
bbfceef4 | 44 | |
1da177e4 LT |
45 | #include <asm/mtrr.h> |
46 | #include <asm/uaccess.h> | |
47 | #include <asm/system.h> | |
e4026440 | 48 | #include <asm/vsyscall.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | #include <asm/smp.h> | |
51 | #include <asm/msr.h> | |
52 | #include <asm/desc.h> | |
53 | #include <video/edid.h> | |
54 | #include <asm/e820.h> | |
55 | #include <asm/dma.h> | |
aaf23042 | 56 | #include <asm/gart.h> |
1da177e4 LT |
57 | #include <asm/mpspec.h> |
58 | #include <asm/mmu_context.h> | |
1da177e4 LT |
59 | #include <asm/proto.h> |
60 | #include <asm/setup.h> | |
61 | #include <asm/mach_apic.h> | |
62 | #include <asm/numa.h> | |
2bc0414e | 63 | #include <asm/sections.h> |
f2d3efed | 64 | #include <asm/dmi.h> |
00bf4098 | 65 | #include <asm/cacheflush.h> |
af7a78e9 | 66 | #include <asm/mce.h> |
eee3af4a | 67 | #include <asm/ds.h> |
df3825c5 | 68 | #include <asm/topology.h> |
1da177e4 | 69 | |
746ef0cd GOC |
70 | #ifdef CONFIG_PARAVIRT |
71 | #include <asm/paravirt.h> | |
72 | #else | |
73 | #define ARCH_SETUP | |
74 | #endif | |
75 | ||
1da177e4 LT |
76 | /* |
77 | * Machine setup.. | |
78 | */ | |
79 | ||
6c231b7b | 80 | struct cpuinfo_x86 boot_cpu_data __read_mostly; |
2ee60e17 | 81 | EXPORT_SYMBOL(boot_cpu_data); |
1da177e4 LT |
82 | |
83 | unsigned long mmu_cr4_features; | |
84 | ||
1da177e4 LT |
85 | /* Boot loader ID as an integer, for the benefit of proc_dointvec */ |
86 | int bootloader_type; | |
87 | ||
88 | unsigned long saved_video_mode; | |
89 | ||
f039b754 AK |
90 | int force_mwait __cpuinitdata; |
91 | ||
04e1ba85 | 92 | /* |
f2d3efed AK |
93 | * Early DMI memory |
94 | */ | |
95 | int dmi_alloc_index; | |
96 | char dmi_alloc_data[DMI_MAX_DATA]; | |
97 | ||
1da177e4 LT |
98 | /* |
99 | * Setup options | |
100 | */ | |
1da177e4 | 101 | struct screen_info screen_info; |
2ee60e17 | 102 | EXPORT_SYMBOL(screen_info); |
1da177e4 LT |
103 | struct sys_desc_table_struct { |
104 | unsigned short length; | |
105 | unsigned char table[0]; | |
106 | }; | |
107 | ||
108 | struct edid_info edid_info; | |
ba70710e | 109 | EXPORT_SYMBOL_GPL(edid_info); |
1da177e4 LT |
110 | |
111 | extern int root_mountflags; | |
1da177e4 | 112 | |
adf48856 | 113 | char __initdata command_line[COMMAND_LINE_SIZE]; |
1da177e4 LT |
114 | |
115 | struct resource standard_io_resources[] = { | |
116 | { .name = "dma1", .start = 0x00, .end = 0x1f, | |
117 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
118 | { .name = "pic1", .start = 0x20, .end = 0x21, | |
119 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
120 | { .name = "timer0", .start = 0x40, .end = 0x43, | |
121 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
122 | { .name = "timer1", .start = 0x50, .end = 0x53, | |
123 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
124 | { .name = "keyboard", .start = 0x60, .end = 0x6f, | |
125 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
126 | { .name = "dma page reg", .start = 0x80, .end = 0x8f, | |
127 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
128 | { .name = "pic2", .start = 0xa0, .end = 0xa1, | |
129 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
130 | { .name = "dma2", .start = 0xc0, .end = 0xdf, | |
131 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
132 | { .name = "fpu", .start = 0xf0, .end = 0xff, | |
133 | .flags = IORESOURCE_BUSY | IORESOURCE_IO } | |
134 | }; | |
135 | ||
1da177e4 LT |
136 | #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM) |
137 | ||
c9cce83d | 138 | static struct resource data_resource = { |
1da177e4 LT |
139 | .name = "Kernel data", |
140 | .start = 0, | |
141 | .end = 0, | |
142 | .flags = IORESOURCE_RAM, | |
143 | }; | |
c9cce83d | 144 | static struct resource code_resource = { |
1da177e4 LT |
145 | .name = "Kernel code", |
146 | .start = 0, | |
147 | .end = 0, | |
148 | .flags = IORESOURCE_RAM, | |
149 | }; | |
c9cce83d | 150 | static struct resource bss_resource = { |
00bf4098 BW |
151 | .name = "Kernel bss", |
152 | .start = 0, | |
153 | .end = 0, | |
154 | .flags = IORESOURCE_RAM, | |
155 | }; | |
1da177e4 | 156 | |
8c61b900 TG |
157 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c); |
158 | ||
2c8c0e6b AK |
159 | #ifdef CONFIG_PROC_VMCORE |
160 | /* elfcorehdr= specifies the location of elf core header | |
161 | * stored by the crashed kernel. This option will be passed | |
162 | * by kexec loader to the capture kernel. | |
163 | */ | |
164 | static int __init setup_elfcorehdr(char *arg) | |
681558fd | 165 | { |
2c8c0e6b AK |
166 | char *end; |
167 | if (!arg) | |
168 | return -EINVAL; | |
169 | elfcorehdr_addr = memparse(arg, &end); | |
170 | return end > arg ? 0 : -EINVAL; | |
681558fd | 171 | } |
2c8c0e6b | 172 | early_param("elfcorehdr", setup_elfcorehdr); |
e2c03888 AK |
173 | #endif |
174 | ||
2b97690f | 175 | #ifndef CONFIG_NUMA |
bbfceef4 MT |
176 | static void __init |
177 | contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn) | |
1da177e4 | 178 | { |
bbfceef4 MT |
179 | unsigned long bootmap_size, bootmap; |
180 | ||
bbfceef4 MT |
181 | bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT; |
182 | bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size); | |
183 | if (bootmap == -1L) | |
04e1ba85 | 184 | panic("Cannot find bootmem map of size %ld\n", bootmap_size); |
bbfceef4 | 185 | bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn); |
5cb248ab MG |
186 | e820_register_active_regions(0, start_pfn, end_pfn); |
187 | free_bootmem_with_active_regions(0, end_pfn); | |
bbfceef4 | 188 | reserve_bootmem(bootmap, bootmap_size); |
04e1ba85 | 189 | } |
1da177e4 LT |
190 | #endif |
191 | ||
1da177e4 LT |
192 | #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE) |
193 | struct edd edd; | |
194 | #ifdef CONFIG_EDD_MODULE | |
195 | EXPORT_SYMBOL(edd); | |
196 | #endif | |
197 | /** | |
198 | * copy_edd() - Copy the BIOS EDD information | |
199 | * from boot_params into a safe place. | |
200 | * | |
201 | */ | |
202 | static inline void copy_edd(void) | |
203 | { | |
30c82645 PA |
204 | memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer, |
205 | sizeof(edd.mbr_signature)); | |
206 | memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info)); | |
207 | edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries; | |
208 | edd.edd_info_nr = boot_params.eddbuf_entries; | |
1da177e4 LT |
209 | } |
210 | #else | |
211 | static inline void copy_edd(void) | |
212 | { | |
213 | } | |
214 | #endif | |
215 | ||
5c3391f9 BW |
216 | #ifdef CONFIG_KEXEC |
217 | static void __init reserve_crashkernel(void) | |
218 | { | |
219 | unsigned long long free_mem; | |
220 | unsigned long long crash_size, crash_base; | |
221 | int ret; | |
222 | ||
04e1ba85 TG |
223 | free_mem = |
224 | ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT; | |
5c3391f9 BW |
225 | |
226 | ret = parse_crashkernel(boot_command_line, free_mem, | |
227 | &crash_size, &crash_base); | |
228 | if (ret == 0 && crash_size) { | |
229 | if (crash_base > 0) { | |
230 | printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " | |
231 | "for crashkernel (System RAM: %ldMB)\n", | |
232 | (unsigned long)(crash_size >> 20), | |
233 | (unsigned long)(crash_base >> 20), | |
234 | (unsigned long)(free_mem >> 20)); | |
235 | crashk_res.start = crash_base; | |
236 | crashk_res.end = crash_base + crash_size - 1; | |
237 | reserve_bootmem(crash_base, crash_size); | |
238 | } else | |
239 | printk(KERN_INFO "crashkernel reservation failed - " | |
240 | "you have to specify a base address\n"); | |
241 | } | |
242 | } | |
243 | #else | |
244 | static inline void __init reserve_crashkernel(void) | |
245 | {} | |
246 | #endif | |
247 | ||
746ef0cd | 248 | /* Overridden in paravirt.c if CONFIG_PARAVIRT */ |
e3cfac84 | 249 | void __attribute__((weak)) __init memory_setup(void) |
746ef0cd GOC |
250 | { |
251 | machine_specific_memory_setup(); | |
252 | } | |
253 | ||
1da177e4 LT |
254 | void __init setup_arch(char **cmdline_p) |
255 | { | |
04e1ba85 TG |
256 | unsigned i; |
257 | ||
adf48856 | 258 | printk(KERN_INFO "Command line: %s\n", boot_command_line); |
43c85c9c | 259 | |
30c82645 PA |
260 | ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev); |
261 | screen_info = boot_params.screen_info; | |
262 | edid_info = boot_params.edid_info; | |
263 | saved_video_mode = boot_params.hdr.vid_mode; | |
264 | bootloader_type = boot_params.hdr.type_of_loader; | |
1da177e4 LT |
265 | |
266 | #ifdef CONFIG_BLK_DEV_RAM | |
30c82645 PA |
267 | rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK; |
268 | rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0); | |
269 | rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0); | |
1da177e4 | 270 | #endif |
5b83683f HY |
271 | #ifdef CONFIG_EFI |
272 | if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature, | |
273 | "EL64", 4)) | |
274 | efi_enabled = 1; | |
275 | #endif | |
746ef0cd GOC |
276 | |
277 | ARCH_SETUP | |
278 | ||
279 | memory_setup(); | |
1da177e4 LT |
280 | copy_edd(); |
281 | ||
30c82645 | 282 | if (!boot_params.hdr.root_flags) |
1da177e4 LT |
283 | root_mountflags &= ~MS_RDONLY; |
284 | init_mm.start_code = (unsigned long) &_text; | |
285 | init_mm.end_code = (unsigned long) &_etext; | |
286 | init_mm.end_data = (unsigned long) &_edata; | |
287 | init_mm.brk = (unsigned long) &_end; | |
288 | ||
e3ebadd9 LT |
289 | code_resource.start = virt_to_phys(&_text); |
290 | code_resource.end = virt_to_phys(&_etext)-1; | |
291 | data_resource.start = virt_to_phys(&_etext); | |
292 | data_resource.end = virt_to_phys(&_edata)-1; | |
00bf4098 BW |
293 | bss_resource.start = virt_to_phys(&__bss_start); |
294 | bss_resource.end = virt_to_phys(&__bss_stop)-1; | |
1da177e4 | 295 | |
1da177e4 LT |
296 | early_identify_cpu(&boot_cpu_data); |
297 | ||
adf48856 | 298 | strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); |
2c8c0e6b AK |
299 | *cmdline_p = command_line; |
300 | ||
301 | parse_early_param(); | |
302 | ||
303 | finish_e820_parsing(); | |
9ca33eb6 | 304 | |
aaf23042 YL |
305 | early_gart_iommu_check(); |
306 | ||
5cb248ab | 307 | e820_register_active_regions(0, 0, -1UL); |
1da177e4 LT |
308 | /* |
309 | * partially used pages are not usable - thus | |
310 | * we are rounding upwards: | |
311 | */ | |
312 | end_pfn = e820_end_of_ram(); | |
99fc8d42 JB |
313 | /* update e820 for memory not covered by WB MTRRs */ |
314 | mtrr_bp_init(); | |
315 | if (mtrr_trim_uncached_memory(end_pfn)) { | |
316 | e820_register_active_regions(0, 0, -1UL); | |
317 | end_pfn = e820_end_of_ram(); | |
318 | } | |
319 | ||
caff0710 | 320 | num_physpages = end_pfn; |
1da177e4 LT |
321 | |
322 | check_efer(); | |
323 | ||
324 | init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT)); | |
5b83683f HY |
325 | if (efi_enabled) |
326 | efi_init(); | |
1da177e4 | 327 | |
f2d3efed AK |
328 | dmi_scan_machine(); |
329 | ||
b02aae9c RH |
330 | io_delay_init(); |
331 | ||
71fff5e6 | 332 | #ifdef CONFIG_SMP |
df3825c5 | 333 | /* setup to use the early static init tables during kernel startup */ |
3b419089 | 334 | x86_cpu_to_apicid_early_ptr = (void *)&x86_cpu_to_apicid_init; |
e8c10ef9 | 335 | #ifdef CONFIG_NUMA |
df3825c5 | 336 | x86_cpu_to_node_map_early_ptr = (void *)&x86_cpu_to_node_map_init; |
71fff5e6 | 337 | #endif |
e8c10ef9 | 338 | x86_bios_cpu_apicid_early_ptr = (void *)&x86_bios_cpu_apicid_init; |
339 | #endif | |
71fff5e6 | 340 | |
888ba6c6 | 341 | #ifdef CONFIG_ACPI |
1da177e4 LT |
342 | /* |
343 | * Initialize the ACPI boot-time table parser (gets the RSDP and SDT). | |
344 | * Call this early for SRAT node setup. | |
345 | */ | |
346 | acpi_boot_table_init(); | |
347 | #endif | |
348 | ||
caff0710 JB |
349 | /* How many end-of-memory variables you have, grandma! */ |
350 | max_low_pfn = end_pfn; | |
351 | max_pfn = end_pfn; | |
352 | high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1; | |
353 | ||
5cb248ab MG |
354 | /* Remove active ranges so rediscovery with NUMA-awareness happens */ |
355 | remove_all_active_ranges(); | |
356 | ||
1da177e4 LT |
357 | #ifdef CONFIG_ACPI_NUMA |
358 | /* | |
359 | * Parse SRAT to discover nodes. | |
360 | */ | |
361 | acpi_numa_init(); | |
362 | #endif | |
363 | ||
2b97690f | 364 | #ifdef CONFIG_NUMA |
04e1ba85 | 365 | numa_initmem_init(0, end_pfn); |
1da177e4 | 366 | #else |
bbfceef4 | 367 | contig_initmem_init(0, end_pfn); |
1da177e4 LT |
368 | #endif |
369 | ||
75175278 | 370 | early_res_to_bootmem(); |
1da177e4 | 371 | |
673d5b43 | 372 | #ifdef CONFIG_ACPI_SLEEP |
1da177e4 | 373 | /* |
04e1ba85 | 374 | * Reserve low memory region for sleep support. |
1da177e4 | 375 | */ |
04e1ba85 TG |
376 | acpi_reserve_bootmem(); |
377 | #endif | |
5b83683f HY |
378 | |
379 | if (efi_enabled) { | |
380 | efi_map_memmap(); | |
381 | efi_reserve_bootmem(); | |
382 | } | |
383 | ||
04e1ba85 TG |
384 | /* |
385 | * Find and reserve possible boot-time SMP configuration: | |
386 | */ | |
1da177e4 | 387 | find_smp_config(); |
1da177e4 | 388 | #ifdef CONFIG_BLK_DEV_INITRD |
30c82645 PA |
389 | if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) { |
390 | unsigned long ramdisk_image = boot_params.hdr.ramdisk_image; | |
391 | unsigned long ramdisk_size = boot_params.hdr.ramdisk_size; | |
392 | unsigned long ramdisk_end = ramdisk_image + ramdisk_size; | |
393 | unsigned long end_of_mem = end_pfn << PAGE_SHIFT; | |
394 | ||
395 | if (ramdisk_end <= end_of_mem) { | |
396 | reserve_bootmem_generic(ramdisk_image, ramdisk_size); | |
397 | initrd_start = ramdisk_image + PAGE_OFFSET; | |
398 | initrd_end = initrd_start+ramdisk_size; | |
399 | } else { | |
75175278 AK |
400 | /* Assumes everything on node 0 */ |
401 | free_bootmem(ramdisk_image, ramdisk_size); | |
1da177e4 | 402 | printk(KERN_ERR "initrd extends beyond end of memory " |
30c82645 PA |
403 | "(0x%08lx > 0x%08lx)\ndisabling initrd\n", |
404 | ramdisk_end, end_of_mem); | |
1da177e4 LT |
405 | initrd_start = 0; |
406 | } | |
407 | } | |
408 | #endif | |
5c3391f9 | 409 | reserve_crashkernel(); |
1da177e4 | 410 | paging_init(); |
e4026440 | 411 | map_vsyscall(); |
1da177e4 | 412 | |
dfa4698c | 413 | early_quirks(); |
1da177e4 | 414 | |
51f62e18 AR |
415 | /* |
416 | * set this early, so we dont allocate cpu0 | |
417 | * if MADT list doesnt list BSP first | |
418 | * mpparse.c/MP_processor_info() allocates logical cpu numbers. | |
419 | */ | |
420 | cpu_set(0, cpu_present_map); | |
888ba6c6 | 421 | #ifdef CONFIG_ACPI |
1da177e4 LT |
422 | /* |
423 | * Read APIC and some other early information from ACPI tables. | |
424 | */ | |
425 | acpi_boot_init(); | |
426 | #endif | |
427 | ||
05b3cbd8 RT |
428 | init_cpu_to_node(); |
429 | ||
1da177e4 LT |
430 | /* |
431 | * get boot-time SMP configuration: | |
432 | */ | |
433 | if (smp_found_config) | |
434 | get_smp_config(); | |
435 | init_apic_mappings(); | |
3e35a0e5 | 436 | ioapic_init_mappings(); |
1da177e4 LT |
437 | |
438 | /* | |
fc986db4 | 439 | * We trust e820 completely. No explicit ROM probing in memory. |
04e1ba85 | 440 | */ |
c9cce83d | 441 | e820_reserve_resources(&code_resource, &data_resource, &bss_resource); |
e8eff5ac | 442 | e820_mark_nosave_regions(); |
1da177e4 | 443 | |
1da177e4 | 444 | /* request I/O space for devices used on all i[345]86 PCs */ |
9d0ef4fd | 445 | for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) |
1da177e4 | 446 | request_resource(&ioport_resource, &standard_io_resources[i]); |
1da177e4 | 447 | |
a1e97782 | 448 | e820_setup_gap(); |
1da177e4 | 449 | |
1da177e4 LT |
450 | #ifdef CONFIG_VT |
451 | #if defined(CONFIG_VGA_CONSOLE) | |
5b83683f HY |
452 | if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY)) |
453 | conswitchp = &vga_con; | |
1da177e4 LT |
454 | #elif defined(CONFIG_DUMMY_CONSOLE) |
455 | conswitchp = &dummy_con; | |
456 | #endif | |
457 | #endif | |
458 | } | |
459 | ||
e6982c67 | 460 | static int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
461 | { |
462 | unsigned int *v; | |
463 | ||
ebfcaa96 | 464 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
465 | return 0; |
466 | ||
467 | v = (unsigned int *) c->x86_model_id; | |
468 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
469 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
470 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
471 | c->x86_model_id[48] = 0; | |
472 | return 1; | |
473 | } | |
474 | ||
475 | ||
e6982c67 | 476 | static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
477 | { |
478 | unsigned int n, dummy, eax, ebx, ecx, edx; | |
479 | ||
ebfcaa96 | 480 | n = c->extended_cpuid_level; |
1da177e4 LT |
481 | |
482 | if (n >= 0x80000005) { | |
483 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
04e1ba85 TG |
484 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " |
485 | "D cache %dK (%d bytes/line)\n", | |
486 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
487 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
488 | /* On K8 L1 TLB is inclusive, so don't count it */ |
489 | c->x86_tlbsize = 0; | |
490 | } | |
491 | ||
492 | if (n >= 0x80000006) { | |
493 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
494 | ecx = cpuid_ecx(0x80000006); | |
495 | c->x86_cache_size = ecx >> 16; | |
496 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
497 | ||
498 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
499 | c->x86_cache_size, ecx & 0xFF); | |
500 | } | |
1da177e4 | 501 | if (n >= 0x80000008) { |
04e1ba85 | 502 | cpuid(0x80000008, &eax, &dummy, &dummy, &dummy); |
1da177e4 LT |
503 | c->x86_virt_bits = (eax >> 8) & 0xff; |
504 | c->x86_phys_bits = eax & 0xff; | |
505 | } | |
506 | } | |
507 | ||
3f098c26 AK |
508 | #ifdef CONFIG_NUMA |
509 | static int nearby_node(int apicid) | |
510 | { | |
04e1ba85 TG |
511 | int i, node; |
512 | ||
3f098c26 | 513 | for (i = apicid - 1; i >= 0; i--) { |
04e1ba85 | 514 | node = apicid_to_node[i]; |
3f098c26 AK |
515 | if (node != NUMA_NO_NODE && node_online(node)) |
516 | return node; | |
517 | } | |
518 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
04e1ba85 | 519 | node = apicid_to_node[i]; |
3f098c26 AK |
520 | if (node != NUMA_NO_NODE && node_online(node)) |
521 | return node; | |
522 | } | |
523 | return first_node(node_online_map); /* Shouldn't happen */ | |
524 | } | |
525 | #endif | |
526 | ||
63518644 AK |
527 | /* |
528 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
529 | * Assumes number of cores is a power of two. | |
530 | */ | |
531 | static void __init amd_detect_cmp(struct cpuinfo_x86 *c) | |
532 | { | |
533 | #ifdef CONFIG_SMP | |
b41e2939 | 534 | unsigned bits; |
3f098c26 | 535 | #ifdef CONFIG_NUMA |
f3fa8ebc | 536 | int cpu = smp_processor_id(); |
3f098c26 | 537 | int node = 0; |
60c1bc82 | 538 | unsigned apicid = hard_smp_processor_id(); |
3f098c26 | 539 | #endif |
a860b63c | 540 | bits = c->x86_coreid_bits; |
b41e2939 AK |
541 | |
542 | /* Low order bits define the core id (index of core in socket) */ | |
f3fa8ebc | 543 | c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1); |
b41e2939 | 544 | /* Convert the APIC ID into the socket ID */ |
f3fa8ebc | 545 | c->phys_proc_id = phys_pkg_id(bits); |
63518644 AK |
546 | |
547 | #ifdef CONFIG_NUMA | |
04e1ba85 TG |
548 | node = c->phys_proc_id; |
549 | if (apicid_to_node[apicid] != NUMA_NO_NODE) | |
550 | node = apicid_to_node[apicid]; | |
551 | if (!node_online(node)) { | |
552 | /* Two possibilities here: | |
553 | - The CPU is missing memory and no node was created. | |
554 | In that case try picking one from a nearby CPU | |
555 | - The APIC IDs differ from the HyperTransport node IDs | |
556 | which the K8 northbridge parsing fills in. | |
557 | Assume they are all increased by a constant offset, | |
558 | but in the same order as the HT nodeids. | |
559 | If that doesn't result in a usable node fall back to the | |
560 | path for the previous case. */ | |
561 | ||
92cb7612 | 562 | int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits); |
04e1ba85 TG |
563 | |
564 | if (ht_nodeid >= 0 && | |
565 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
566 | node = apicid_to_node[ht_nodeid]; | |
567 | /* Pick a nearby node */ | |
568 | if (!node_online(node)) | |
569 | node = nearby_node(apicid); | |
570 | } | |
69d81fcd | 571 | numa_set_node(cpu, node); |
3f098c26 | 572 | |
e42f9437 | 573 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
63518644 | 574 | #endif |
63518644 AK |
575 | #endif |
576 | } | |
1da177e4 | 577 | |
2b16a235 | 578 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
a860b63c YL |
579 | { |
580 | #ifdef CONFIG_SMP | |
581 | unsigned bits, ecx; | |
582 | ||
583 | /* Multi core CPU? */ | |
584 | if (c->extended_cpuid_level < 0x80000008) | |
585 | return; | |
586 | ||
587 | ecx = cpuid_ecx(0x80000008); | |
588 | ||
589 | c->x86_max_cores = (ecx & 0xff) + 1; | |
590 | ||
591 | /* CPU telling us the core id bits shift? */ | |
592 | bits = (ecx >> 12) & 0xF; | |
593 | ||
594 | /* Otherwise recompute */ | |
595 | if (bits == 0) { | |
596 | while ((1 << bits) < c->x86_max_cores) | |
597 | bits++; | |
598 | } | |
599 | ||
600 | c->x86_coreid_bits = bits; | |
601 | ||
602 | #endif | |
603 | } | |
604 | ||
fb79d22e TG |
605 | #define ENABLE_C1E_MASK 0x18000000 |
606 | #define CPUID_PROCESSOR_SIGNATURE 1 | |
607 | #define CPUID_XFAM 0x0ff00000 | |
608 | #define CPUID_XFAM_K8 0x00000000 | |
609 | #define CPUID_XFAM_10H 0x00100000 | |
610 | #define CPUID_XFAM_11H 0x00200000 | |
611 | #define CPUID_XMOD 0x000f0000 | |
612 | #define CPUID_XMOD_REV_F 0x00040000 | |
613 | ||
614 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ | |
615 | static __cpuinit int amd_apic_timer_broken(void) | |
616 | { | |
04e1ba85 TG |
617 | u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
618 | ||
fb79d22e TG |
619 | switch (eax & CPUID_XFAM) { |
620 | case CPUID_XFAM_K8: | |
621 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) | |
622 | break; | |
623 | case CPUID_XFAM_10H: | |
624 | case CPUID_XFAM_11H: | |
625 | rdmsr(MSR_K8_ENABLE_C1E, lo, hi); | |
626 | if (lo & ENABLE_C1E_MASK) | |
627 | return 1; | |
628 | break; | |
629 | default: | |
630 | /* err on the side of caution */ | |
631 | return 1; | |
632 | } | |
633 | return 0; | |
634 | } | |
635 | ||
2b16a235 AK |
636 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
637 | { | |
638 | early_init_amd_mc(c); | |
639 | ||
640 | /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */ | |
641 | if (c->x86_power & (1<<8)) | |
642 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
643 | } | |
644 | ||
ed77504b | 645 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 646 | { |
7bcd3f34 | 647 | unsigned level; |
1da177e4 | 648 | |
bc5e8fdf LT |
649 | #ifdef CONFIG_SMP |
650 | unsigned long value; | |
651 | ||
7d318d77 AK |
652 | /* |
653 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
654 | * bit 6 of msr C001_0015 | |
04e1ba85 | 655 | * |
7d318d77 AK |
656 | * Errata 63 for SH-B3 steppings |
657 | * Errata 122 for all steppings (F+ have it disabled by default) | |
658 | */ | |
659 | if (c->x86 == 15) { | |
660 | rdmsrl(MSR_K8_HWCR, value); | |
661 | value |= 1 << 6; | |
662 | wrmsrl(MSR_K8_HWCR, value); | |
663 | } | |
bc5e8fdf LT |
664 | #endif |
665 | ||
1da177e4 LT |
666 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
667 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | |
5548fecd | 668 | clear_bit(0*32+31, (unsigned long *)&c->x86_capability); |
04e1ba85 | 669 | |
7bcd3f34 AK |
670 | /* On C+ stepping K8 rep microcode works well for copy/memset */ |
671 | level = cpuid_eax(1); | |
04e1ba85 TG |
672 | if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || |
673 | level >= 0x0f58)) | |
53756d37 | 674 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
99741faa | 675 | if (c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 676 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
7bcd3f34 | 677 | |
18bd057b AK |
678 | /* Enable workaround for FXSAVE leak */ |
679 | if (c->x86 >= 6) | |
53756d37 | 680 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
18bd057b | 681 | |
e42f9437 RS |
682 | level = get_model_name(c); |
683 | if (!level) { | |
04e1ba85 | 684 | switch (c->x86) { |
1da177e4 LT |
685 | case 15: |
686 | /* Should distinguish Models here, but this is only | |
687 | a fallback anyways. */ | |
688 | strcpy(c->x86_model_id, "Hammer"); | |
04e1ba85 TG |
689 | break; |
690 | } | |
691 | } | |
1da177e4 LT |
692 | display_cacheinfo(c); |
693 | ||
faee9a5d AK |
694 | /* Multi core CPU? */ |
695 | if (c->extended_cpuid_level >= 0x80000008) | |
63518644 | 696 | amd_detect_cmp(c); |
1da177e4 | 697 | |
67cddd94 AK |
698 | if (c->extended_cpuid_level >= 0x80000006 && |
699 | (cpuid_edx(0x80000006) & 0xf000)) | |
700 | num_cache_leaves = 4; | |
701 | else | |
702 | num_cache_leaves = 3; | |
2049336f | 703 | |
0bd8acd1 | 704 | if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 705 | set_cpu_cap(c, X86_FEATURE_K8); |
0bd8acd1 | 706 | |
de421863 AK |
707 | /* MFENCE stops RDTSC speculation */ |
708 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
f039b754 | 709 | |
fb79d22e TG |
710 | if (amd_apic_timer_broken()) |
711 | disable_apic_timer = 1; | |
1da177e4 LT |
712 | } |
713 | ||
1a53905a | 714 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
715 | { |
716 | #ifdef CONFIG_SMP | |
04e1ba85 TG |
717 | u32 eax, ebx, ecx, edx; |
718 | int index_msb, core_bits; | |
94605eff SS |
719 | |
720 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
721 | ||
94605eff | 722 | |
e42f9437 | 723 | if (!cpu_has(c, X86_FEATURE_HT)) |
1da177e4 | 724 | return; |
04e1ba85 | 725 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
e42f9437 | 726 | goto out; |
1da177e4 | 727 | |
1da177e4 | 728 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
94605eff | 729 | |
1da177e4 LT |
730 | if (smp_num_siblings == 1) { |
731 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
04e1ba85 | 732 | } else if (smp_num_siblings > 1) { |
94605eff | 733 | |
1da177e4 | 734 | if (smp_num_siblings > NR_CPUS) { |
04e1ba85 TG |
735 | printk(KERN_WARNING "CPU: Unsupported number of " |
736 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
737 | smp_num_siblings = 1; |
738 | return; | |
739 | } | |
94605eff SS |
740 | |
741 | index_msb = get_count_order(smp_num_siblings); | |
f3fa8ebc | 742 | c->phys_proc_id = phys_pkg_id(index_msb); |
3dd9d514 | 743 | |
94605eff | 744 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 745 | |
04e1ba85 | 746 | index_msb = get_count_order(smp_num_siblings); |
94605eff SS |
747 | |
748 | core_bits = get_count_order(c->x86_max_cores); | |
3dd9d514 | 749 | |
f3fa8ebc | 750 | c->cpu_core_id = phys_pkg_id(index_msb) & |
94605eff | 751 | ((1 << core_bits) - 1); |
1da177e4 | 752 | } |
e42f9437 RS |
753 | out: |
754 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
04e1ba85 TG |
755 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
756 | c->phys_proc_id); | |
757 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
758 | c->cpu_core_id); | |
e42f9437 RS |
759 | } |
760 | ||
1da177e4 LT |
761 | #endif |
762 | } | |
763 | ||
3dd9d514 AK |
764 | /* |
765 | * find out the number of processor cores on the die | |
766 | */ | |
e6982c67 | 767 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 768 | { |
2bbc419f | 769 | unsigned int eax, t; |
3dd9d514 AK |
770 | |
771 | if (c->cpuid_level < 4) | |
772 | return 1; | |
773 | ||
2bbc419f | 774 | cpuid_count(4, 0, &eax, &t, &t, &t); |
3dd9d514 AK |
775 | |
776 | if (eax & 0x1f) | |
777 | return ((eax >> 26) + 1); | |
778 | else | |
779 | return 1; | |
780 | } | |
781 | ||
df0cc26b AK |
782 | static void srat_detect_node(void) |
783 | { | |
784 | #ifdef CONFIG_NUMA | |
ddea7be0 | 785 | unsigned node; |
df0cc26b | 786 | int cpu = smp_processor_id(); |
e42f9437 | 787 | int apicid = hard_smp_processor_id(); |
df0cc26b AK |
788 | |
789 | /* Don't do the funky fallback heuristics the AMD version employs | |
790 | for now. */ | |
e42f9437 | 791 | node = apicid_to_node[apicid]; |
df0cc26b | 792 | if (node == NUMA_NO_NODE) |
0d015324 | 793 | node = first_node(node_online_map); |
69d81fcd | 794 | numa_set_node(cpu, node); |
df0cc26b | 795 | |
c31fbb1a | 796 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
df0cc26b AK |
797 | #endif |
798 | } | |
799 | ||
2b16a235 AK |
800 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
801 | { | |
802 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | |
803 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
804 | set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); | |
805 | } | |
806 | ||
e6982c67 | 807 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
808 | { |
809 | /* Cache sizes */ | |
810 | unsigned n; | |
811 | ||
812 | init_intel_cacheinfo(c); | |
04e1ba85 | 813 | if (c->cpuid_level > 9) { |
0080e667 VP |
814 | unsigned eax = cpuid_eax(10); |
815 | /* Check for version and the number of counters */ | |
816 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
53756d37 | 817 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 VP |
818 | } |
819 | ||
36b2a8d5 SE |
820 | if (cpu_has_ds) { |
821 | unsigned int l1, l2; | |
822 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
ee58fad5 | 823 | if (!(l1 & (1<<11))) |
53756d37 | 824 | set_cpu_cap(c, X86_FEATURE_BTS); |
36b2a8d5 | 825 | if (!(l1 & (1<<12))) |
53756d37 | 826 | set_cpu_cap(c, X86_FEATURE_PEBS); |
36b2a8d5 SE |
827 | } |
828 | ||
eee3af4a MM |
829 | |
830 | if (cpu_has_bts) | |
831 | ds_init_intel(c); | |
832 | ||
ebfcaa96 | 833 | n = c->extended_cpuid_level; |
1da177e4 LT |
834 | if (n >= 0x80000008) { |
835 | unsigned eax = cpuid_eax(0x80000008); | |
836 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
837 | c->x86_phys_bits = eax & 0xff; | |
af9c142d SL |
838 | /* CPUID workaround for Intel 0F34 CPU */ |
839 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
840 | c->x86 == 0xF && c->x86_model == 0x3 && | |
841 | c->x86_mask == 0x4) | |
842 | c->x86_phys_bits = 36; | |
1da177e4 LT |
843 | } |
844 | ||
845 | if (c->x86 == 15) | |
846 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
39b3a791 AK |
847 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
848 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
53756d37 | 849 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
27fbe5b2 | 850 | if (c->x86 == 6) |
53756d37 | 851 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
707fa8ed | 852 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
04e1ba85 | 853 | c->x86_max_cores = intel_num_cpu_cores(c); |
df0cc26b AK |
854 | |
855 | srat_detect_node(); | |
1da177e4 LT |
856 | } |
857 | ||
672289e9 | 858 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
859 | { |
860 | char *v = c->x86_vendor_id; | |
861 | ||
862 | if (!strcmp(v, "AuthenticAMD")) | |
863 | c->x86_vendor = X86_VENDOR_AMD; | |
864 | else if (!strcmp(v, "GenuineIntel")) | |
865 | c->x86_vendor = X86_VENDOR_INTEL; | |
866 | else | |
867 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
868 | } | |
869 | ||
870 | struct cpu_model_info { | |
871 | int vendor; | |
872 | int family; | |
873 | char *model_names[16]; | |
874 | }; | |
875 | ||
876 | /* Do some early cpuid on the boot CPU to get some parameter that are | |
877 | needed before check_bugs. Everything advanced is in identify_cpu | |
878 | below. */ | |
8c61b900 | 879 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 | 880 | { |
a860b63c | 881 | u32 tfms, xlvl; |
1da177e4 LT |
882 | |
883 | c->loops_per_jiffy = loops_per_jiffy; | |
884 | c->x86_cache_size = -1; | |
885 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
886 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
887 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
888 | c->x86_model_id[0] = '\0'; /* Unset */ | |
889 | c->x86_clflush_size = 64; | |
890 | c->x86_cache_alignment = c->x86_clflush_size; | |
94605eff | 891 | c->x86_max_cores = 1; |
a860b63c | 892 | c->x86_coreid_bits = 0; |
ebfcaa96 | 893 | c->extended_cpuid_level = 0; |
1da177e4 LT |
894 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
895 | ||
896 | /* Get vendor name */ | |
897 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
898 | (unsigned int *)&c->x86_vendor_id[0], | |
899 | (unsigned int *)&c->x86_vendor_id[8], | |
900 | (unsigned int *)&c->x86_vendor_id[4]); | |
04e1ba85 | 901 | |
1da177e4 LT |
902 | get_cpu_vendor(c); |
903 | ||
904 | /* Initialize the standard set of capabilities */ | |
905 | /* Note that the vendor-specific code below might override */ | |
906 | ||
907 | /* Intel-defined flags: level 0x00000001 */ | |
908 | if (c->cpuid_level >= 0x00000001) { | |
909 | __u32 misc; | |
910 | cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], | |
911 | &c->x86_capability[0]); | |
912 | c->x86 = (tfms >> 8) & 0xf; | |
913 | c->x86_model = (tfms >> 4) & 0xf; | |
914 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 915 | if (c->x86 == 0xf) |
1da177e4 | 916 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 917 | if (c->x86 >= 0x6) |
1da177e4 | 918 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
04e1ba85 | 919 | if (c->x86_capability[0] & (1<<19)) |
1da177e4 | 920 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
1da177e4 LT |
921 | } else { |
922 | /* Have CPUID level 0 only - unheard of */ | |
923 | c->x86 = 4; | |
924 | } | |
a158608b AK |
925 | |
926 | #ifdef CONFIG_SMP | |
f3fa8ebc | 927 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
a158608b | 928 | #endif |
1da177e4 LT |
929 | /* AMD-defined flags: level 0x80000001 */ |
930 | xlvl = cpuid_eax(0x80000000); | |
ebfcaa96 | 931 | c->extended_cpuid_level = xlvl; |
1da177e4 LT |
932 | if ((xlvl & 0xffff0000) == 0x80000000) { |
933 | if (xlvl >= 0x80000001) { | |
934 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
5b7abc6f | 935 | c->x86_capability[6] = cpuid_ecx(0x80000001); |
1da177e4 LT |
936 | } |
937 | if (xlvl >= 0x80000004) | |
938 | get_model_name(c); /* Default name */ | |
939 | } | |
940 | ||
941 | /* Transmeta-defined flags: level 0x80860001 */ | |
942 | xlvl = cpuid_eax(0x80860000); | |
943 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
944 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
945 | if (xlvl >= 0x80860001) | |
946 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
947 | } | |
948 | ||
9566e91d AH |
949 | c->extended_cpuid_level = cpuid_eax(0x80000000); |
950 | if (c->extended_cpuid_level >= 0x80000007) | |
951 | c->x86_power = cpuid_edx(0x80000007); | |
952 | ||
a860b63c YL |
953 | switch (c->x86_vendor) { |
954 | case X86_VENDOR_AMD: | |
955 | early_init_amd(c); | |
956 | break; | |
957 | } | |
958 | ||
959 | } | |
960 | ||
961 | /* | |
962 | * This does the hard work of actually picking apart the CPU stuff... | |
963 | */ | |
964 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) | |
965 | { | |
966 | int i; | |
967 | ||
968 | early_identify_cpu(c); | |
969 | ||
1d67953f VP |
970 | init_scattered_cpuid_features(c); |
971 | ||
1e9f28fa SS |
972 | c->apicid = phys_pkg_id(0); |
973 | ||
1da177e4 LT |
974 | /* |
975 | * Vendor-specific initialization. In this section we | |
976 | * canonicalize the feature flags, meaning if there are | |
977 | * features a certain CPU supports which CPUID doesn't | |
978 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
979 | * we handle them here. | |
980 | * | |
981 | * At the end of this section, c->x86_capability better | |
982 | * indicate the features this CPU genuinely supports! | |
983 | */ | |
984 | switch (c->x86_vendor) { | |
985 | case X86_VENDOR_AMD: | |
986 | init_amd(c); | |
987 | break; | |
988 | ||
989 | case X86_VENDOR_INTEL: | |
990 | init_intel(c); | |
991 | break; | |
992 | ||
993 | case X86_VENDOR_UNKNOWN: | |
994 | default: | |
995 | display_cacheinfo(c); | |
996 | break; | |
997 | } | |
998 | ||
999 | select_idle_routine(c); | |
04e1ba85 | 1000 | detect_ht(c); |
1da177e4 LT |
1001 | |
1002 | /* | |
1003 | * On SMP, boot_cpu_data holds the common feature set between | |
1004 | * all CPUs; so make sure that we indicate which features are | |
1005 | * common between the CPUs. The first time this routine gets | |
1006 | * executed, c == &boot_cpu_data. | |
1007 | */ | |
1008 | if (c != &boot_cpu_data) { | |
1009 | /* AND the already accumulated flags with these */ | |
04e1ba85 | 1010 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
1011 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
1012 | } | |
1013 | ||
1014 | #ifdef CONFIG_X86_MCE | |
1015 | mcheck_init(c); | |
1016 | #endif | |
8bd99481 | 1017 | if (c != &boot_cpu_data) |
3b520b23 | 1018 | mtrr_ap_init(); |
1da177e4 | 1019 | #ifdef CONFIG_NUMA |
3019e8eb | 1020 | numa_add_cpu(smp_processor_id()); |
1da177e4 | 1021 | #endif |
2b16a235 | 1022 | |
2b16a235 AK |
1023 | switch (c->x86_vendor) { |
1024 | case X86_VENDOR_AMD: | |
1025 | early_init_amd(c); | |
1026 | break; | |
1027 | case X86_VENDOR_INTEL: | |
1028 | early_init_intel(c); | |
1029 | break; | |
1030 | } | |
1da177e4 | 1031 | } |
1da177e4 | 1032 | |
e6982c67 | 1033 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
1034 | { |
1035 | if (c->x86_model_id[0]) | |
04e1ba85 | 1036 | printk(KERN_INFO "%s", c->x86_model_id); |
1da177e4 | 1037 | |
04e1ba85 TG |
1038 | if (c->x86_mask || c->cpuid_level >= 0) |
1039 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
1da177e4 | 1040 | else |
04e1ba85 | 1041 | printk(KERN_CONT "\n"); |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | /* | |
1045 | * Get CPU information for use by the procfs. | |
1046 | */ | |
1047 | ||
1048 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1049 | { | |
1050 | struct cpuinfo_x86 *c = v; | |
04e1ba85 | 1051 | int cpu = 0, i; |
1da177e4 | 1052 | |
04e1ba85 | 1053 | /* |
1da177e4 LT |
1054 | * These flag bits must match the definitions in <asm/cpufeature.h>. |
1055 | * NULL means this bit is undefined or reserved; either way it doesn't | |
1056 | * have meaning as far as Linux is concerned. Note that it's important | |
1057 | * to realize there is a difference between this table and CPUID -- if | |
1058 | * applications want to get the raw CPUID data, they should access | |
1059 | * /dev/cpu/<cpu_nr>/cpuid instead. | |
1060 | */ | |
121d7bf5 | 1061 | static const char *const x86_cap_flags[] = { |
1da177e4 | 1062 | /* Intel-defined */ |
04e1ba85 TG |
1063 | "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", |
1064 | "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov", | |
1065 | "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx", | |
1066 | "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe", | |
1da177e4 LT |
1067 | |
1068 | /* AMD-defined */ | |
3c3b73b6 | 1069 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
1da177e4 LT |
1070 | NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL, |
1071 | NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL, | |
f790cd30 AK |
1072 | NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", |
1073 | "3dnowext", "3dnow", | |
1da177e4 LT |
1074 | |
1075 | /* Transmeta-defined */ | |
1076 | "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL, | |
1077 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1078 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1079 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1080 | ||
1081 | /* Other (Linux-defined) */ | |
ec481536 PA |
1082 | "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", |
1083 | NULL, NULL, NULL, NULL, | |
1084 | "constant_tsc", "up", NULL, "arch_perfmon", | |
1085 | "pebs", "bts", NULL, "sync_rdtsc", | |
1086 | "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1da177e4 LT |
1087 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
1088 | ||
1089 | /* Intel-defined (#2) */ | |
9d95dd84 | 1090 | "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est", |
dcf10307 | 1091 | "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL, |
e1054b39 | 1092 | NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt", |
1da177e4 LT |
1093 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
1094 | ||
5b7abc6f PA |
1095 | /* VIA/Cyrix/Centaur-defined */ |
1096 | NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en", | |
ec481536 | 1097 | "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL, |
5b7abc6f PA |
1098 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
1099 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1100 | ||
1da177e4 | 1101 | /* AMD-defined (#2) */ |
e1054b39 PA |
1102 | "lahf_lm", "cmp_legacy", "svm", "extapic", |
1103 | "cr8_legacy", "abm", "sse4a", "misalignsse", | |
1104 | "3dnowprefetch", "osvw", "ibs", "sse5", | |
1105 | "skinit", "wdt", NULL, NULL, | |
1da177e4 | 1106 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
5b7abc6f | 1107 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
1d67953f VP |
1108 | |
1109 | /* Auxiliary (Linux-defined) */ | |
1110 | "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1111 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1112 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1113 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
1da177e4 | 1114 | }; |
121d7bf5 | 1115 | static const char *const x86_power_flags[] = { |
1da177e4 LT |
1116 | "ts", /* temperature sensor */ |
1117 | "fid", /* frequency id control */ | |
1118 | "vid", /* voltage id control */ | |
1119 | "ttp", /* thermal trip */ | |
1120 | "tm", | |
3f98bc49 | 1121 | "stc", |
f790cd30 AK |
1122 | "100mhzsteps", |
1123 | "hwpstate", | |
d824395c JR |
1124 | "", /* tsc invariant mapped to constant_tsc */ |
1125 | /* nothing */ | |
1da177e4 LT |
1126 | }; |
1127 | ||
1128 | ||
1129 | #ifdef CONFIG_SMP | |
92cb7612 | 1130 | cpu = c->cpu_index; |
1da177e4 LT |
1131 | #endif |
1132 | ||
04e1ba85 TG |
1133 | seq_printf(m, "processor\t: %u\n" |
1134 | "vendor_id\t: %s\n" | |
1135 | "cpu family\t: %d\n" | |
1136 | "model\t\t: %d\n" | |
1137 | "model name\t: %s\n", | |
1138 | (unsigned)cpu, | |
1139 | c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown", | |
1140 | c->x86, | |
1141 | (int)c->x86_model, | |
1142 | c->x86_model_id[0] ? c->x86_model_id : "unknown"); | |
1143 | ||
1da177e4 LT |
1144 | if (c->x86_mask || c->cpuid_level >= 0) |
1145 | seq_printf(m, "stepping\t: %d\n", c->x86_mask); | |
1146 | else | |
1147 | seq_printf(m, "stepping\t: unknown\n"); | |
04e1ba85 TG |
1148 | |
1149 | if (cpu_has(c, X86_FEATURE_TSC)) { | |
92cb7612 | 1150 | unsigned int freq = cpufreq_quick_get((unsigned)cpu); |
04e1ba85 | 1151 | |
95235ca2 VP |
1152 | if (!freq) |
1153 | freq = cpu_khz; | |
1da177e4 | 1154 | seq_printf(m, "cpu MHz\t\t: %u.%03u\n", |
04e1ba85 | 1155 | freq / 1000, (freq % 1000)); |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | /* Cache size */ | |
04e1ba85 | 1159 | if (c->x86_cache_size >= 0) |
1da177e4 | 1160 | seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size); |
04e1ba85 | 1161 | |
1da177e4 | 1162 | #ifdef CONFIG_SMP |
94605eff | 1163 | if (smp_num_siblings * c->x86_max_cores > 1) { |
f3fa8ebc | 1164 | seq_printf(m, "physical id\t: %d\n", c->phys_proc_id); |
08357611 MT |
1165 | seq_printf(m, "siblings\t: %d\n", |
1166 | cpus_weight(per_cpu(cpu_core_map, cpu))); | |
f3fa8ebc | 1167 | seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id); |
94605eff | 1168 | seq_printf(m, "cpu cores\t: %d\n", c->booted_cores); |
db468681 | 1169 | } |
04e1ba85 | 1170 | #endif |
1da177e4 LT |
1171 | |
1172 | seq_printf(m, | |
04e1ba85 TG |
1173 | "fpu\t\t: yes\n" |
1174 | "fpu_exception\t: yes\n" | |
1175 | "cpuid level\t: %d\n" | |
1176 | "wp\t\t: yes\n" | |
1177 | "flags\t\t:", | |
1da177e4 LT |
1178 | c->cpuid_level); |
1179 | ||
04e1ba85 TG |
1180 | for (i = 0; i < 32*NCAPINTS; i++) |
1181 | if (cpu_has(c, i) && x86_cap_flags[i] != NULL) | |
1182 | seq_printf(m, " %s", x86_cap_flags[i]); | |
1183 | ||
1da177e4 LT |
1184 | seq_printf(m, "\nbogomips\t: %lu.%02lu\n", |
1185 | c->loops_per_jiffy/(500000/HZ), | |
1186 | (c->loops_per_jiffy/(5000/HZ)) % 100); | |
1187 | ||
04e1ba85 | 1188 | if (c->x86_tlbsize > 0) |
1da177e4 LT |
1189 | seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize); |
1190 | seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size); | |
1191 | seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); | |
1192 | ||
04e1ba85 | 1193 | seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", |
1da177e4 LT |
1194 | c->x86_phys_bits, c->x86_virt_bits); |
1195 | ||
1196 | seq_printf(m, "power management:"); | |
04e1ba85 TG |
1197 | for (i = 0; i < 32; i++) { |
1198 | if (c->x86_power & (1 << i)) { | |
1199 | if (i < ARRAY_SIZE(x86_power_flags) && | |
1200 | x86_power_flags[i]) | |
1201 | seq_printf(m, "%s%s", | |
1202 | x86_power_flags[i][0]?" ":"", | |
1203 | x86_power_flags[i]); | |
1204 | else | |
1205 | seq_printf(m, " [%d]", i); | |
1206 | } | |
1da177e4 | 1207 | } |
1da177e4 | 1208 | |
d31ddaa1 | 1209 | seq_printf(m, "\n\n"); |
1da177e4 LT |
1210 | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1215 | { | |
92cb7612 | 1216 | if (*pos == 0) /* just in case, cpu 0 is not the first */ |
c0c52d28 AH |
1217 | *pos = first_cpu(cpu_online_map); |
1218 | if ((*pos) < NR_CPUS && cpu_online(*pos)) | |
92cb7612 MT |
1219 | return &cpu_data(*pos); |
1220 | return NULL; | |
1da177e4 LT |
1221 | } |
1222 | ||
1223 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1224 | { | |
c0c52d28 | 1225 | *pos = next_cpu(*pos, cpu_online_map); |
1da177e4 LT |
1226 | return c_start(m, pos); |
1227 | } | |
1228 | ||
1229 | static void c_stop(struct seq_file *m, void *v) | |
1230 | { | |
1231 | } | |
1232 | ||
1233 | struct seq_operations cpuinfo_op = { | |
04e1ba85 | 1234 | .start = c_start, |
1da177e4 LT |
1235 | .next = c_next, |
1236 | .stop = c_stop, | |
1237 | .show = show_cpuinfo, | |
1238 | }; |