Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> |
569712b2 | 72 | #include <asm/setup.h> |
bdbcdd48 | 73 | #include <asm/uv/uv.h> |
cb3c8b90 | 74 | #include <linux/mc146818rtc.h> |
b81bb373 | 75 | #include <asm/i8259.h> |
48927bbb | 76 | #include <asm/realmode.h> |
646e29a1 | 77 | #include <asm/misc.h> |
48927bbb | 78 | |
a355352b GC |
79 | /* Number of siblings per CPU package */ |
80 | int smp_num_siblings = 1; | |
81 | EXPORT_SYMBOL(smp_num_siblings); | |
82 | ||
83 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 85 | |
a355352b | 86 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
93 | ||
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 95 | |
a355352b | 96 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 99 | |
2b6163bf | 100 | atomic_t init_deasserted; |
cb3c8b90 | 101 | |
f77aa308 TG |
102 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
103 | { | |
104 | unsigned long flags; | |
105 | ||
106 | spin_lock_irqsave(&rtc_lock, flags); | |
107 | CMOS_WRITE(0xa, 0xf); | |
108 | spin_unlock_irqrestore(&rtc_lock, flags); | |
109 | local_flush_tlb(); | |
110 | pr_debug("1.\n"); | |
111 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
112 | start_eip >> 4; | |
113 | pr_debug("2.\n"); | |
114 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
115 | start_eip & 0xf; | |
116 | pr_debug("3.\n"); | |
117 | } | |
118 | ||
119 | static inline void smpboot_restore_warm_reset_vector(void) | |
120 | { | |
121 | unsigned long flags; | |
122 | ||
123 | /* | |
124 | * Install writable page 0 entry to set BIOS data area. | |
125 | */ | |
126 | local_flush_tlb(); | |
127 | ||
128 | /* | |
129 | * Paranoid: Set warm reset code and vector here back | |
130 | * to default values. | |
131 | */ | |
132 | spin_lock_irqsave(&rtc_lock, flags); | |
133 | CMOS_WRITE(0, 0xf); | |
134 | spin_unlock_irqrestore(&rtc_lock, flags); | |
135 | ||
136 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
137 | } | |
138 | ||
cb3c8b90 | 139 | /* |
30106c17 FY |
140 | * Report back to the Boot Processor during boot time or to the caller processor |
141 | * during CPU online. | |
cb3c8b90 | 142 | */ |
148f9bb8 | 143 | static void smp_callin(void) |
cb3c8b90 GOC |
144 | { |
145 | int cpuid, phys_id; | |
cb3c8b90 GOC |
146 | |
147 | /* | |
148 | * If waken up by an INIT in an 82489DX configuration | |
149 | * we may get here before an INIT-deassert IPI reaches | |
150 | * our local APIC. We have to wait for the IPI or we'll | |
151 | * lock up on an APIC access. | |
e1c467e6 FY |
152 | * |
153 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 154 | */ |
e1c467e6 | 155 | cpuid = smp_processor_id(); |
465822cf DR |
156 | if (apic->wait_for_init_deassert && cpuid) |
157 | while (!atomic_read(&init_deasserted)) | |
158 | cpu_relax(); | |
cb3c8b90 GOC |
159 | |
160 | /* | |
161 | * (This works even if the APIC is not enabled.) | |
162 | */ | |
4c9961d5 | 163 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
164 | |
165 | /* | |
166 | * the boot CPU has finished the init stage and is spinning | |
167 | * on callin_map until we finish. We are free to set up this | |
168 | * CPU, first the APIC. (this is probably redundant on most | |
169 | * boards) | |
170 | */ | |
05f7e46d | 171 | apic_ap_setup(); |
cb3c8b90 | 172 | |
9d133e5d SS |
173 | /* |
174 | * Need to setup vector mappings before we enable interrupts. | |
175 | */ | |
36e9e1ea | 176 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
177 | |
178 | /* | |
179 | * Save our processor parameters. Note: this information | |
180 | * is needed for clock calibration. | |
181 | */ | |
182 | smp_store_cpu_info(cpuid); | |
183 | ||
cb3c8b90 GOC |
184 | /* |
185 | * Get our bogomips. | |
b565201c JS |
186 | * Update loops_per_jiffy in cpu_data. Previous call to |
187 | * smp_store_cpu_info() stored a value that is close but not as | |
188 | * accurate as the value just calculated. | |
cb3c8b90 | 189 | */ |
cb3c8b90 | 190 | calibrate_delay(); |
b565201c | 191 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 192 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 193 | |
5ef428c4 AK |
194 | /* |
195 | * This must be done before setting cpu_online_mask | |
196 | * or calling notify_cpu_starting. | |
197 | */ | |
198 | set_cpu_sibling_map(raw_smp_processor_id()); | |
199 | wmb(); | |
200 | ||
85257024 PZ |
201 | notify_cpu_starting(cpuid); |
202 | ||
cb3c8b90 GOC |
203 | /* |
204 | * Allow the master to continue. | |
205 | */ | |
c2d1cec1 | 206 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
207 | } |
208 | ||
e1c467e6 FY |
209 | static int cpu0_logical_apicid; |
210 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
211 | /* |
212 | * Activate a secondary processor. | |
213 | */ | |
148f9bb8 | 214 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
215 | { |
216 | /* | |
217 | * Don't put *anything* before cpu_init(), SMP booting is too | |
218 | * fragile that we want to limit the things done here to the | |
219 | * most necessary things. | |
220 | */ | |
b40827fa | 221 | cpu_init(); |
df156f90 | 222 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
223 | preempt_disable(); |
224 | smp_callin(); | |
fd89a137 | 225 | |
e1c467e6 FY |
226 | enable_start_cpu0 = 0; |
227 | ||
fd89a137 | 228 | #ifdef CONFIG_X86_32 |
b40827fa | 229 | /* switch away from the initial page table */ |
fd89a137 JR |
230 | load_cr3(swapper_pg_dir); |
231 | __flush_tlb_all(); | |
232 | #endif | |
233 | ||
bbc2ff6a GOC |
234 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
235 | barrier(); | |
236 | /* | |
237 | * Check TSC synchronization with the BP: | |
238 | */ | |
239 | check_tsc_sync_target(); | |
240 | ||
3891a04a PA |
241 | /* |
242 | * Enable the espfix hack for this CPU | |
243 | */ | |
197725de | 244 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a PA |
245 | init_espfix_ap(); |
246 | #endif | |
247 | ||
bbc2ff6a | 248 | /* |
d388e5fd EB |
249 | * We need to hold vector_lock so there the set of online cpus |
250 | * does not change while we are assigning vectors to cpus. Holding | |
251 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 252 | */ |
d388e5fd | 253 | lock_vector_lock(); |
c2d1cec1 | 254 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 255 | unlock_vector_lock(); |
2a442c9c | 256 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 257 | x86_platform.nmi_init(); |
bbc2ff6a | 258 | |
0cefa5b9 MS |
259 | /* enable local interrupts */ |
260 | local_irq_enable(); | |
261 | ||
35f720c5 JP |
262 | /* to prevent fake stack check failure in clock setup */ |
263 | boot_init_stack_canary(); | |
0cefa5b9 | 264 | |
736decac | 265 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
266 | |
267 | wmb(); | |
7d1a9417 | 268 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
269 | } |
270 | ||
30106c17 FY |
271 | void __init smp_store_boot_cpu_info(void) |
272 | { | |
273 | int id = 0; /* CPU 0 */ | |
274 | struct cpuinfo_x86 *c = &cpu_data(id); | |
275 | ||
276 | *c = boot_cpu_data; | |
277 | c->cpu_index = id; | |
278 | } | |
279 | ||
1d89a7f0 GOC |
280 | /* |
281 | * The bootstrap kernel entry code has set these up. Save them for | |
282 | * a given CPU | |
283 | */ | |
148f9bb8 | 284 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
285 | { |
286 | struct cpuinfo_x86 *c = &cpu_data(id); | |
287 | ||
b3d7336d | 288 | *c = boot_cpu_data; |
1d89a7f0 | 289 | c->cpu_index = id; |
30106c17 FY |
290 | /* |
291 | * During boot time, CPU0 has this setup already. Save the info when | |
292 | * bringing up AP or offlined CPU0. | |
293 | */ | |
294 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
295 | } |
296 | ||
cebf15eb DH |
297 | static bool |
298 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
299 | { | |
300 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
301 | ||
302 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
303 | } | |
304 | ||
148f9bb8 | 305 | static bool |
316ad248 | 306 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 307 | { |
316ad248 PZ |
308 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
309 | ||
cebf15eb | 310 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
311 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
312 | "[node: %d != %d]. Ignoring dependency.\n", | |
313 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
314 | } | |
315 | ||
7d79a7bd | 316 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 317 | do { \ |
7d79a7bd BG |
318 | cpumask_set_cpu((c1), mfunc(c2)); \ |
319 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
320 | } while (0) |
321 | ||
148f9bb8 | 322 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 323 | { |
193f3fcb | 324 | if (cpu_has_topoext) { |
316ad248 PZ |
325 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
326 | ||
327 | if (c->phys_proc_id == o->phys_proc_id && | |
328 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
329 | c->compute_unit_id == o->compute_unit_id) | |
330 | return topology_sane(c, o, "smt"); | |
331 | ||
332 | } else if (c->phys_proc_id == o->phys_proc_id && | |
333 | c->cpu_core_id == o->cpu_core_id) { | |
334 | return topology_sane(c, o, "smt"); | |
335 | } | |
336 | ||
337 | return false; | |
338 | } | |
339 | ||
148f9bb8 | 340 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
341 | { |
342 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
343 | ||
344 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
345 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
346 | return topology_sane(c, o, "llc"); | |
347 | ||
348 | return false; | |
d4fbe4f0 AH |
349 | } |
350 | ||
cebf15eb DH |
351 | /* |
352 | * Unlike the other levels, we do not enforce keeping a | |
353 | * multicore group inside a NUMA node. If this happens, we will | |
354 | * discard the MC level of the topology later. | |
355 | */ | |
356 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 357 | { |
cebf15eb DH |
358 | if (c->phys_proc_id == o->phys_proc_id) |
359 | return true; | |
316ad248 PZ |
360 | return false; |
361 | } | |
1d89a7f0 | 362 | |
cebf15eb DH |
363 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
364 | #ifdef CONFIG_SCHED_SMT | |
365 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
366 | #endif | |
367 | #ifdef CONFIG_SCHED_MC | |
368 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
369 | #endif | |
370 | { NULL, }, | |
371 | }; | |
372 | /* | |
373 | * set_sched_topology() sets the topology internal to a CPU. The | |
374 | * NUMA topologies are layered on top of it to build the full | |
375 | * system topology. | |
376 | * | |
377 | * If NUMA nodes are observed to occur within a CPU package, this | |
378 | * function should be called. It forces the sched domain code to | |
379 | * only use the SMT level for the CPU portion of the topology. | |
380 | * This essentially falls back to relying on NUMA information | |
381 | * from the SRAT table to describe the entire system topology | |
382 | * (except for hyperthreads). | |
383 | */ | |
384 | static void primarily_use_numa_for_topology(void) | |
385 | { | |
386 | set_sched_topology(numa_inside_package_topology); | |
387 | } | |
388 | ||
148f9bb8 | 389 | void set_cpu_sibling_map(int cpu) |
768d9505 | 390 | { |
316ad248 | 391 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 392 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 393 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
394 | struct cpuinfo_x86 *o; |
395 | int i; | |
768d9505 | 396 | |
c2d1cec1 | 397 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 398 | |
b0bc225d | 399 | if (!has_mp) { |
7d79a7bd | 400 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 401 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 402 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
403 | c->booted_cores = 1; |
404 | return; | |
405 | } | |
406 | ||
c2d1cec1 | 407 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
408 | o = &cpu_data(i); |
409 | ||
410 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 411 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 412 | |
b0bc225d | 413 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 414 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 415 | |
ceb1cbac KB |
416 | } |
417 | ||
418 | /* | |
419 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 420 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
421 | */ |
422 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
423 | o = &cpu_data(i); | |
424 | ||
cebf15eb | 425 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 426 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 427 | |
768d9505 GC |
428 | /* |
429 | * Does this new cpu bringup a new core? | |
430 | */ | |
7d79a7bd BG |
431 | if (cpumask_weight( |
432 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
433 | /* |
434 | * for each core in package, increment | |
435 | * the booted_cores for this new cpu | |
436 | */ | |
7d79a7bd BG |
437 | if (cpumask_first( |
438 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
439 | c->booted_cores++; |
440 | /* | |
441 | * increment the core count for all | |
442 | * the other cpus in this package | |
443 | */ | |
444 | if (i != cpu) | |
445 | cpu_data(i).booted_cores++; | |
446 | } else if (i != cpu && !c->booted_cores) | |
447 | c->booted_cores = cpu_data(i).booted_cores; | |
448 | } | |
728e5653 | 449 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 450 | primarily_use_numa_for_topology(); |
768d9505 GC |
451 | } |
452 | } | |
453 | ||
70708a18 | 454 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 455 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 456 | { |
9f646389 | 457 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
458 | } |
459 | ||
a4928cff | 460 | static void impress_friends(void) |
904541e2 GOC |
461 | { |
462 | int cpu; | |
463 | unsigned long bogosum = 0; | |
464 | /* | |
465 | * Allow the user to impress friends. | |
466 | */ | |
c767a54b | 467 | pr_debug("Before bogomips\n"); |
904541e2 | 468 | for_each_possible_cpu(cpu) |
c2d1cec1 | 469 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 470 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 471 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 472 | num_online_cpus(), |
904541e2 GOC |
473 | bogosum/(500000/HZ), |
474 | (bogosum/(5000/HZ))%100); | |
475 | ||
c767a54b | 476 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
477 | } |
478 | ||
569712b2 | 479 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
480 | { |
481 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 482 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
483 | int timeout; |
484 | u32 status; | |
485 | ||
c767a54b | 486 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
487 | |
488 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 489 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
490 | |
491 | /* | |
492 | * Wait for idle. | |
493 | */ | |
494 | status = safe_apic_wait_icr_idle(); | |
495 | if (status) | |
c767a54b | 496 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 497 | |
1b374e4d | 498 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
499 | |
500 | timeout = 0; | |
501 | do { | |
502 | udelay(100); | |
503 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
504 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
505 | ||
506 | switch (status) { | |
507 | case APIC_ICR_RR_VALID: | |
508 | status = apic_read(APIC_RRR); | |
c767a54b | 509 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
510 | break; |
511 | default: | |
c767a54b | 512 | pr_cont("failed\n"); |
cb3c8b90 GOC |
513 | } |
514 | } | |
515 | } | |
516 | ||
d68921f9 LB |
517 | /* |
518 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
519 | * that there should be a 10ms delay between the BSP asserting INIT | |
520 | * and de-asserting INIT, when starting a remote processor. | |
521 | * But that slows boot and resume on modern processors, which include | |
522 | * many cores and don't require that delay. | |
523 | * | |
524 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 525 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
526 | */ |
527 | #define UDELAY_10MS_DEFAULT 10000 | |
528 | ||
529 | static unsigned int init_udelay = UDELAY_10MS_DEFAULT; | |
530 | ||
531 | static int __init cpu_init_udelay(char *str) | |
532 | { | |
533 | get_option(&str, &init_udelay); | |
534 | ||
535 | return 0; | |
536 | } | |
537 | early_param("cpu_init_udelay", cpu_init_udelay); | |
538 | ||
1a744cb3 LB |
539 | static void __init smp_quirk_init_udelay(void) |
540 | { | |
541 | /* if cmdline changed it from default, leave it alone */ | |
542 | if (init_udelay != UDELAY_10MS_DEFAULT) | |
543 | return; | |
544 | ||
545 | /* if modern processor, use no delay */ | |
546 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
547 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) | |
548 | init_udelay = 0; | |
549 | } | |
550 | ||
cb3c8b90 GOC |
551 | /* |
552 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
553 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
554 | * won't ... remember to clear down the APIC, etc later. | |
555 | */ | |
148f9bb8 | 556 | int |
e1c467e6 | 557 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
558 | { |
559 | unsigned long send_status, accept_status = 0; | |
560 | int maxlvt; | |
561 | ||
562 | /* Target chip */ | |
cb3c8b90 GOC |
563 | /* Boot on the stack */ |
564 | /* Kick the second */ | |
e1c467e6 | 565 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 566 | |
cfc1b9a6 | 567 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
568 | send_status = safe_apic_wait_icr_idle(); |
569 | ||
570 | /* | |
571 | * Give the other CPU some time to accept the IPI. | |
572 | */ | |
573 | udelay(200); | |
569712b2 | 574 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
575 | maxlvt = lapic_get_maxlvt(); |
576 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
577 | apic_write(APIC_ESR, 0); | |
578 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
579 | } | |
c767a54b | 580 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
581 | |
582 | if (send_status) | |
c767a54b | 583 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 584 | if (accept_status) |
c767a54b | 585 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
586 | |
587 | return (send_status | accept_status); | |
588 | } | |
cb3c8b90 | 589 | |
148f9bb8 | 590 | static int |
569712b2 | 591 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 592 | { |
f5d6a52f | 593 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
594 | int maxlvt, num_starts, j; |
595 | ||
593f4a78 MR |
596 | maxlvt = lapic_get_maxlvt(); |
597 | ||
cb3c8b90 GOC |
598 | /* |
599 | * Be paranoid about clearing APIC errors. | |
600 | */ | |
601 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
602 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
603 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
604 | apic_read(APIC_ESR); |
605 | } | |
606 | ||
c767a54b | 607 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
608 | |
609 | /* | |
610 | * Turn INIT on target chip | |
611 | */ | |
cb3c8b90 GOC |
612 | /* |
613 | * Send IPI | |
614 | */ | |
1b374e4d SS |
615 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
616 | phys_apicid); | |
cb3c8b90 | 617 | |
cfc1b9a6 | 618 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
619 | send_status = safe_apic_wait_icr_idle(); |
620 | ||
7cb68598 | 621 | udelay(init_udelay); |
cb3c8b90 | 622 | |
c767a54b | 623 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
624 | |
625 | /* Target chip */ | |
cb3c8b90 | 626 | /* Send IPI */ |
1b374e4d | 627 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 628 | |
cfc1b9a6 | 629 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
630 | send_status = safe_apic_wait_icr_idle(); |
631 | ||
632 | mb(); | |
633 | atomic_set(&init_deasserted, 1); | |
634 | ||
635 | /* | |
636 | * Should we send STARTUP IPIs ? | |
637 | * | |
638 | * Determine this based on the APIC version. | |
639 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
640 | */ | |
641 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
642 | num_starts = 2; | |
643 | else | |
644 | num_starts = 0; | |
645 | ||
646 | /* | |
647 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
648 | * target processor state. | |
649 | */ | |
650 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 651 | stack_start); |
cb3c8b90 GOC |
652 | |
653 | /* | |
654 | * Run STARTUP IPI loop. | |
655 | */ | |
c767a54b | 656 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 657 | |
cb3c8b90 | 658 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 659 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
660 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
661 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 662 | apic_read(APIC_ESR); |
c767a54b | 663 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
664 | |
665 | /* | |
666 | * STARTUP IPI | |
667 | */ | |
668 | ||
669 | /* Target chip */ | |
cb3c8b90 GOC |
670 | /* Boot on the stack */ |
671 | /* Kick the second */ | |
1b374e4d SS |
672 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
673 | phys_apicid); | |
cb3c8b90 GOC |
674 | |
675 | /* | |
676 | * Give the other CPU some time to accept the IPI. | |
677 | */ | |
678 | udelay(300); | |
679 | ||
c767a54b | 680 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 681 | |
cfc1b9a6 | 682 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
683 | send_status = safe_apic_wait_icr_idle(); |
684 | ||
685 | /* | |
686 | * Give the other CPU some time to accept the IPI. | |
687 | */ | |
688 | udelay(200); | |
cb3c8b90 | 689 | |
593f4a78 | 690 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 691 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
692 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
693 | if (send_status || accept_status) | |
694 | break; | |
695 | } | |
c767a54b | 696 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
697 | |
698 | if (send_status) | |
c767a54b | 699 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 700 | if (accept_status) |
c767a54b | 701 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
702 | |
703 | return (send_status | accept_status); | |
704 | } | |
cb3c8b90 | 705 | |
a17bce4d BP |
706 | void smp_announce(void) |
707 | { | |
708 | int num_nodes = num_online_nodes(); | |
709 | ||
710 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
711 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
712 | } | |
713 | ||
2eaad1fd | 714 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 715 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
716 | { |
717 | static int current_node = -1; | |
4adc8b71 | 718 | int node = early_cpu_to_node(cpu); |
a17bce4d | 719 | static int width, node_width; |
646e29a1 BP |
720 | |
721 | if (!width) | |
722 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 723 | |
a17bce4d BP |
724 | if (!node_width) |
725 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
726 | ||
727 | if (cpu == 1) | |
728 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
729 | ||
2eaad1fd MT |
730 | if (system_state == SYSTEM_BOOTING) { |
731 | if (node != current_node) { | |
732 | if (current_node > (-1)) | |
a17bce4d | 733 | pr_cont("\n"); |
2eaad1fd | 734 | current_node = node; |
a17bce4d BP |
735 | |
736 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
737 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 738 | } |
646e29a1 BP |
739 | |
740 | /* Add padding for the BSP */ | |
741 | if (cpu == 1) | |
742 | pr_cont("%*s", width + 1, " "); | |
743 | ||
744 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
745 | ||
2eaad1fd MT |
746 | } else |
747 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
748 | node, cpu, apicid); | |
749 | } | |
750 | ||
e1c467e6 FY |
751 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
752 | { | |
753 | int cpu; | |
754 | ||
755 | cpu = smp_processor_id(); | |
756 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
757 | return NMI_HANDLED; | |
758 | ||
759 | return NMI_DONE; | |
760 | } | |
761 | ||
762 | /* | |
763 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
764 | * | |
765 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
766 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
767 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
768 | * | |
769 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
770 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
771 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
772 | * real platform and request are available. | |
773 | */ | |
148f9bb8 | 774 | static int |
e1c467e6 FY |
775 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
776 | int *cpu0_nmi_registered) | |
777 | { | |
778 | int id; | |
779 | int boot_error; | |
780 | ||
ea7bdc65 JK |
781 | preempt_disable(); |
782 | ||
e1c467e6 FY |
783 | /* |
784 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
785 | */ | |
ea7bdc65 JK |
786 | if (cpu) { |
787 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
788 | goto out; | |
789 | } | |
e1c467e6 FY |
790 | |
791 | /* | |
792 | * Wake up BSP by nmi. | |
793 | * | |
794 | * Register a NMI handler to help wake up CPU0. | |
795 | */ | |
796 | boot_error = register_nmi_handler(NMI_LOCAL, | |
797 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
798 | ||
799 | if (!boot_error) { | |
800 | enable_start_cpu0 = 1; | |
801 | *cpu0_nmi_registered = 1; | |
802 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
803 | id = cpu0_logical_apicid; | |
804 | else | |
805 | id = apicid; | |
806 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
807 | } | |
ea7bdc65 JK |
808 | |
809 | out: | |
810 | preempt_enable(); | |
e1c467e6 FY |
811 | |
812 | return boot_error; | |
813 | } | |
814 | ||
3f85483b BO |
815 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
816 | { | |
817 | /* Just in case we booted with a single CPU. */ | |
818 | alternatives_enable_smp(); | |
819 | ||
820 | per_cpu(current_task, cpu) = idle; | |
821 | ||
822 | #ifdef CONFIG_X86_32 | |
823 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
824 | irq_ctx_init(cpu); | |
825 | per_cpu(cpu_current_top_of_stack, cpu) = | |
826 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
827 | #else | |
828 | clear_tsk_thread_flag(idle, TIF_FORK); | |
829 | initial_gs = per_cpu_offset(cpu); | |
830 | #endif | |
3f85483b BO |
831 | } |
832 | ||
cb3c8b90 GOC |
833 | /* |
834 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
835 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
836 | * Returns zero if CPU booted OK, else error code from |
837 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 838 | */ |
148f9bb8 | 839 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 840 | { |
48927bbb | 841 | volatile u32 *trampoline_status = |
b429dbf6 | 842 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 843 | /* start_ip had better be page-aligned! */ |
f37240f1 | 844 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 845 | |
cb3c8b90 | 846 | unsigned long boot_error = 0; |
e1c467e6 | 847 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 848 | unsigned long timeout; |
cb3c8b90 | 849 | |
7eb43a6d TG |
850 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
851 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
cb3c8b90 | 852 | |
a939098a | 853 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 854 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 855 | stack_start = idle->thread.sp; |
cb3c8b90 | 856 | |
2eaad1fd MT |
857 | /* So we see what's up */ |
858 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
859 | |
860 | /* | |
861 | * This grunge runs the startup process for | |
862 | * the targeted processor. | |
863 | */ | |
864 | ||
865 | atomic_set(&init_deasserted, 0); | |
866 | ||
34d05591 | 867 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 868 | |
cfc1b9a6 | 869 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 870 | |
34d05591 JS |
871 | smpboot_setup_warm_reset_vector(start_ip); |
872 | /* | |
873 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
874 | */ |
875 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
876 | apic_write(APIC_ESR, 0); | |
877 | apic_read(APIC_ESR); | |
878 | } | |
34d05591 | 879 | } |
cb3c8b90 | 880 | |
ce4b1b16 IM |
881 | /* |
882 | * AP might wait on cpu_callout_mask in cpu_init() with | |
883 | * cpu_initialized_mask set if previous attempt to online | |
884 | * it timed-out. Clear cpu_initialized_mask so that after | |
885 | * INIT/SIPI it could start with a clean state. | |
886 | */ | |
887 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
888 | smp_mb(); | |
889 | ||
cb3c8b90 | 890 | /* |
e1c467e6 FY |
891 | * Wake up a CPU in difference cases: |
892 | * - Use the method in the APIC driver if it's defined | |
893 | * Otherwise, | |
894 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 895 | */ |
1f5bcabf IM |
896 | if (apic->wakeup_secondary_cpu) |
897 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
898 | else | |
e1c467e6 FY |
899 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
900 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
901 | |
902 | if (!boot_error) { | |
903 | /* | |
ce4b1b16 | 904 | * Wait 10s total for a response from AP |
cb3c8b90 | 905 | */ |
ce4b1b16 IM |
906 | boot_error = -1; |
907 | timeout = jiffies + 10*HZ; | |
908 | while (time_before(jiffies, timeout)) { | |
909 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
910 | /* | |
911 | * Tell AP to proceed with initialization | |
912 | */ | |
913 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
914 | boot_error = 0; | |
915 | break; | |
916 | } | |
917 | udelay(100); | |
918 | schedule(); | |
919 | } | |
920 | } | |
cb3c8b90 | 921 | |
ce4b1b16 | 922 | if (!boot_error) { |
cb3c8b90 | 923 | /* |
ce4b1b16 | 924 | * Wait till AP completes initial initialization |
cb3c8b90 | 925 | */ |
ce4b1b16 | 926 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
927 | /* |
928 | * Allow other tasks to run while we wait for the | |
929 | * AP to come online. This also gives a chance | |
930 | * for the MTRR work(triggered by the AP coming online) | |
931 | * to be completed in the stop machine context. | |
932 | */ | |
ce4b1b16 | 933 | udelay(100); |
68f202e4 | 934 | schedule(); |
cb3c8b90 | 935 | } |
cb3c8b90 GOC |
936 | } |
937 | ||
938 | /* mark "stuck" area as not stuck */ | |
48927bbb | 939 | *trampoline_status = 0; |
cb3c8b90 | 940 | |
02421f98 YL |
941 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
942 | /* | |
943 | * Cleanup possible dangling ends... | |
944 | */ | |
945 | smpboot_restore_warm_reset_vector(); | |
946 | } | |
e1c467e6 FY |
947 | /* |
948 | * Clean up the nmi handler. Do this after the callin and callout sync | |
949 | * to avoid impact of possible long unregister time. | |
950 | */ | |
951 | if (cpu0_nmi_registered) | |
952 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
953 | ||
cb3c8b90 GOC |
954 | return boot_error; |
955 | } | |
956 | ||
148f9bb8 | 957 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 958 | { |
a21769a4 | 959 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
960 | unsigned long flags; |
961 | int err; | |
962 | ||
963 | WARN_ON(irqs_disabled()); | |
964 | ||
cfc1b9a6 | 965 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 966 | |
30106c17 | 967 | if (apicid == BAD_APICID || |
c284b42a | 968 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 969 | !apic->apic_id_valid(apicid)) { |
c767a54b | 970 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
971 | return -EINVAL; |
972 | } | |
973 | ||
974 | /* | |
975 | * Already booted CPU? | |
976 | */ | |
c2d1cec1 | 977 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 978 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
979 | return -ENOSYS; |
980 | } | |
981 | ||
982 | /* | |
983 | * Save current MTRR state in case it was changed since early boot | |
984 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
985 | */ | |
986 | mtrr_save_state(); | |
987 | ||
2a442c9c PM |
988 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
989 | err = cpu_check_up_prepare(cpu); | |
990 | if (err && err != -EBUSY) | |
991 | return err; | |
cb3c8b90 | 992 | |
644c1541 VP |
993 | /* the FPU context is blank, nobody can own it */ |
994 | __cpu_disable_lazy_restore(cpu); | |
995 | ||
3f85483b BO |
996 | common_cpu_up(cpu, tidle); |
997 | ||
7eb43a6d | 998 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 999 | if (err) { |
feef1e8e | 1000 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1001 | return -EIO; |
cb3c8b90 GOC |
1002 | } |
1003 | ||
1004 | /* | |
1005 | * Check TSC synchronization with the AP (keep irqs disabled | |
1006 | * while doing so): | |
1007 | */ | |
1008 | local_irq_save(flags); | |
1009 | check_tsc_sync_source(cpu); | |
1010 | local_irq_restore(flags); | |
1011 | ||
7c04e64a | 1012 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1013 | cpu_relax(); |
1014 | touch_nmi_watchdog(); | |
1015 | } | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
7167d08e HK |
1020 | /** |
1021 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1022 | */ | |
1023 | void arch_disable_smp_support(void) | |
1024 | { | |
1025 | disable_ioapic_support(); | |
1026 | } | |
1027 | ||
8aef135c GOC |
1028 | /* |
1029 | * Fall back to non SMP mode after errors. | |
1030 | * | |
1031 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1032 | */ | |
1033 | static __init void disable_smp(void) | |
1034 | { | |
613c25ef TG |
1035 | pr_info("SMP disabled\n"); |
1036 | ||
ef4c59a4 TG |
1037 | disable_ioapic_support(); |
1038 | ||
4f062896 RR |
1039 | init_cpu_present(cpumask_of(0)); |
1040 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1041 | |
8aef135c | 1042 | if (smp_found_config) |
b6df1b8b | 1043 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1044 | else |
b6df1b8b | 1045 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1046 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1047 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1048 | } |
1049 | ||
613c25ef TG |
1050 | enum { |
1051 | SMP_OK, | |
1052 | SMP_NO_CONFIG, | |
1053 | SMP_NO_APIC, | |
1054 | SMP_FORCE_UP, | |
1055 | }; | |
1056 | ||
8aef135c GOC |
1057 | /* |
1058 | * Various sanity checks. | |
1059 | */ | |
1060 | static int __init smp_sanity_check(unsigned max_cpus) | |
1061 | { | |
ac23d4ee | 1062 | preempt_disable(); |
a58f03b0 | 1063 | |
1ff2f20d | 1064 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1065 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1066 | unsigned int cpu; | |
1067 | unsigned nr; | |
1068 | ||
c767a54b JP |
1069 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1070 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1071 | |
1072 | nr = 0; | |
1073 | for_each_present_cpu(cpu) { | |
1074 | if (nr >= 8) | |
c2d1cec1 | 1075 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1076 | nr++; |
1077 | } | |
1078 | ||
1079 | nr = 0; | |
1080 | for_each_possible_cpu(cpu) { | |
1081 | if (nr >= 8) | |
c2d1cec1 | 1082 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1083 | nr++; |
1084 | } | |
1085 | ||
1086 | nr_cpu_ids = 8; | |
1087 | } | |
1088 | #endif | |
1089 | ||
8aef135c | 1090 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1091 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1092 | hard_smp_processor_id()); |
1093 | ||
8aef135c GOC |
1094 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * If we couldn't find an SMP configuration at boot time, | |
1099 | * get out of here now! | |
1100 | */ | |
1101 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1102 | preempt_enable(); |
c767a54b | 1103 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1104 | return SMP_NO_CONFIG; |
8aef135c GOC |
1105 | } |
1106 | ||
1107 | /* | |
1108 | * Should not be necessary because the MP table should list the boot | |
1109 | * CPU too, but we do it for the sake of robustness anyway. | |
1110 | */ | |
a27a6210 | 1111 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1112 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1113 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1114 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1115 | } | |
ac23d4ee | 1116 | preempt_enable(); |
8aef135c GOC |
1117 | |
1118 | /* | |
1119 | * If we couldn't find a local APIC, then get out of here now! | |
1120 | */ | |
1121 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1122 | !cpu_has_apic) { | |
103428e5 CG |
1123 | if (!disable_apic) { |
1124 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1125 | boot_cpu_physical_apicid); | |
c767a54b | 1126 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1127 | } |
613c25ef | 1128 | return SMP_NO_APIC; |
8aef135c GOC |
1129 | } |
1130 | ||
8aef135c GOC |
1131 | /* |
1132 | * If SMP should be disabled, then really disable it! | |
1133 | */ | |
1134 | if (!max_cpus) { | |
c767a54b | 1135 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1136 | return SMP_FORCE_UP; |
8aef135c GOC |
1137 | } |
1138 | ||
613c25ef | 1139 | return SMP_OK; |
8aef135c GOC |
1140 | } |
1141 | ||
1142 | static void __init smp_cpu_index_default(void) | |
1143 | { | |
1144 | int i; | |
1145 | struct cpuinfo_x86 *c; | |
1146 | ||
7c04e64a | 1147 | for_each_possible_cpu(i) { |
8aef135c GOC |
1148 | c = &cpu_data(i); |
1149 | /* mark all to hotplug */ | |
9628937d | 1150 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1151 | } |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1156 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1157 | */ | |
1158 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1159 | { | |
7ad728f9 RR |
1160 | unsigned int i; |
1161 | ||
8aef135c | 1162 | smp_cpu_index_default(); |
792363d2 | 1163 | |
8aef135c GOC |
1164 | /* |
1165 | * Setup boot CPU information | |
1166 | */ | |
30106c17 | 1167 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1168 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1169 | mb(); | |
bd22a2f1 | 1170 | |
8aef135c | 1171 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1172 | for_each_possible_cpu(i) { |
79f55997 LZ |
1173 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1174 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1175 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1176 | } |
8aef135c GOC |
1177 | set_cpu_sibling_map(0); |
1178 | ||
613c25ef TG |
1179 | switch (smp_sanity_check(max_cpus)) { |
1180 | case SMP_NO_CONFIG: | |
8aef135c | 1181 | disable_smp(); |
613c25ef TG |
1182 | if (APIC_init_uniprocessor()) |
1183 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1184 | return; | |
1185 | case SMP_NO_APIC: | |
1186 | disable_smp(); | |
1187 | return; | |
1188 | case SMP_FORCE_UP: | |
1189 | disable_smp(); | |
374aab33 | 1190 | apic_bsp_setup(false); |
250a1ac6 | 1191 | return; |
613c25ef TG |
1192 | case SMP_OK: |
1193 | break; | |
8aef135c GOC |
1194 | } |
1195 | ||
fa47f7e5 SS |
1196 | default_setup_apic_routing(); |
1197 | ||
4c9961d5 | 1198 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1199 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1200 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1201 | /* Or can we switch back to PIC here? */ |
1202 | } | |
1203 | ||
374aab33 | 1204 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1205 | |
c767a54b | 1206 | pr_info("CPU%d: ", 0); |
8aef135c | 1207 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1208 | |
1209 | if (is_uv_system()) | |
1210 | uv_system_init(); | |
d0af9eed SS |
1211 | |
1212 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1213 | |
1214 | smp_quirk_init_udelay(); | |
8aef135c | 1215 | } |
d0af9eed SS |
1216 | |
1217 | void arch_enable_nonboot_cpus_begin(void) | |
1218 | { | |
1219 | set_mtrr_aps_delayed_init(); | |
1220 | } | |
1221 | ||
1222 | void arch_enable_nonboot_cpus_end(void) | |
1223 | { | |
1224 | mtrr_aps_init(); | |
1225 | } | |
1226 | ||
a8db8453 GOC |
1227 | /* |
1228 | * Early setup to make printk work. | |
1229 | */ | |
1230 | void __init native_smp_prepare_boot_cpu(void) | |
1231 | { | |
1232 | int me = smp_processor_id(); | |
552be871 | 1233 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1234 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1235 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1236 | cpu_set_state_online(me); |
a8db8453 GOC |
1237 | } |
1238 | ||
83f7eb9c GOC |
1239 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1240 | { | |
c767a54b | 1241 | pr_debug("Boot done\n"); |
83f7eb9c | 1242 | |
99e8b9ca | 1243 | nmi_selftest(); |
83f7eb9c | 1244 | impress_friends(); |
83f7eb9c | 1245 | setup_ioapic_dest(); |
d0af9eed | 1246 | mtrr_aps_init(); |
83f7eb9c GOC |
1247 | } |
1248 | ||
3b11ce7f MT |
1249 | static int __initdata setup_possible_cpus = -1; |
1250 | static int __init _setup_possible_cpus(char *str) | |
1251 | { | |
1252 | get_option(&str, &setup_possible_cpus); | |
1253 | return 0; | |
1254 | } | |
1255 | early_param("possible_cpus", _setup_possible_cpus); | |
1256 | ||
1257 | ||
68a1c3f8 | 1258 | /* |
4f062896 | 1259 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1260 | * are onlined, or offlined. The reason is per-cpu data-structures |
1261 | * are allocated by some modules at init time, and dont expect to | |
1262 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1263 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1264 | * In case when cpu_hotplug is not compiled, then we resort to current |
1265 | * behaviour, which is cpu_possible == cpu_present. | |
1266 | * - Ashok Raj | |
1267 | * | |
1268 | * Three ways to find out the number of additional hotplug CPUs: | |
1269 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1270 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1271 | * - Otherwise don't reserve additional CPUs. |
1272 | * We do this because additional CPUs waste a lot of memory. | |
1273 | * -AK | |
1274 | */ | |
1275 | __init void prefill_possible_map(void) | |
1276 | { | |
cb48bb59 | 1277 | int i, possible; |
68a1c3f8 | 1278 | |
329513a3 YL |
1279 | /* no processor from mptable or madt */ |
1280 | if (!num_processors) | |
1281 | num_processors = 1; | |
1282 | ||
5f2eb550 JB |
1283 | i = setup_max_cpus ?: 1; |
1284 | if (setup_possible_cpus == -1) { | |
1285 | possible = num_processors; | |
1286 | #ifdef CONFIG_HOTPLUG_CPU | |
1287 | if (setup_max_cpus) | |
1288 | possible += disabled_cpus; | |
1289 | #else | |
1290 | if (possible > i) | |
1291 | possible = i; | |
1292 | #endif | |
1293 | } else | |
3b11ce7f MT |
1294 | possible = setup_possible_cpus; |
1295 | ||
730cf272 MT |
1296 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1297 | ||
2b633e3f YL |
1298 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1299 | if (possible > nr_cpu_ids) { | |
c767a54b | 1300 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1301 | possible, nr_cpu_ids); |
1302 | possible = nr_cpu_ids; | |
3b11ce7f | 1303 | } |
68a1c3f8 | 1304 | |
5f2eb550 JB |
1305 | #ifdef CONFIG_HOTPLUG_CPU |
1306 | if (!setup_max_cpus) | |
1307 | #endif | |
1308 | if (possible > i) { | |
c767a54b | 1309 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1310 | possible, setup_max_cpus); |
1311 | possible = i; | |
1312 | } | |
1313 | ||
c767a54b | 1314 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1315 | possible, max_t(int, possible - num_processors, 0)); |
1316 | ||
1317 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1318 | set_cpu_possible(i, true); |
5f2eb550 JB |
1319 | for (; i < NR_CPUS; i++) |
1320 | set_cpu_possible(i, false); | |
3461b0af MT |
1321 | |
1322 | nr_cpu_ids = possible; | |
68a1c3f8 | 1323 | } |
69c18c15 | 1324 | |
14adf855 CE |
1325 | #ifdef CONFIG_HOTPLUG_CPU |
1326 | ||
1327 | static void remove_siblinginfo(int cpu) | |
1328 | { | |
1329 | int sibling; | |
1330 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1331 | ||
7d79a7bd BG |
1332 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1333 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1334 | /*/ |
1335 | * last thread sibling in this cpu core going down | |
1336 | */ | |
7d79a7bd | 1337 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1338 | cpu_data(sibling).booted_cores--; |
1339 | } | |
1340 | ||
7d79a7bd BG |
1341 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1342 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1343 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1344 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1345 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1346 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1347 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1348 | c->phys_proc_id = 0; |
1349 | c->cpu_core_id = 0; | |
c2d1cec1 | 1350 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1351 | } |
1352 | ||
69c18c15 GC |
1353 | static void __ref remove_cpu_from_maps(int cpu) |
1354 | { | |
c2d1cec1 MT |
1355 | set_cpu_online(cpu, false); |
1356 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1357 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1358 | /* was set by cpu_init() */ |
c2d1cec1 | 1359 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1360 | numa_remove_cpu(cpu); |
69c18c15 GC |
1361 | } |
1362 | ||
8227dce7 | 1363 | void cpu_disable_common(void) |
69c18c15 GC |
1364 | { |
1365 | int cpu = smp_processor_id(); | |
69c18c15 | 1366 | |
69c18c15 GC |
1367 | remove_siblinginfo(cpu); |
1368 | ||
1369 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1370 | lock_vector_lock(); |
69c18c15 | 1371 | remove_cpu_from_maps(cpu); |
d388e5fd | 1372 | unlock_vector_lock(); |
d7b381bb | 1373 | fixup_irqs(); |
8227dce7 AN |
1374 | } |
1375 | ||
1376 | int native_cpu_disable(void) | |
1377 | { | |
da6139e4 PB |
1378 | int ret; |
1379 | ||
1380 | ret = check_irq_vectors_for_cpu_disable(); | |
1381 | if (ret) | |
1382 | return ret; | |
1383 | ||
8227dce7 | 1384 | clear_local_APIC(); |
8227dce7 | 1385 | cpu_disable_common(); |
2ed53c0d | 1386 | |
69c18c15 GC |
1387 | return 0; |
1388 | } | |
1389 | ||
2a442c9c | 1390 | int common_cpu_die(unsigned int cpu) |
54279552 | 1391 | { |
2a442c9c | 1392 | int ret = 0; |
54279552 | 1393 | |
69c18c15 | 1394 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1395 | |
2ed53c0d | 1396 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1397 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1398 | if (system_state == SYSTEM_RUNNING) |
1399 | pr_info("CPU %u is now offline\n", cpu); | |
1400 | } else { | |
1401 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1402 | ret = -1; |
69c18c15 | 1403 | } |
2a442c9c PM |
1404 | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | void native_cpu_die(unsigned int cpu) | |
1409 | { | |
1410 | common_cpu_die(cpu); | |
69c18c15 | 1411 | } |
a21f5d88 AN |
1412 | |
1413 | void play_dead_common(void) | |
1414 | { | |
1415 | idle_task_exit(); | |
1416 | reset_lazy_tlbstate(); | |
02c68a02 | 1417 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 | 1418 | |
a21f5d88 | 1419 | /* Ack it */ |
2a442c9c | 1420 | (void)cpu_report_death(); |
a21f5d88 AN |
1421 | |
1422 | /* | |
1423 | * With physical CPU hotplug, we should halt the cpu | |
1424 | */ | |
1425 | local_irq_disable(); | |
1426 | } | |
1427 | ||
e1c467e6 FY |
1428 | static bool wakeup_cpu0(void) |
1429 | { | |
1430 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1431 | return true; | |
1432 | ||
1433 | return false; | |
1434 | } | |
1435 | ||
ea530692 PA |
1436 | /* |
1437 | * We need to flush the caches before going to sleep, lest we have | |
1438 | * dirty data in our caches when we come back up. | |
1439 | */ | |
1440 | static inline void mwait_play_dead(void) | |
1441 | { | |
1442 | unsigned int eax, ebx, ecx, edx; | |
1443 | unsigned int highest_cstate = 0; | |
1444 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1445 | void *mwait_ptr; |
576cfb40 | 1446 | int i; |
ea530692 | 1447 | |
69fb3676 | 1448 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1449 | return; |
840d2830 | 1450 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1451 | return; |
7b543a53 | 1452 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1453 | return; |
1454 | ||
1455 | eax = CPUID_MWAIT_LEAF; | |
1456 | ecx = 0; | |
1457 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1458 | ||
1459 | /* | |
1460 | * eax will be 0 if EDX enumeration is not valid. | |
1461 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1462 | */ | |
1463 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1464 | eax = 0; | |
1465 | } else { | |
1466 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1467 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1468 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1469 | highest_cstate = i; | |
1470 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1471 | } | |
1472 | } | |
1473 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1474 | (highest_subcstate - 1); | |
1475 | } | |
1476 | ||
ce5f6824 PA |
1477 | /* |
1478 | * This should be a memory location in a cache line which is | |
1479 | * unlikely to be touched by other processors. The actual | |
1480 | * content is immaterial as it is not actually modified in any way. | |
1481 | */ | |
1482 | mwait_ptr = ¤t_thread_info()->flags; | |
1483 | ||
a68e5c94 PA |
1484 | wbinvd(); |
1485 | ||
ea530692 | 1486 | while (1) { |
ce5f6824 PA |
1487 | /* |
1488 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1489 | * the Xeon 7400 series. It's not clear it is actually | |
1490 | * needed, but it should be harmless in either case. | |
1491 | * The WBINVD is insufficient due to the spurious-wakeup | |
1492 | * case where we return around the loop. | |
1493 | */ | |
7d590cca | 1494 | mb(); |
ce5f6824 | 1495 | clflush(mwait_ptr); |
7d590cca | 1496 | mb(); |
ce5f6824 | 1497 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1498 | mb(); |
1499 | __mwait(eax, 0); | |
e1c467e6 FY |
1500 | /* |
1501 | * If NMI wants to wake up CPU0, start CPU0. | |
1502 | */ | |
1503 | if (wakeup_cpu0()) | |
1504 | start_cpu0(); | |
ea530692 PA |
1505 | } |
1506 | } | |
1507 | ||
1508 | static inline void hlt_play_dead(void) | |
1509 | { | |
7b543a53 | 1510 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1511 | wbinvd(); |
1512 | ||
ea530692 | 1513 | while (1) { |
ea530692 | 1514 | native_halt(); |
e1c467e6 FY |
1515 | /* |
1516 | * If NMI wants to wake up CPU0, start CPU0. | |
1517 | */ | |
1518 | if (wakeup_cpu0()) | |
1519 | start_cpu0(); | |
ea530692 PA |
1520 | } |
1521 | } | |
1522 | ||
a21f5d88 AN |
1523 | void native_play_dead(void) |
1524 | { | |
1525 | play_dead_common(); | |
86886e55 | 1526 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1527 | |
1528 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1529 | if (cpuidle_play_dead()) |
1530 | hlt_play_dead(); | |
a21f5d88 AN |
1531 | } |
1532 | ||
69c18c15 | 1533 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1534 | int native_cpu_disable(void) |
69c18c15 GC |
1535 | { |
1536 | return -ENOSYS; | |
1537 | } | |
1538 | ||
93be71b6 | 1539 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1540 | { |
1541 | /* We said "no" in __cpu_disable */ | |
1542 | BUG(); | |
1543 | } | |
a21f5d88 AN |
1544 | |
1545 | void native_play_dead(void) | |
1546 | { | |
1547 | BUG(); | |
1548 | } | |
1549 | ||
68a1c3f8 | 1550 | #endif |