Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
07bbc16a | 55 | #include <asm/idle.h> |
69c18c15 | 56 | #include <asm/smp.h> |
e44b7b75 | 57 | #include <asm/trampoline.h> |
69c18c15 GC |
58 | #include <asm/cpu.h> |
59 | #include <asm/numa.h> | |
cb3c8b90 GOC |
60 | #include <asm/pgtable.h> |
61 | #include <asm/tlbflush.h> | |
62 | #include <asm/mtrr.h> | |
bbc2ff6a | 63 | #include <asm/vmi.h> |
34d05591 | 64 | #include <asm/genapic.h> |
569712b2 | 65 | #include <asm/setup.h> |
cb3c8b90 | 66 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 67 | |
f6bc4029 | 68 | #include <mach_apic.h> |
cb3c8b90 GOC |
69 | #include <mach_wakecpu.h> |
70 | #include <smpboot_hooks.h> | |
71 | ||
16ecf7a4 | 72 | #ifdef CONFIG_X86_32 |
4cedb334 | 73 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 74 | static int low_mappings; |
acbb6734 GOC |
75 | #endif |
76 | ||
a8db8453 GOC |
77 | /* State of each CPU */ |
78 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
79 | ||
cb3c8b90 GOC |
80 | /* Store all idle threads, this can be reused instead of creating |
81 | * a new thread. Also avoids complicated thread destroy functionality | |
82 | * for idle threads. | |
83 | */ | |
84 | #ifdef CONFIG_HOTPLUG_CPU | |
85 | /* | |
86 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
87 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
88 | */ | |
89 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
90 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
91 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
92 | #else | |
f86c9985 | 93 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
94 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
95 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
96 | #endif | |
f6bc4029 | 97 | |
a355352b GC |
98 | /* Number of siblings per CPU package */ |
99 | int smp_num_siblings = 1; | |
100 | EXPORT_SYMBOL(smp_num_siblings); | |
101 | ||
102 | /* Last level cache ID of each logical CPU */ | |
103 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
104 | ||
105 | /* bitmap of online cpus */ | |
106 | cpumask_t cpu_online_map __read_mostly; | |
107 | EXPORT_SYMBOL(cpu_online_map); | |
108 | ||
109 | cpumask_t cpu_callin_map; | |
110 | cpumask_t cpu_callout_map; | |
111 | cpumask_t cpu_possible_map; | |
112 | EXPORT_SYMBOL(cpu_possible_map); | |
113 | ||
114 | /* representing HT siblings of each logical CPU */ | |
115 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
116 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
117 | ||
118 | /* representing HT and core siblings of each logical CPU */ | |
119 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
120 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
121 | ||
122 | /* Per CPU bogomips and other parameters */ | |
123 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
124 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 125 | |
cb3c8b90 GOC |
126 | static atomic_t init_deasserted; |
127 | ||
8aef135c | 128 | |
768d9505 GC |
129 | /* representing cpus for which sibling maps can be computed */ |
130 | static cpumask_t cpu_sibling_setup_map; | |
131 | ||
1d89a7f0 | 132 | /* Set if we find a B stepping CPU */ |
f86c9985 | 133 | static int __cpuinitdata smp_b_stepping; |
1d89a7f0 | 134 | |
7cc3959e GOC |
135 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
136 | ||
137 | /* which logical CPUs are on which nodes */ | |
138 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
139 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
140 | EXPORT_SYMBOL(node_to_cpumask_map); | |
141 | /* which node each logical CPU is on */ | |
142 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
143 | EXPORT_SYMBOL(cpu_to_node_map); | |
144 | ||
145 | /* set up a mapping between cpu and node. */ | |
146 | static void map_cpu_to_node(int cpu, int node) | |
147 | { | |
148 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
149 | cpu_set(cpu, node_to_cpumask_map[node]); | |
150 | cpu_to_node_map[cpu] = node; | |
151 | } | |
152 | ||
153 | /* undo a mapping between cpu and node. */ | |
154 | static void unmap_cpu_to_node(int cpu) | |
155 | { | |
156 | int node; | |
157 | ||
158 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
159 | for (node = 0; node < MAX_NUMNODES; node++) | |
160 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
161 | cpu_to_node_map[cpu] = 0; | |
162 | } | |
163 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
164 | #define map_cpu_to_node(cpu, node) ({}) | |
165 | #define unmap_cpu_to_node(cpu) ({}) | |
166 | #endif | |
167 | ||
168 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
169 | static int boot_cpu_logical_apicid; |
170 | ||
7cc3959e GOC |
171 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
172 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
173 | ||
a4928cff | 174 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
175 | { |
176 | int cpu = smp_processor_id(); | |
177 | int apicid = logical_smp_processor_id(); | |
178 | int node = apicid_to_node(apicid); | |
179 | ||
180 | if (!node_online(node)) | |
181 | node = first_online_node; | |
182 | ||
183 | cpu_2_logical_apicid[cpu] = apicid; | |
184 | map_cpu_to_node(cpu, node); | |
185 | } | |
186 | ||
1481a3dd | 187 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
188 | { |
189 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
190 | unmap_cpu_to_node(cpu); | |
191 | } | |
192 | #else | |
7cc3959e GOC |
193 | #define map_cpu_to_logical_apicid() do {} while (0) |
194 | #endif | |
195 | ||
cb3c8b90 GOC |
196 | /* |
197 | * Report back to the Boot Processor. | |
198 | * Running on AP. | |
199 | */ | |
a4928cff | 200 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
201 | { |
202 | int cpuid, phys_id; | |
203 | unsigned long timeout; | |
204 | ||
205 | /* | |
206 | * If waken up by an INIT in an 82489DX configuration | |
207 | * we may get here before an INIT-deassert IPI reaches | |
208 | * our local APIC. We have to wait for the IPI or we'll | |
209 | * lock up on an APIC access. | |
210 | */ | |
211 | wait_for_init_deassert(&init_deasserted); | |
212 | ||
213 | /* | |
214 | * (This works even if the APIC is not enabled.) | |
215 | */ | |
4c9961d5 | 216 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
217 | cpuid = smp_processor_id(); |
218 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
219 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
220 | phys_id, cpuid); | |
221 | } | |
cfc1b9a6 | 222 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
223 | |
224 | /* | |
225 | * STARTUP IPIs are fragile beasts as they might sometimes | |
226 | * trigger some glue motherboard logic. Complete APIC bus | |
227 | * silence for 1 second, this overestimates the time the | |
228 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
229 | * by a factor of two. This should be enough. | |
230 | */ | |
231 | ||
232 | /* | |
233 | * Waiting 2s total for startup (udelay is not yet working) | |
234 | */ | |
235 | timeout = jiffies + 2*HZ; | |
236 | while (time_before(jiffies, timeout)) { | |
237 | /* | |
238 | * Has the boot CPU finished it's STARTUP sequence? | |
239 | */ | |
240 | if (cpu_isset(cpuid, cpu_callout_map)) | |
241 | break; | |
242 | cpu_relax(); | |
243 | } | |
244 | ||
245 | if (!time_before(jiffies, timeout)) { | |
246 | panic("%s: CPU%d started up but did not get a callout!\n", | |
247 | __func__, cpuid); | |
248 | } | |
249 | ||
250 | /* | |
251 | * the boot CPU has finished the init stage and is spinning | |
252 | * on callin_map until we finish. We are free to set up this | |
253 | * CPU, first the APIC. (this is probably redundant on most | |
254 | * boards) | |
255 | */ | |
256 | ||
cfc1b9a6 | 257 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
cb3c8b90 GOC |
258 | smp_callin_clear_local_apic(); |
259 | setup_local_APIC(); | |
260 | end_local_APIC_setup(); | |
261 | map_cpu_to_logical_apicid(); | |
262 | ||
e545a614 | 263 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
264 | /* |
265 | * Get our bogomips. | |
266 | * | |
267 | * Need to enable IRQs because it can take longer and then | |
268 | * the NMI watchdog might kill us. | |
269 | */ | |
270 | local_irq_enable(); | |
271 | calibrate_delay(); | |
272 | local_irq_disable(); | |
cfc1b9a6 | 273 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
274 | |
275 | /* | |
276 | * Save our processor parameters | |
277 | */ | |
278 | smp_store_cpu_info(cpuid); | |
279 | ||
280 | /* | |
281 | * Allow the master to continue. | |
282 | */ | |
283 | cpu_set(cpuid, cpu_callin_map); | |
284 | } | |
285 | ||
25ddbb18 AK |
286 | static int __cpuinitdata unsafe_smp; |
287 | ||
bbc2ff6a GOC |
288 | /* |
289 | * Activate a secondary processor. | |
290 | */ | |
dbe55f47 | 291 | static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
292 | { |
293 | /* | |
294 | * Don't put *anything* before cpu_init(), SMP booting is too | |
295 | * fragile that we want to limit the things done here to the | |
296 | * most necessary things. | |
297 | */ | |
298 | #ifdef CONFIG_VMI | |
299 | vmi_bringup(); | |
300 | #endif | |
301 | cpu_init(); | |
302 | preempt_disable(); | |
303 | smp_callin(); | |
304 | ||
305 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
306 | barrier(); | |
307 | /* | |
308 | * Check TSC synchronization with the BP: | |
309 | */ | |
310 | check_tsc_sync_target(); | |
311 | ||
312 | if (nmi_watchdog == NMI_IO_APIC) { | |
313 | disable_8259A_irq(0); | |
314 | enable_NMI_through_LVT0(); | |
315 | enable_8259A_irq(0); | |
316 | } | |
317 | ||
61165d7a HD |
318 | #ifdef CONFIG_X86_32 |
319 | while (low_mappings) | |
320 | cpu_relax(); | |
321 | __flush_tlb_all(); | |
322 | #endif | |
323 | ||
bbc2ff6a GOC |
324 | /* This must be done before setting cpu_online_map */ |
325 | set_cpu_sibling_map(raw_smp_processor_id()); | |
326 | wmb(); | |
327 | ||
328 | /* | |
329 | * We need to hold call_lock, so there is no inconsistency | |
330 | * between the time smp_call_function() determines number of | |
331 | * IPI recipients, and the time when the determination is made | |
332 | * for which cpus receive the IPI. Holding this | |
333 | * lock helps us to not include this cpu in a currently in progress | |
334 | * smp_call_function(). | |
d388e5fd EB |
335 | * |
336 | * We need to hold vector_lock so there the set of online cpus | |
337 | * does not change while we are assigning vectors to cpus. Holding | |
338 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 339 | */ |
0cefa5b9 | 340 | ipi_call_lock(); |
d388e5fd EB |
341 | lock_vector_lock(); |
342 | __setup_vector_irq(smp_processor_id()); | |
bbc2ff6a | 343 | cpu_set(smp_processor_id(), cpu_online_map); |
d388e5fd | 344 | unlock_vector_lock(); |
0cefa5b9 | 345 | ipi_call_unlock(); |
bbc2ff6a GOC |
346 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
347 | ||
0cefa5b9 MS |
348 | /* enable local interrupts */ |
349 | local_irq_enable(); | |
350 | ||
bbc2ff6a GOC |
351 | setup_secondary_clock(); |
352 | ||
353 | wmb(); | |
354 | cpu_idle(); | |
355 | } | |
356 | ||
1d89a7f0 GOC |
357 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
358 | { | |
1d89a7f0 GOC |
359 | /* |
360 | * Mask B, Pentium, but not Pentium MMX | |
361 | */ | |
362 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
363 | c->x86 == 5 && | |
364 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
365 | c->x86_model <= 3) | |
366 | /* | |
367 | * Remember we have B step Pentia with bugs | |
368 | */ | |
369 | smp_b_stepping = 1; | |
370 | ||
371 | /* | |
372 | * Certain Athlons might work (for various values of 'work') in SMP | |
373 | * but they are not certified as MP capable. | |
374 | */ | |
375 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
376 | ||
377 | if (num_possible_cpus() == 1) | |
378 | goto valid_k7; | |
379 | ||
380 | /* Athlon 660/661 is valid. */ | |
381 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
382 | (c->x86_mask == 1))) | |
383 | goto valid_k7; | |
384 | ||
385 | /* Duron 670 is valid */ | |
386 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
387 | goto valid_k7; | |
388 | ||
389 | /* | |
390 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
391 | * bit. It's worth noting that the A5 stepping (662) of some | |
392 | * Athlon XP's have the MP bit set. | |
393 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
394 | * more. | |
395 | */ | |
396 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
397 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
398 | (c->x86_model > 7)) | |
399 | if (cpu_has_mp) | |
400 | goto valid_k7; | |
401 | ||
402 | /* If we get here, not a certified SMP capable AMD system. */ | |
25ddbb18 | 403 | unsafe_smp = 1; |
1d89a7f0 GOC |
404 | } |
405 | ||
406 | valid_k7: | |
407 | ; | |
1d89a7f0 GOC |
408 | } |
409 | ||
a4928cff | 410 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
411 | { |
412 | if (smp_b_stepping) | |
413 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
414 | "with B stepping processors.\n"); | |
415 | ||
416 | /* | |
417 | * Don't taint if we are running SMP kernel on a single non-MP | |
418 | * approved Athlon | |
419 | */ | |
25ddbb18 AK |
420 | if (unsafe_smp && num_online_cpus() > 1) { |
421 | printk(KERN_INFO "WARNING: This combination of AMD" | |
422 | "processors is not suitable for SMP.\n"); | |
423 | add_taint(TAINT_UNSAFE_SMP); | |
693d4b8a GOC |
424 | } |
425 | } | |
426 | ||
1d89a7f0 GOC |
427 | /* |
428 | * The bootstrap kernel entry code has set these up. Save them for | |
429 | * a given CPU | |
430 | */ | |
431 | ||
432 | void __cpuinit smp_store_cpu_info(int id) | |
433 | { | |
434 | struct cpuinfo_x86 *c = &cpu_data(id); | |
435 | ||
436 | *c = boot_cpu_data; | |
437 | c->cpu_index = id; | |
438 | if (id != 0) | |
439 | identify_secondary_cpu(c); | |
440 | smp_apply_quirks(c); | |
441 | } | |
442 | ||
443 | ||
768d9505 GC |
444 | void __cpuinit set_cpu_sibling_map(int cpu) |
445 | { | |
446 | int i; | |
447 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
448 | ||
449 | cpu_set(cpu, cpu_sibling_setup_map); | |
450 | ||
451 | if (smp_num_siblings > 1) { | |
334ef7a7 | 452 | for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { |
768d9505 GC |
453 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && |
454 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
455 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
456 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
457 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
458 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
459 | cpu_set(i, c->llc_shared_map); | |
460 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
461 | } | |
462 | } | |
463 | } else { | |
464 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
465 | } | |
466 | ||
467 | cpu_set(cpu, c->llc_shared_map); | |
468 | ||
469 | if (current_cpu_data.x86_max_cores == 1) { | |
470 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
471 | c->booted_cores = 1; | |
472 | return; | |
473 | } | |
474 | ||
334ef7a7 | 475 | for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { |
768d9505 GC |
476 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
477 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
478 | cpu_set(i, c->llc_shared_map); | |
479 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
480 | } | |
481 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
482 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
483 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
484 | /* | |
485 | * Does this new cpu bringup a new core? | |
486 | */ | |
487 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
488 | /* | |
489 | * for each core in package, increment | |
490 | * the booted_cores for this new cpu | |
491 | */ | |
492 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
493 | c->booted_cores++; | |
494 | /* | |
495 | * increment the core count for all | |
496 | * the other cpus in this package | |
497 | */ | |
498 | if (i != cpu) | |
499 | cpu_data(i).booted_cores++; | |
500 | } else if (i != cpu && !c->booted_cores) | |
501 | c->booted_cores = cpu_data(i).booted_cores; | |
502 | } | |
503 | } | |
504 | } | |
505 | ||
70708a18 GC |
506 | /* maps the cpu to the sched domain representing multi-core */ |
507 | cpumask_t cpu_coregroup_map(int cpu) | |
508 | { | |
509 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
510 | /* | |
511 | * For perf, we return last level cache shared map. | |
512 | * And for power savings, we return cpu_core_map | |
513 | */ | |
514 | if (sched_mc_power_savings || sched_smt_power_savings) | |
515 | return per_cpu(cpu_core_map, cpu); | |
516 | else | |
517 | return c->llc_shared_map; | |
518 | } | |
519 | ||
a4928cff | 520 | static void impress_friends(void) |
904541e2 GOC |
521 | { |
522 | int cpu; | |
523 | unsigned long bogosum = 0; | |
524 | /* | |
525 | * Allow the user to impress friends. | |
526 | */ | |
cfc1b9a6 | 527 | pr_debug("Before bogomips.\n"); |
904541e2 GOC |
528 | for_each_possible_cpu(cpu) |
529 | if (cpu_isset(cpu, cpu_callout_map)) | |
530 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
531 | printk(KERN_INFO | |
532 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 533 | num_online_cpus(), |
904541e2 GOC |
534 | bogosum/(500000/HZ), |
535 | (bogosum/(5000/HZ))%100); | |
536 | ||
cfc1b9a6 | 537 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
538 | } |
539 | ||
569712b2 | 540 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
541 | { |
542 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
543 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
544 | int timeout; | |
545 | u32 status; | |
546 | ||
823b259b | 547 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
548 | |
549 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 550 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
551 | |
552 | /* | |
553 | * Wait for idle. | |
554 | */ | |
555 | status = safe_apic_wait_icr_idle(); | |
556 | if (status) | |
557 | printk(KERN_CONT | |
558 | "a previous APIC delivery may have failed\n"); | |
559 | ||
1b374e4d | 560 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
561 | |
562 | timeout = 0; | |
563 | do { | |
564 | udelay(100); | |
565 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
566 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
567 | ||
568 | switch (status) { | |
569 | case APIC_ICR_RR_VALID: | |
570 | status = apic_read(APIC_RRR); | |
571 | printk(KERN_CONT "%08x\n", status); | |
572 | break; | |
573 | default: | |
574 | printk(KERN_CONT "failed\n"); | |
575 | } | |
576 | } | |
577 | } | |
578 | ||
cb3c8b90 GOC |
579 | /* |
580 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
581 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
582 | * won't ... remember to clear down the APIC, etc later. | |
583 | */ | |
569712b2 YL |
584 | int __devinit |
585 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |
cb3c8b90 GOC |
586 | { |
587 | unsigned long send_status, accept_status = 0; | |
588 | int maxlvt; | |
589 | ||
590 | /* Target chip */ | |
cb3c8b90 GOC |
591 | /* Boot on the stack */ |
592 | /* Kick the second */ | |
1b374e4d | 593 | apic_icr_write(APIC_DM_NMI | APIC_DEST_LOGICAL, logical_apicid); |
cb3c8b90 | 594 | |
cfc1b9a6 | 595 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
596 | send_status = safe_apic_wait_icr_idle(); |
597 | ||
598 | /* | |
599 | * Give the other CPU some time to accept the IPI. | |
600 | */ | |
601 | udelay(200); | |
569712b2 | 602 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
603 | maxlvt = lapic_get_maxlvt(); |
604 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
605 | apic_write(APIC_ESR, 0); | |
606 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
607 | } | |
cfc1b9a6 | 608 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
609 | |
610 | if (send_status) | |
611 | printk(KERN_ERR "APIC never delivered???\n"); | |
612 | if (accept_status) | |
613 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
614 | ||
615 | return (send_status | accept_status); | |
616 | } | |
cb3c8b90 | 617 | |
cb3c8b90 | 618 | static int __devinit |
569712b2 | 619 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
620 | { |
621 | unsigned long send_status, accept_status = 0; | |
622 | int maxlvt, num_starts, j; | |
623 | ||
34d05591 JS |
624 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
625 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
626 | atomic_set(&init_deasserted, 1); | |
627 | return send_status; | |
628 | } | |
629 | ||
593f4a78 MR |
630 | maxlvt = lapic_get_maxlvt(); |
631 | ||
cb3c8b90 GOC |
632 | /* |
633 | * Be paranoid about clearing APIC errors. | |
634 | */ | |
635 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
636 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
637 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
638 | apic_read(APIC_ESR); |
639 | } | |
640 | ||
cfc1b9a6 | 641 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
642 | |
643 | /* | |
644 | * Turn INIT on target chip | |
645 | */ | |
cb3c8b90 GOC |
646 | /* |
647 | * Send IPI | |
648 | */ | |
1b374e4d SS |
649 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
650 | phys_apicid); | |
cb3c8b90 | 651 | |
cfc1b9a6 | 652 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
653 | send_status = safe_apic_wait_icr_idle(); |
654 | ||
655 | mdelay(10); | |
656 | ||
cfc1b9a6 | 657 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
658 | |
659 | /* Target chip */ | |
cb3c8b90 | 660 | /* Send IPI */ |
1b374e4d | 661 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 662 | |
cfc1b9a6 | 663 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
664 | send_status = safe_apic_wait_icr_idle(); |
665 | ||
666 | mb(); | |
667 | atomic_set(&init_deasserted, 1); | |
668 | ||
669 | /* | |
670 | * Should we send STARTUP IPIs ? | |
671 | * | |
672 | * Determine this based on the APIC version. | |
673 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
674 | */ | |
675 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
676 | num_starts = 2; | |
677 | else | |
678 | num_starts = 0; | |
679 | ||
680 | /* | |
681 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
682 | * target processor state. | |
683 | */ | |
684 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 685 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
686 | |
687 | /* | |
688 | * Run STARTUP IPI loop. | |
689 | */ | |
cfc1b9a6 | 690 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 691 | |
cb3c8b90 | 692 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 693 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
694 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
695 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 696 | apic_read(APIC_ESR); |
cfc1b9a6 | 697 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
698 | |
699 | /* | |
700 | * STARTUP IPI | |
701 | */ | |
702 | ||
703 | /* Target chip */ | |
cb3c8b90 GOC |
704 | /* Boot on the stack */ |
705 | /* Kick the second */ | |
1b374e4d SS |
706 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
707 | phys_apicid); | |
cb3c8b90 GOC |
708 | |
709 | /* | |
710 | * Give the other CPU some time to accept the IPI. | |
711 | */ | |
712 | udelay(300); | |
713 | ||
cfc1b9a6 | 714 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 715 | |
cfc1b9a6 | 716 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
717 | send_status = safe_apic_wait_icr_idle(); |
718 | ||
719 | /* | |
720 | * Give the other CPU some time to accept the IPI. | |
721 | */ | |
722 | udelay(200); | |
593f4a78 | 723 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 724 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
725 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
726 | if (send_status || accept_status) | |
727 | break; | |
728 | } | |
cfc1b9a6 | 729 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
730 | |
731 | if (send_status) | |
732 | printk(KERN_ERR "APIC never delivered???\n"); | |
733 | if (accept_status) | |
734 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
735 | ||
736 | return (send_status | accept_status); | |
737 | } | |
569712b2 YL |
738 | |
739 | static int __devinit | |
740 | wakeup_secondary_cpu(int apicid, unsigned long start_eip) | |
741 | { | |
742 | if (x86_quirks->wakeup_secondary_cpu) | |
743 | return x86_quirks->wakeup_secondary_cpu(apicid, start_eip); | |
744 | ||
745 | return wakeup_secondary_cpu_via_init(apicid, start_eip); | |
746 | } | |
cb3c8b90 GOC |
747 | |
748 | struct create_idle { | |
749 | struct work_struct work; | |
750 | struct task_struct *idle; | |
751 | struct completion done; | |
752 | int cpu; | |
753 | }; | |
754 | ||
755 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
756 | { | |
757 | struct create_idle *c_idle = | |
758 | container_of(work, struct create_idle, work); | |
759 | ||
760 | c_idle->idle = fork_idle(c_idle->cpu); | |
761 | complete(&c_idle->done); | |
762 | } | |
763 | ||
f307d25e | 764 | #ifdef CONFIG_X86_64 |
d19fbfdf MS |
765 | |
766 | /* __ref because it's safe to call free_bootmem when after_bootmem == 0. */ | |
767 | static void __ref free_bootmem_pda(struct x8664_pda *oldpda) | |
768 | { | |
769 | if (!after_bootmem) | |
770 | free_bootmem((unsigned long)oldpda, sizeof(*oldpda)); | |
771 | } | |
772 | ||
3461b0af MT |
773 | /* |
774 | * Allocate node local memory for the AP pda. | |
775 | * | |
776 | * Must be called after the _cpu_pda pointer table is initialized. | |
777 | */ | |
7c33b1e6 | 778 | int __cpuinit get_local_pda(int cpu) |
3461b0af MT |
779 | { |
780 | struct x8664_pda *oldpda, *newpda; | |
781 | unsigned long size = sizeof(struct x8664_pda); | |
782 | int node = cpu_to_node(cpu); | |
783 | ||
784 | if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem) | |
785 | return 0; | |
786 | ||
787 | oldpda = cpu_pda(cpu); | |
788 | newpda = kmalloc_node(size, GFP_ATOMIC, node); | |
789 | if (!newpda) { | |
790 | printk(KERN_ERR "Could not allocate node local PDA " | |
791 | "for CPU %d on node %d\n", cpu, node); | |
792 | ||
793 | if (oldpda) | |
794 | return 0; /* have a usable pda */ | |
795 | else | |
796 | return -1; | |
797 | } | |
798 | ||
799 | if (oldpda) { | |
800 | memcpy(newpda, oldpda, size); | |
d19fbfdf | 801 | free_bootmem_pda(oldpda); |
3461b0af MT |
802 | } |
803 | ||
804 | newpda->in_bootmem = 0; | |
805 | cpu_pda(cpu) = newpda; | |
806 | return 0; | |
807 | } | |
f307d25e | 808 | #endif /* CONFIG_X86_64 */ |
3461b0af | 809 | |
cb3c8b90 GOC |
810 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
811 | /* | |
812 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
813 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
814 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
815 | */ | |
816 | { | |
817 | unsigned long boot_error = 0; | |
818 | int timeout; | |
819 | unsigned long start_ip; | |
820 | unsigned short nmi_high = 0, nmi_low = 0; | |
821 | struct create_idle c_idle = { | |
822 | .cpu = cpu, | |
823 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
824 | }; | |
825 | INIT_WORK(&c_idle.work, do_fork_idle); | |
cb3c8b90 | 826 | |
a939098a | 827 | #ifdef CONFIG_X86_64 |
cb3c8b90 | 828 | /* Allocate node local memory for AP pdas */ |
3461b0af MT |
829 | if (cpu > 0) { |
830 | boot_error = get_local_pda(cpu); | |
831 | if (boot_error) | |
832 | goto restore_state; | |
833 | /* if can't get pda memory, can't start cpu */ | |
cb3c8b90 GOC |
834 | } |
835 | #endif | |
836 | ||
837 | alternatives_smp_switch(1); | |
838 | ||
839 | c_idle.idle = get_idle_for_cpu(cpu); | |
840 | ||
841 | /* | |
842 | * We can't use kernel_thread since we must avoid to | |
843 | * reschedule the child. | |
844 | */ | |
845 | if (c_idle.idle) { | |
846 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
847 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
848 | init_idle(c_idle.idle, cpu); | |
849 | goto do_rest; | |
850 | } | |
851 | ||
852 | if (!keventd_up() || current_is_keventd()) | |
853 | c_idle.work.func(&c_idle.work); | |
854 | else { | |
855 | schedule_work(&c_idle.work); | |
856 | wait_for_completion(&c_idle.done); | |
857 | } | |
858 | ||
859 | if (IS_ERR(c_idle.idle)) { | |
860 | printk("failed fork for CPU %d\n", cpu); | |
861 | return PTR_ERR(c_idle.idle); | |
862 | } | |
863 | ||
864 | set_idle_for_cpu(cpu, c_idle.idle); | |
865 | do_rest: | |
866 | #ifdef CONFIG_X86_32 | |
867 | per_cpu(current_task, cpu) = c_idle.idle; | |
868 | init_gdt(cpu); | |
cb3c8b90 | 869 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
870 | irq_ctx_init(cpu); |
871 | #else | |
872 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
cb3c8b90 GOC |
873 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
874 | #endif | |
a939098a | 875 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 876 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 877 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
878 | |
879 | /* start_ip had better be page-aligned! */ | |
880 | start_ip = setup_trampoline(); | |
881 | ||
882 | /* So we see what's up */ | |
823b259b | 883 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
884 | cpu, apicid, start_ip); |
885 | ||
886 | /* | |
887 | * This grunge runs the startup process for | |
888 | * the targeted processor. | |
889 | */ | |
890 | ||
891 | atomic_set(&init_deasserted, 0); | |
892 | ||
34d05591 | 893 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 894 | |
cfc1b9a6 | 895 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 896 | |
34d05591 JS |
897 | store_NMI_vector(&nmi_high, &nmi_low); |
898 | ||
899 | smpboot_setup_warm_reset_vector(start_ip); | |
900 | /* | |
901 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
902 | */ |
903 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
904 | apic_write(APIC_ESR, 0); | |
905 | apic_read(APIC_ESR); | |
906 | } | |
34d05591 | 907 | } |
cb3c8b90 | 908 | |
cb3c8b90 GOC |
909 | /* |
910 | * Starting actual IPI sequence... | |
911 | */ | |
912 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
913 | ||
914 | if (!boot_error) { | |
915 | /* | |
916 | * allow APs to start initializing. | |
917 | */ | |
cfc1b9a6 | 918 | pr_debug("Before Callout %d.\n", cpu); |
cb3c8b90 | 919 | cpu_set(cpu, cpu_callout_map); |
cfc1b9a6 | 920 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
921 | |
922 | /* | |
923 | * Wait 5s total for a response | |
924 | */ | |
925 | for (timeout = 0; timeout < 50000; timeout++) { | |
926 | if (cpu_isset(cpu, cpu_callin_map)) | |
927 | break; /* It has booted */ | |
928 | udelay(100); | |
929 | } | |
930 | ||
931 | if (cpu_isset(cpu, cpu_callin_map)) { | |
932 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
cfc1b9a6 | 933 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
934 | printk(KERN_INFO "CPU%d: ", cpu); |
935 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 936 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
937 | } else { |
938 | boot_error = 1; | |
939 | if (*((volatile unsigned char *)trampoline_base) | |
940 | == 0xA5) | |
941 | /* trampoline started but...? */ | |
942 | printk(KERN_ERR "Stuck ??\n"); | |
943 | else | |
944 | /* trampoline code not run */ | |
945 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
946 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
947 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
948 | } |
949 | } | |
6f585e01 | 950 | #ifdef CONFIG_X86_64 |
3461b0af | 951 | restore_state: |
6f585e01 | 952 | #endif |
cb3c8b90 GOC |
953 | if (boot_error) { |
954 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 955 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
cb3c8b90 GOC |
956 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ |
957 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
cb3c8b90 GOC |
958 | cpu_clear(cpu, cpu_present_map); |
959 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
960 | } | |
961 | ||
962 | /* mark "stuck" area as not stuck */ | |
963 | *((volatile unsigned long *)trampoline_base) = 0; | |
964 | ||
63d38198 AK |
965 | /* |
966 | * Cleanup possible dangling ends... | |
967 | */ | |
968 | smpboot_restore_warm_reset_vector(); | |
969 | ||
cb3c8b90 GOC |
970 | return boot_error; |
971 | } | |
972 | ||
973 | int __cpuinit native_cpu_up(unsigned int cpu) | |
974 | { | |
975 | int apicid = cpu_present_to_apicid(cpu); | |
976 | unsigned long flags; | |
977 | int err; | |
978 | ||
979 | WARN_ON(irqs_disabled()); | |
980 | ||
cfc1b9a6 | 981 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
982 | |
983 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
984 | !physid_isset(apicid, phys_cpu_present_map)) { | |
985 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
989 | /* | |
990 | * Already booted CPU? | |
991 | */ | |
992 | if (cpu_isset(cpu, cpu_callin_map)) { | |
cfc1b9a6 | 993 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
994 | return -ENOSYS; |
995 | } | |
996 | ||
997 | /* | |
998 | * Save current MTRR state in case it was changed since early boot | |
999 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1000 | */ | |
1001 | mtrr_save_state(); | |
1002 | ||
1003 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1004 | ||
1005 | #ifdef CONFIG_X86_32 | |
1006 | /* init low mem mapping */ | |
68db065c | 1007 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 1008 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 1009 | flush_tlb_all(); |
61165d7a | 1010 | low_mappings = 1; |
cb3c8b90 GOC |
1011 | |
1012 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
1013 | |
1014 | zap_low_mappings(); | |
1015 | low_mappings = 0; | |
1016 | #else | |
1017 | err = do_boot_cpu(apicid, cpu); | |
1018 | #endif | |
1019 | if (err) { | |
cfc1b9a6 | 1020 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 1021 | return -EIO; |
cb3c8b90 GOC |
1022 | } |
1023 | ||
1024 | /* | |
1025 | * Check TSC synchronization with the AP (keep irqs disabled | |
1026 | * while doing so): | |
1027 | */ | |
1028 | local_irq_save(flags); | |
1029 | check_tsc_sync_source(cpu); | |
1030 | local_irq_restore(flags); | |
1031 | ||
7c04e64a | 1032 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1033 | cpu_relax(); |
1034 | touch_nmi_watchdog(); | |
1035 | } | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
8aef135c GOC |
1040 | /* |
1041 | * Fall back to non SMP mode after errors. | |
1042 | * | |
1043 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1044 | */ | |
1045 | static __init void disable_smp(void) | |
1046 | { | |
1047 | cpu_present_map = cpumask_of_cpu(0); | |
1048 | cpu_possible_map = cpumask_of_cpu(0); | |
8aef135c | 1049 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 1050 | |
8aef135c | 1051 | if (smp_found_config) |
b6df1b8b | 1052 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1053 | else |
b6df1b8b | 1054 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c GOC |
1055 | map_cpu_to_logical_apicid(); |
1056 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1057 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * Various sanity checks. | |
1062 | */ | |
1063 | static int __init smp_sanity_check(unsigned max_cpus) | |
1064 | { | |
ac23d4ee | 1065 | preempt_disable(); |
a58f03b0 YL |
1066 | |
1067 | #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32) | |
1068 | if (def_to_bigsmp && nr_cpu_ids > 8) { | |
1069 | unsigned int cpu; | |
1070 | unsigned nr; | |
1071 | ||
1072 | printk(KERN_WARNING | |
1073 | "More than 8 CPUs detected - skipping them.\n" | |
1074 | "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); | |
1075 | ||
1076 | nr = 0; | |
1077 | for_each_present_cpu(cpu) { | |
1078 | if (nr >= 8) | |
1079 | cpu_clear(cpu, cpu_present_map); | |
1080 | nr++; | |
1081 | } | |
1082 | ||
1083 | nr = 0; | |
1084 | for_each_possible_cpu(cpu) { | |
1085 | if (nr >= 8) | |
1086 | cpu_clear(cpu, cpu_possible_map); | |
1087 | nr++; | |
1088 | } | |
1089 | ||
1090 | nr_cpu_ids = 8; | |
1091 | } | |
1092 | #endif | |
1093 | ||
8aef135c GOC |
1094 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1095 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1096 | "by the BIOS.\n", hard_smp_processor_id()); | |
1097 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1098 | } | |
1099 | ||
1100 | /* | |
1101 | * If we couldn't find an SMP configuration at boot time, | |
1102 | * get out of here now! | |
1103 | */ | |
1104 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1105 | preempt_enable(); |
8aef135c GOC |
1106 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1107 | disable_smp(); | |
1108 | if (APIC_init_uniprocessor()) | |
1109 | printk(KERN_NOTICE "Local APIC not detected." | |
1110 | " Using dummy APIC emulation.\n"); | |
1111 | return -1; | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Should not be necessary because the MP table should list the boot | |
1116 | * CPU too, but we do it for the sake of robustness anyway. | |
1117 | */ | |
1118 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1119 | printk(KERN_NOTICE | |
1120 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1121 | boot_cpu_physical_apicid); | |
1122 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1123 | } | |
ac23d4ee | 1124 | preempt_enable(); |
8aef135c GOC |
1125 | |
1126 | /* | |
1127 | * If we couldn't find a local APIC, then get out of here now! | |
1128 | */ | |
1129 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1130 | !cpu_has_apic) { | |
1131 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1132 | boot_cpu_physical_apicid); | |
1133 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1134 | "(tell your hw vendor)\n"); | |
1135 | smpboot_clear_io_apic(); | |
1136 | return -1; | |
1137 | } | |
1138 | ||
1139 | verify_local_APIC(); | |
1140 | ||
1141 | /* | |
1142 | * If SMP should be disabled, then really disable it! | |
1143 | */ | |
1144 | if (!max_cpus) { | |
73d08e63 | 1145 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1146 | smpboot_clear_io_apic(); |
d54db1ac MR |
1147 | |
1148 | localise_nmi_watchdog(); | |
1149 | ||
e90955c2 | 1150 | connect_bsp_APIC(); |
e90955c2 JB |
1151 | setup_local_APIC(); |
1152 | end_local_APIC_setup(); | |
8aef135c GOC |
1153 | return -1; |
1154 | } | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static void __init smp_cpu_index_default(void) | |
1160 | { | |
1161 | int i; | |
1162 | struct cpuinfo_x86 *c; | |
1163 | ||
7c04e64a | 1164 | for_each_possible_cpu(i) { |
8aef135c GOC |
1165 | c = &cpu_data(i); |
1166 | /* mark all to hotplug */ | |
1167 | c->cpu_index = NR_CPUS; | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1173 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1174 | */ | |
1175 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1176 | { | |
deef3250 | 1177 | preempt_disable(); |
8aef135c GOC |
1178 | smp_cpu_index_default(); |
1179 | current_cpu_data = boot_cpu_data; | |
1180 | cpu_callin_map = cpumask_of_cpu(0); | |
1181 | mb(); | |
1182 | /* | |
1183 | * Setup boot CPU information | |
1184 | */ | |
1185 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1186 | #ifdef CONFIG_X86_32 |
8aef135c | 1187 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1188 | #endif |
8aef135c GOC |
1189 | current_thread_info()->cpu = 0; /* needed? */ |
1190 | set_cpu_sibling_map(0); | |
1191 | ||
6e1cb38a SS |
1192 | #ifdef CONFIG_X86_64 |
1193 | enable_IR_x2apic(); | |
1194 | setup_apic_routing(); | |
1195 | #endif | |
1196 | ||
8aef135c GOC |
1197 | if (smp_sanity_check(max_cpus) < 0) { |
1198 | printk(KERN_INFO "SMP disabled\n"); | |
1199 | disable_smp(); | |
deef3250 | 1200 | goto out; |
8aef135c GOC |
1201 | } |
1202 | ||
ac23d4ee | 1203 | preempt_disable(); |
4c9961d5 | 1204 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1205 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1206 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1207 | /* Or can we switch back to PIC here? */ |
1208 | } | |
ac23d4ee | 1209 | preempt_enable(); |
8aef135c | 1210 | |
8aef135c | 1211 | connect_bsp_APIC(); |
b5841765 | 1212 | |
8aef135c GOC |
1213 | /* |
1214 | * Switch from PIC to APIC mode. | |
1215 | */ | |
1216 | setup_local_APIC(); | |
1217 | ||
1218 | #ifdef CONFIG_X86_64 | |
1219 | /* | |
1220 | * Enable IO APIC before setting up error vector | |
1221 | */ | |
1222 | if (!skip_ioapic_setup && nr_ioapics) | |
1223 | enable_IO_APIC(); | |
1224 | #endif | |
1225 | end_local_APIC_setup(); | |
1226 | ||
1227 | map_cpu_to_logical_apicid(); | |
1228 | ||
1229 | setup_portio_remap(); | |
1230 | ||
1231 | smpboot_setup_io_apic(); | |
1232 | /* | |
1233 | * Set up local APIC timer on boot CPU. | |
1234 | */ | |
1235 | ||
1236 | printk(KERN_INFO "CPU%d: ", 0); | |
1237 | print_cpu_info(&cpu_data(0)); | |
1238 | setup_boot_clock(); | |
c4bd1fda MS |
1239 | |
1240 | if (is_uv_system()) | |
1241 | uv_system_init(); | |
deef3250 IM |
1242 | out: |
1243 | preempt_enable(); | |
8aef135c | 1244 | } |
a8db8453 GOC |
1245 | /* |
1246 | * Early setup to make printk work. | |
1247 | */ | |
1248 | void __init native_smp_prepare_boot_cpu(void) | |
1249 | { | |
1250 | int me = smp_processor_id(); | |
1251 | #ifdef CONFIG_X86_32 | |
1252 | init_gdt(me); | |
a8db8453 | 1253 | #endif |
a939098a | 1254 | switch_to_new_gdt(); |
a8db8453 GOC |
1255 | /* already set me in cpu_online_map in boot_cpu_init() */ |
1256 | cpu_set(me, cpu_callout_map); | |
1257 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1258 | } | |
1259 | ||
83f7eb9c GOC |
1260 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1261 | { | |
cfc1b9a6 | 1262 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1263 | |
1264 | impress_friends(); | |
1265 | smp_checks(); | |
1266 | #ifdef CONFIG_X86_IO_APIC | |
1267 | setup_ioapic_dest(); | |
1268 | #endif | |
1269 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1270 | } |
1271 | ||
68a1c3f8 GC |
1272 | /* |
1273 | * cpu_possible_map should be static, it cannot change as cpu's | |
1274 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1275 | * are allocated by some modules at init time, and dont expect to | |
1276 | * do this dynamically on cpu arrival/departure. | |
1277 | * cpu_present_map on the other hand can change dynamically. | |
1278 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1279 | * behaviour, which is cpu_possible == cpu_present. | |
1280 | * - Ashok Raj | |
1281 | * | |
1282 | * Three ways to find out the number of additional hotplug CPUs: | |
1283 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1284 | * - The user can overwrite it with additional_cpus=NUM | |
1285 | * - Otherwise don't reserve additional CPUs. | |
1286 | * We do this because additional CPUs waste a lot of memory. | |
1287 | * -AK | |
1288 | */ | |
1289 | __init void prefill_possible_map(void) | |
1290 | { | |
cb48bb59 | 1291 | int i, possible; |
68a1c3f8 | 1292 | |
329513a3 YL |
1293 | /* no processor from mptable or madt */ |
1294 | if (!num_processors) | |
1295 | num_processors = 1; | |
1296 | ||
cb48bb59 | 1297 | possible = num_processors + disabled_cpus; |
68a1c3f8 GC |
1298 | if (possible > NR_CPUS) |
1299 | possible = NR_CPUS; | |
1300 | ||
1301 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1302 | possible, max_t(int, possible - num_processors, 0)); | |
1303 | ||
1304 | for (i = 0; i < possible; i++) | |
1305 | cpu_set(i, cpu_possible_map); | |
3461b0af MT |
1306 | |
1307 | nr_cpu_ids = possible; | |
68a1c3f8 | 1308 | } |
69c18c15 | 1309 | |
14adf855 CE |
1310 | #ifdef CONFIG_HOTPLUG_CPU |
1311 | ||
1312 | static void remove_siblinginfo(int cpu) | |
1313 | { | |
1314 | int sibling; | |
1315 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1316 | ||
1317 | for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) { | |
1318 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1319 | /*/ | |
1320 | * last thread sibling in this cpu core going down | |
1321 | */ | |
1322 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1323 | cpu_data(sibling).booted_cores--; | |
1324 | } | |
1325 | ||
1326 | for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu)) | |
1327 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1328 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1329 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1330 | c->phys_proc_id = 0; | |
1331 | c->cpu_core_id = 0; | |
1332 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1333 | } | |
1334 | ||
69c18c15 GC |
1335 | static void __ref remove_cpu_from_maps(int cpu) |
1336 | { | |
1337 | cpu_clear(cpu, cpu_online_map); | |
69c18c15 GC |
1338 | cpu_clear(cpu, cpu_callout_map); |
1339 | cpu_clear(cpu, cpu_callin_map); | |
1340 | /* was set by cpu_init() */ | |
29cbeb0e | 1341 | cpu_clear(cpu, cpu_initialized); |
23ca4bba | 1342 | numa_remove_cpu(cpu); |
69c18c15 GC |
1343 | } |
1344 | ||
8227dce7 | 1345 | void cpu_disable_common(void) |
69c18c15 GC |
1346 | { |
1347 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1348 | /* |
1349 | * HACK: | |
1350 | * Allow any queued timer interrupts to get serviced | |
1351 | * This is only a temporary solution until we cleanup | |
1352 | * fixup_irqs as we do for IA64. | |
1353 | */ | |
1354 | local_irq_enable(); | |
1355 | mdelay(1); | |
1356 | ||
1357 | local_irq_disable(); | |
1358 | remove_siblinginfo(cpu); | |
1359 | ||
1360 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1361 | lock_vector_lock(); |
69c18c15 | 1362 | remove_cpu_from_maps(cpu); |
d388e5fd | 1363 | unlock_vector_lock(); |
69c18c15 | 1364 | fixup_irqs(cpu_online_map); |
8227dce7 AN |
1365 | } |
1366 | ||
1367 | int native_cpu_disable(void) | |
1368 | { | |
1369 | int cpu = smp_processor_id(); | |
1370 | ||
1371 | /* | |
1372 | * Perhaps use cpufreq to drop frequency, but that could go | |
1373 | * into generic code. | |
1374 | * | |
1375 | * We won't take down the boot processor on i386 due to some | |
1376 | * interrupts only being able to be serviced by the BSP. | |
1377 | * Especially so if we're not using an IOAPIC -zwane | |
1378 | */ | |
1379 | if (cpu == 0) | |
1380 | return -EBUSY; | |
1381 | ||
1382 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1383 | stop_apic_nmi_watchdog(NULL); | |
1384 | clear_local_APIC(); | |
1385 | ||
1386 | cpu_disable_common(); | |
69c18c15 GC |
1387 | return 0; |
1388 | } | |
1389 | ||
93be71b6 | 1390 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1391 | { |
1392 | /* We don't do anything here: idle task is faking death itself. */ | |
1393 | unsigned int i; | |
1394 | ||
1395 | for (i = 0; i < 10; i++) { | |
1396 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1397 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1398 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1399 | if (1 == num_online_cpus()) | |
1400 | alternatives_smp_switch(0); | |
1401 | return; | |
1402 | } | |
1403 | msleep(100); | |
1404 | } | |
1405 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1406 | } | |
a21f5d88 AN |
1407 | |
1408 | void play_dead_common(void) | |
1409 | { | |
1410 | idle_task_exit(); | |
1411 | reset_lazy_tlbstate(); | |
1412 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1413 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1414 | |
1415 | mb(); | |
1416 | /* Ack it */ | |
1417 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1418 | ||
1419 | /* | |
1420 | * With physical CPU hotplug, we should halt the cpu | |
1421 | */ | |
1422 | local_irq_disable(); | |
1423 | } | |
1424 | ||
1425 | void native_play_dead(void) | |
1426 | { | |
1427 | play_dead_common(); | |
1428 | wbinvd_halt(); | |
1429 | } | |
1430 | ||
69c18c15 | 1431 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1432 | int native_cpu_disable(void) |
69c18c15 GC |
1433 | { |
1434 | return -ENOSYS; | |
1435 | } | |
1436 | ||
93be71b6 | 1437 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1438 | { |
1439 | /* We said "no" in __cpu_disable */ | |
1440 | BUG(); | |
1441 | } | |
a21f5d88 AN |
1442 | |
1443 | void native_play_dead(void) | |
1444 | { | |
1445 | BUG(); | |
1446 | } | |
1447 | ||
68a1c3f8 | 1448 | #endif |