Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
1164dd00 | 76 | #include <asm/smpboot_hooks.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
48927bbb | 78 | #include <asm/realmode.h> |
646e29a1 | 79 | #include <asm/misc.h> |
48927bbb | 80 | |
a8db8453 GOC |
81 | /* State of each CPU */ |
82 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
83 | ||
a355352b GC |
84 | /* Number of siblings per CPU package */ |
85 | int smp_num_siblings = 1; | |
86 | EXPORT_SYMBOL(smp_num_siblings); | |
87 | ||
88 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 89 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 90 | |
a355352b | 91 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 92 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
93 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
94 | ||
95 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 96 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
97 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
98 | ||
0816b0f0 | 99 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 100 | |
a355352b GC |
101 | /* Per CPU bogomips and other parameters */ |
102 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
103 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 104 | |
2b6163bf | 105 | atomic_t init_deasserted; |
cb3c8b90 | 106 | |
cb3c8b90 | 107 | /* |
30106c17 FY |
108 | * Report back to the Boot Processor during boot time or to the caller processor |
109 | * during CPU online. | |
cb3c8b90 | 110 | */ |
148f9bb8 | 111 | static void smp_callin(void) |
cb3c8b90 GOC |
112 | { |
113 | int cpuid, phys_id; | |
114 | unsigned long timeout; | |
115 | ||
116 | /* | |
117 | * If waken up by an INIT in an 82489DX configuration | |
118 | * we may get here before an INIT-deassert IPI reaches | |
119 | * our local APIC. We have to wait for the IPI or we'll | |
120 | * lock up on an APIC access. | |
e1c467e6 FY |
121 | * |
122 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 123 | */ |
e1c467e6 | 124 | cpuid = smp_processor_id(); |
465822cf DR |
125 | if (apic->wait_for_init_deassert && cpuid) |
126 | while (!atomic_read(&init_deasserted)) | |
127 | cpu_relax(); | |
cb3c8b90 GOC |
128 | |
129 | /* | |
130 | * (This works even if the APIC is not enabled.) | |
131 | */ | |
4c9961d5 | 132 | phys_id = read_apic_id(); |
c2d1cec1 | 133 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
134 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
135 | phys_id, cpuid); | |
136 | } | |
cfc1b9a6 | 137 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
138 | |
139 | /* | |
140 | * STARTUP IPIs are fragile beasts as they might sometimes | |
141 | * trigger some glue motherboard logic. Complete APIC bus | |
142 | * silence for 1 second, this overestimates the time the | |
143 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
144 | * by a factor of two. This should be enough. | |
145 | */ | |
146 | ||
147 | /* | |
148 | * Waiting 2s total for startup (udelay is not yet working) | |
149 | */ | |
150 | timeout = jiffies + 2*HZ; | |
151 | while (time_before(jiffies, timeout)) { | |
152 | /* | |
153 | * Has the boot CPU finished it's STARTUP sequence? | |
154 | */ | |
c2d1cec1 | 155 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
156 | break; |
157 | cpu_relax(); | |
158 | } | |
159 | ||
160 | if (!time_before(jiffies, timeout)) { | |
161 | panic("%s: CPU%d started up but did not get a callout!\n", | |
162 | __func__, cpuid); | |
163 | } | |
164 | ||
165 | /* | |
166 | * the boot CPU has finished the init stage and is spinning | |
167 | * on callin_map until we finish. We are free to set up this | |
168 | * CPU, first the APIC. (this is probably redundant on most | |
169 | * boards) | |
170 | */ | |
171 | ||
c767a54b | 172 | pr_debug("CALLIN, before setup_local_APIC()\n"); |
333344d9 IM |
173 | if (apic->smp_callin_clear_local_apic) |
174 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
175 | setup_local_APIC(); |
176 | end_local_APIC_setup(); | |
cb3c8b90 | 177 | |
9d133e5d SS |
178 | /* |
179 | * Need to setup vector mappings before we enable interrupts. | |
180 | */ | |
36e9e1ea | 181 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
182 | |
183 | /* | |
184 | * Save our processor parameters. Note: this information | |
185 | * is needed for clock calibration. | |
186 | */ | |
187 | smp_store_cpu_info(cpuid); | |
188 | ||
cb3c8b90 GOC |
189 | /* |
190 | * Get our bogomips. | |
b565201c JS |
191 | * Update loops_per_jiffy in cpu_data. Previous call to |
192 | * smp_store_cpu_info() stored a value that is close but not as | |
193 | * accurate as the value just calculated. | |
cb3c8b90 | 194 | */ |
cb3c8b90 | 195 | calibrate_delay(); |
b565201c | 196 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 197 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 198 | |
5ef428c4 AK |
199 | /* |
200 | * This must be done before setting cpu_online_mask | |
201 | * or calling notify_cpu_starting. | |
202 | */ | |
203 | set_cpu_sibling_map(raw_smp_processor_id()); | |
204 | wmb(); | |
205 | ||
85257024 PZ |
206 | notify_cpu_starting(cpuid); |
207 | ||
cb3c8b90 GOC |
208 | /* |
209 | * Allow the master to continue. | |
210 | */ | |
c2d1cec1 | 211 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
212 | } |
213 | ||
e1c467e6 FY |
214 | static int cpu0_logical_apicid; |
215 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
216 | /* |
217 | * Activate a secondary processor. | |
218 | */ | |
148f9bb8 | 219 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
220 | { |
221 | /* | |
222 | * Don't put *anything* before cpu_init(), SMP booting is too | |
223 | * fragile that we want to limit the things done here to the | |
224 | * most necessary things. | |
225 | */ | |
b40827fa | 226 | cpu_init(); |
df156f90 | 227 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
228 | preempt_disable(); |
229 | smp_callin(); | |
fd89a137 | 230 | |
e1c467e6 FY |
231 | enable_start_cpu0 = 0; |
232 | ||
fd89a137 | 233 | #ifdef CONFIG_X86_32 |
b40827fa | 234 | /* switch away from the initial page table */ |
fd89a137 JR |
235 | load_cr3(swapper_pg_dir); |
236 | __flush_tlb_all(); | |
237 | #endif | |
238 | ||
bbc2ff6a GOC |
239 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
240 | barrier(); | |
241 | /* | |
242 | * Check TSC synchronization with the BP: | |
243 | */ | |
244 | check_tsc_sync_target(); | |
245 | ||
bbc2ff6a | 246 | /* |
d388e5fd EB |
247 | * We need to hold vector_lock so there the set of online cpus |
248 | * does not change while we are assigning vectors to cpus. Holding | |
249 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 250 | */ |
d388e5fd | 251 | lock_vector_lock(); |
c2d1cec1 | 252 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 253 | unlock_vector_lock(); |
bbc2ff6a | 254 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 255 | x86_platform.nmi_init(); |
bbc2ff6a | 256 | |
0cefa5b9 MS |
257 | /* enable local interrupts */ |
258 | local_irq_enable(); | |
259 | ||
35f720c5 JP |
260 | /* to prevent fake stack check failure in clock setup */ |
261 | boot_init_stack_canary(); | |
0cefa5b9 | 262 | |
736decac | 263 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
264 | |
265 | wmb(); | |
7d1a9417 | 266 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
267 | } |
268 | ||
30106c17 FY |
269 | void __init smp_store_boot_cpu_info(void) |
270 | { | |
271 | int id = 0; /* CPU 0 */ | |
272 | struct cpuinfo_x86 *c = &cpu_data(id); | |
273 | ||
274 | *c = boot_cpu_data; | |
275 | c->cpu_index = id; | |
276 | } | |
277 | ||
1d89a7f0 GOC |
278 | /* |
279 | * The bootstrap kernel entry code has set these up. Save them for | |
280 | * a given CPU | |
281 | */ | |
148f9bb8 | 282 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
283 | { |
284 | struct cpuinfo_x86 *c = &cpu_data(id); | |
285 | ||
b3d7336d | 286 | *c = boot_cpu_data; |
1d89a7f0 | 287 | c->cpu_index = id; |
30106c17 FY |
288 | /* |
289 | * During boot time, CPU0 has this setup already. Save the info when | |
290 | * bringing up AP or offlined CPU0. | |
291 | */ | |
292 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
293 | } |
294 | ||
148f9bb8 | 295 | static bool |
316ad248 | 296 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 297 | { |
316ad248 PZ |
298 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
299 | ||
300 | return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), | |
301 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " | |
302 | "[node: %d != %d]. Ignoring dependency.\n", | |
303 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
304 | } | |
305 | ||
306 | #define link_mask(_m, c1, c2) \ | |
307 | do { \ | |
308 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
309 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
310 | } while (0) | |
311 | ||
148f9bb8 | 312 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 313 | { |
193f3fcb | 314 | if (cpu_has_topoext) { |
316ad248 PZ |
315 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
316 | ||
317 | if (c->phys_proc_id == o->phys_proc_id && | |
318 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
319 | c->compute_unit_id == o->compute_unit_id) | |
320 | return topology_sane(c, o, "smt"); | |
321 | ||
322 | } else if (c->phys_proc_id == o->phys_proc_id && | |
323 | c->cpu_core_id == o->cpu_core_id) { | |
324 | return topology_sane(c, o, "smt"); | |
325 | } | |
326 | ||
327 | return false; | |
328 | } | |
329 | ||
148f9bb8 | 330 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
331 | { |
332 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
333 | ||
334 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
335 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
336 | return topology_sane(c, o, "llc"); | |
337 | ||
338 | return false; | |
d4fbe4f0 AH |
339 | } |
340 | ||
148f9bb8 | 341 | static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 342 | { |
161270fc BP |
343 | if (c->phys_proc_id == o->phys_proc_id) { |
344 | if (cpu_has(c, X86_FEATURE_AMD_DCM)) | |
345 | return true; | |
316ad248 | 346 | |
161270fc BP |
347 | return topology_sane(c, o, "mc"); |
348 | } | |
316ad248 PZ |
349 | return false; |
350 | } | |
1d89a7f0 | 351 | |
148f9bb8 | 352 | void set_cpu_sibling_map(int cpu) |
768d9505 | 353 | { |
316ad248 | 354 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 355 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 356 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
357 | struct cpuinfo_x86 *o; |
358 | int i; | |
768d9505 | 359 | |
c2d1cec1 | 360 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 361 | |
b0bc225d | 362 | if (!has_mp) { |
c2d1cec1 | 363 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
364 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
365 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
366 | c->booted_cores = 1; |
367 | return; | |
368 | } | |
369 | ||
c2d1cec1 | 370 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
371 | o = &cpu_data(i); |
372 | ||
373 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
374 | link_mask(sibling, cpu, i); | |
375 | ||
b0bc225d | 376 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
377 | link_mask(llc_shared, cpu, i); |
378 | ||
ceb1cbac KB |
379 | } |
380 | ||
381 | /* | |
382 | * This needs a separate iteration over the cpus because we rely on all | |
383 | * cpu_sibling_mask links to be set-up. | |
384 | */ | |
385 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
386 | o = &cpu_data(i); | |
387 | ||
b0bc225d | 388 | if ((i == cpu) || (has_mp && match_mc(c, o))) { |
316ad248 PZ |
389 | link_mask(core, cpu, i); |
390 | ||
768d9505 GC |
391 | /* |
392 | * Does this new cpu bringup a new core? | |
393 | */ | |
c2d1cec1 | 394 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
395 | /* |
396 | * for each core in package, increment | |
397 | * the booted_cores for this new cpu | |
398 | */ | |
c2d1cec1 | 399 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
400 | c->booted_cores++; |
401 | /* | |
402 | * increment the core count for all | |
403 | * the other cpus in this package | |
404 | */ | |
405 | if (i != cpu) | |
406 | cpu_data(i).booted_cores++; | |
407 | } else if (i != cpu && !c->booted_cores) | |
408 | c->booted_cores = cpu_data(i).booted_cores; | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
70708a18 | 413 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 414 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 415 | { |
9f646389 | 416 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
417 | } |
418 | ||
a4928cff | 419 | static void impress_friends(void) |
904541e2 GOC |
420 | { |
421 | int cpu; | |
422 | unsigned long bogosum = 0; | |
423 | /* | |
424 | * Allow the user to impress friends. | |
425 | */ | |
c767a54b | 426 | pr_debug("Before bogomips\n"); |
904541e2 | 427 | for_each_possible_cpu(cpu) |
c2d1cec1 | 428 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 429 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 430 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 431 | num_online_cpus(), |
904541e2 GOC |
432 | bogosum/(500000/HZ), |
433 | (bogosum/(5000/HZ))%100); | |
434 | ||
c767a54b | 435 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
436 | } |
437 | ||
569712b2 | 438 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
439 | { |
440 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 441 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
442 | int timeout; |
443 | u32 status; | |
444 | ||
c767a54b | 445 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
446 | |
447 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 448 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
449 | |
450 | /* | |
451 | * Wait for idle. | |
452 | */ | |
453 | status = safe_apic_wait_icr_idle(); | |
454 | if (status) | |
c767a54b | 455 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 456 | |
1b374e4d | 457 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
458 | |
459 | timeout = 0; | |
460 | do { | |
461 | udelay(100); | |
462 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
463 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
464 | ||
465 | switch (status) { | |
466 | case APIC_ICR_RR_VALID: | |
467 | status = apic_read(APIC_RRR); | |
c767a54b | 468 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
469 | break; |
470 | default: | |
c767a54b | 471 | pr_cont("failed\n"); |
cb3c8b90 GOC |
472 | } |
473 | } | |
474 | } | |
475 | ||
cb3c8b90 GOC |
476 | /* |
477 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
478 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
479 | * won't ... remember to clear down the APIC, etc later. | |
480 | */ | |
148f9bb8 | 481 | int |
e1c467e6 | 482 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
483 | { |
484 | unsigned long send_status, accept_status = 0; | |
485 | int maxlvt; | |
486 | ||
487 | /* Target chip */ | |
cb3c8b90 GOC |
488 | /* Boot on the stack */ |
489 | /* Kick the second */ | |
e1c467e6 | 490 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 491 | |
cfc1b9a6 | 492 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
493 | send_status = safe_apic_wait_icr_idle(); |
494 | ||
495 | /* | |
496 | * Give the other CPU some time to accept the IPI. | |
497 | */ | |
498 | udelay(200); | |
569712b2 | 499 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
500 | maxlvt = lapic_get_maxlvt(); |
501 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
502 | apic_write(APIC_ESR, 0); | |
503 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
504 | } | |
c767a54b | 505 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
506 | |
507 | if (send_status) | |
c767a54b | 508 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 509 | if (accept_status) |
c767a54b | 510 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
511 | |
512 | return (send_status | accept_status); | |
513 | } | |
cb3c8b90 | 514 | |
148f9bb8 | 515 | static int |
569712b2 | 516 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
517 | { |
518 | unsigned long send_status, accept_status = 0; | |
519 | int maxlvt, num_starts, j; | |
520 | ||
593f4a78 MR |
521 | maxlvt = lapic_get_maxlvt(); |
522 | ||
cb3c8b90 GOC |
523 | /* |
524 | * Be paranoid about clearing APIC errors. | |
525 | */ | |
526 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
527 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
528 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
529 | apic_read(APIC_ESR); |
530 | } | |
531 | ||
c767a54b | 532 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
533 | |
534 | /* | |
535 | * Turn INIT on target chip | |
536 | */ | |
cb3c8b90 GOC |
537 | /* |
538 | * Send IPI | |
539 | */ | |
1b374e4d SS |
540 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
541 | phys_apicid); | |
cb3c8b90 | 542 | |
cfc1b9a6 | 543 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
544 | send_status = safe_apic_wait_icr_idle(); |
545 | ||
546 | mdelay(10); | |
547 | ||
c767a54b | 548 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
549 | |
550 | /* Target chip */ | |
cb3c8b90 | 551 | /* Send IPI */ |
1b374e4d | 552 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 553 | |
cfc1b9a6 | 554 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
555 | send_status = safe_apic_wait_icr_idle(); |
556 | ||
557 | mb(); | |
558 | atomic_set(&init_deasserted, 1); | |
559 | ||
560 | /* | |
561 | * Should we send STARTUP IPIs ? | |
562 | * | |
563 | * Determine this based on the APIC version. | |
564 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
565 | */ | |
566 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
567 | num_starts = 2; | |
568 | else | |
569 | num_starts = 0; | |
570 | ||
571 | /* | |
572 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
573 | * target processor state. | |
574 | */ | |
575 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 576 | stack_start); |
cb3c8b90 GOC |
577 | |
578 | /* | |
579 | * Run STARTUP IPI loop. | |
580 | */ | |
c767a54b | 581 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 582 | |
cb3c8b90 | 583 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 584 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
585 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
586 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 587 | apic_read(APIC_ESR); |
c767a54b | 588 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
589 | |
590 | /* | |
591 | * STARTUP IPI | |
592 | */ | |
593 | ||
594 | /* Target chip */ | |
cb3c8b90 GOC |
595 | /* Boot on the stack */ |
596 | /* Kick the second */ | |
1b374e4d SS |
597 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
598 | phys_apicid); | |
cb3c8b90 GOC |
599 | |
600 | /* | |
601 | * Give the other CPU some time to accept the IPI. | |
602 | */ | |
603 | udelay(300); | |
604 | ||
c767a54b | 605 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 606 | |
cfc1b9a6 | 607 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
608 | send_status = safe_apic_wait_icr_idle(); |
609 | ||
610 | /* | |
611 | * Give the other CPU some time to accept the IPI. | |
612 | */ | |
613 | udelay(200); | |
593f4a78 | 614 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 615 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
616 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
617 | if (send_status || accept_status) | |
618 | break; | |
619 | } | |
c767a54b | 620 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
621 | |
622 | if (send_status) | |
c767a54b | 623 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 624 | if (accept_status) |
c767a54b | 625 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
626 | |
627 | return (send_status | accept_status); | |
628 | } | |
cb3c8b90 | 629 | |
a17bce4d BP |
630 | void smp_announce(void) |
631 | { | |
632 | int num_nodes = num_online_nodes(); | |
633 | ||
634 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
635 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
636 | } | |
637 | ||
2eaad1fd | 638 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 639 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
640 | { |
641 | static int current_node = -1; | |
4adc8b71 | 642 | int node = early_cpu_to_node(cpu); |
a17bce4d | 643 | static int width, node_width; |
646e29a1 BP |
644 | |
645 | if (!width) | |
646 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 647 | |
a17bce4d BP |
648 | if (!node_width) |
649 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
650 | ||
651 | if (cpu == 1) | |
652 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
653 | ||
2eaad1fd MT |
654 | if (system_state == SYSTEM_BOOTING) { |
655 | if (node != current_node) { | |
656 | if (current_node > (-1)) | |
a17bce4d | 657 | pr_cont("\n"); |
2eaad1fd | 658 | current_node = node; |
a17bce4d BP |
659 | |
660 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
661 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 662 | } |
646e29a1 BP |
663 | |
664 | /* Add padding for the BSP */ | |
665 | if (cpu == 1) | |
666 | pr_cont("%*s", width + 1, " "); | |
667 | ||
668 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
669 | ||
2eaad1fd MT |
670 | } else |
671 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
672 | node, cpu, apicid); | |
673 | } | |
674 | ||
e1c467e6 FY |
675 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
676 | { | |
677 | int cpu; | |
678 | ||
679 | cpu = smp_processor_id(); | |
680 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
681 | return NMI_HANDLED; | |
682 | ||
683 | return NMI_DONE; | |
684 | } | |
685 | ||
686 | /* | |
687 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
688 | * | |
689 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
690 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
691 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
692 | * | |
693 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
694 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
695 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
696 | * real platform and request are available. | |
697 | */ | |
148f9bb8 | 698 | static int |
e1c467e6 FY |
699 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
700 | int *cpu0_nmi_registered) | |
701 | { | |
702 | int id; | |
703 | int boot_error; | |
704 | ||
ea7bdc65 JK |
705 | preempt_disable(); |
706 | ||
e1c467e6 FY |
707 | /* |
708 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
709 | */ | |
ea7bdc65 JK |
710 | if (cpu) { |
711 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
712 | goto out; | |
713 | } | |
e1c467e6 FY |
714 | |
715 | /* | |
716 | * Wake up BSP by nmi. | |
717 | * | |
718 | * Register a NMI handler to help wake up CPU0. | |
719 | */ | |
720 | boot_error = register_nmi_handler(NMI_LOCAL, | |
721 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
722 | ||
723 | if (!boot_error) { | |
724 | enable_start_cpu0 = 1; | |
725 | *cpu0_nmi_registered = 1; | |
726 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
727 | id = cpu0_logical_apicid; | |
728 | else | |
729 | id = apicid; | |
730 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
731 | } | |
ea7bdc65 JK |
732 | |
733 | out: | |
734 | preempt_enable(); | |
e1c467e6 FY |
735 | |
736 | return boot_error; | |
737 | } | |
738 | ||
cb3c8b90 GOC |
739 | /* |
740 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
741 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
742 | * Returns zero if CPU booted OK, else error code from |
743 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 744 | */ |
148f9bb8 | 745 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 746 | { |
48927bbb | 747 | volatile u32 *trampoline_status = |
b429dbf6 | 748 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 749 | /* start_ip had better be page-aligned! */ |
f37240f1 | 750 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 751 | |
cb3c8b90 | 752 | unsigned long boot_error = 0; |
ab6fb7c0 | 753 | int timeout; |
e1c467e6 | 754 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 755 | |
816afe4f RR |
756 | /* Just in case we booted with a single CPU. */ |
757 | alternatives_enable_smp(); | |
cb3c8b90 | 758 | |
7eb43a6d TG |
759 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
760 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
761 | per_cpu(current_task, cpu) = idle; | |
cb3c8b90 | 762 | |
c6f5e0ac | 763 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 764 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
765 | irq_ctx_init(cpu); |
766 | #else | |
7eb43a6d | 767 | clear_tsk_thread_flag(idle, TIF_FORK); |
004aa322 | 768 | initial_gs = per_cpu_offset(cpu); |
198d208d | 769 | #endif |
9af45651 | 770 | per_cpu(kernel_stack, cpu) = |
7eb43a6d | 771 | (unsigned long)task_stack_page(idle) - |
9af45651 | 772 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
a939098a | 773 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 774 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 775 | stack_start = idle->thread.sp; |
cb3c8b90 | 776 | |
2eaad1fd MT |
777 | /* So we see what's up */ |
778 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
779 | |
780 | /* | |
781 | * This grunge runs the startup process for | |
782 | * the targeted processor. | |
783 | */ | |
784 | ||
785 | atomic_set(&init_deasserted, 0); | |
786 | ||
34d05591 | 787 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 788 | |
cfc1b9a6 | 789 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 790 | |
34d05591 JS |
791 | smpboot_setup_warm_reset_vector(start_ip); |
792 | /* | |
793 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
794 | */ |
795 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
796 | apic_write(APIC_ESR, 0); | |
797 | apic_read(APIC_ESR); | |
798 | } | |
34d05591 | 799 | } |
cb3c8b90 | 800 | |
cb3c8b90 | 801 | /* |
e1c467e6 FY |
802 | * Wake up a CPU in difference cases: |
803 | * - Use the method in the APIC driver if it's defined | |
804 | * Otherwise, | |
805 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 806 | */ |
1f5bcabf IM |
807 | if (apic->wakeup_secondary_cpu) |
808 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
809 | else | |
e1c467e6 FY |
810 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
811 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
812 | |
813 | if (!boot_error) { | |
814 | /* | |
815 | * allow APs to start initializing. | |
816 | */ | |
c767a54b | 817 | pr_debug("Before Callout %d\n", cpu); |
c2d1cec1 | 818 | cpumask_set_cpu(cpu, cpu_callout_mask); |
c767a54b | 819 | pr_debug("After Callout %d\n", cpu); |
cb3c8b90 GOC |
820 | |
821 | /* | |
822 | * Wait 5s total for a response | |
823 | */ | |
824 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 825 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
826 | break; /* It has booted */ |
827 | udelay(100); | |
68f202e4 SS |
828 | /* |
829 | * Allow other tasks to run while we wait for the | |
830 | * AP to come online. This also gives a chance | |
831 | * for the MTRR work(triggered by the AP coming online) | |
832 | * to be completed in the stop machine context. | |
833 | */ | |
834 | schedule(); | |
cb3c8b90 GOC |
835 | } |
836 | ||
21c3fcf3 YL |
837 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
838 | print_cpu_msr(&cpu_data(cpu)); | |
2eaad1fd | 839 | pr_debug("CPU%d: has booted.\n", cpu); |
21c3fcf3 | 840 | } else { |
cb3c8b90 | 841 | boot_error = 1; |
48927bbb | 842 | if (*trampoline_status == 0xA5A5A5A5) |
cb3c8b90 | 843 | /* trampoline started but...? */ |
2eaad1fd | 844 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
845 | else |
846 | /* trampoline code not run */ | |
c767a54b | 847 | pr_err("CPU%d: Not responding\n", cpu); |
25dc0049 IM |
848 | if (apic->inquire_remote_apic) |
849 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
850 | } |
851 | } | |
1a51e3a0 | 852 | |
cb3c8b90 GOC |
853 | if (boot_error) { |
854 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 855 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
856 | |
857 | /* was set by do_boot_cpu() */ | |
858 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
859 | ||
860 | /* was set by cpu_init() */ | |
861 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
cb3c8b90 GOC |
862 | } |
863 | ||
864 | /* mark "stuck" area as not stuck */ | |
48927bbb | 865 | *trampoline_status = 0; |
cb3c8b90 | 866 | |
02421f98 YL |
867 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
868 | /* | |
869 | * Cleanup possible dangling ends... | |
870 | */ | |
871 | smpboot_restore_warm_reset_vector(); | |
872 | } | |
e1c467e6 FY |
873 | /* |
874 | * Clean up the nmi handler. Do this after the callin and callout sync | |
875 | * to avoid impact of possible long unregister time. | |
876 | */ | |
877 | if (cpu0_nmi_registered) | |
878 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
879 | ||
cb3c8b90 GOC |
880 | return boot_error; |
881 | } | |
882 | ||
148f9bb8 | 883 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 884 | { |
a21769a4 | 885 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
886 | unsigned long flags; |
887 | int err; | |
888 | ||
889 | WARN_ON(irqs_disabled()); | |
890 | ||
cfc1b9a6 | 891 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 892 | |
30106c17 | 893 | if (apicid == BAD_APICID || |
c284b42a | 894 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 895 | !apic->apic_id_valid(apicid)) { |
c767a54b | 896 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
897 | return -EINVAL; |
898 | } | |
899 | ||
900 | /* | |
901 | * Already booted CPU? | |
902 | */ | |
c2d1cec1 | 903 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 904 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
905 | return -ENOSYS; |
906 | } | |
907 | ||
908 | /* | |
909 | * Save current MTRR state in case it was changed since early boot | |
910 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
911 | */ | |
912 | mtrr_save_state(); | |
913 | ||
914 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
915 | ||
644c1541 VP |
916 | /* the FPU context is blank, nobody can own it */ |
917 | __cpu_disable_lazy_restore(cpu); | |
918 | ||
7eb43a6d | 919 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 920 | if (err) { |
cfc1b9a6 | 921 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 922 | return -EIO; |
cb3c8b90 GOC |
923 | } |
924 | ||
925 | /* | |
926 | * Check TSC synchronization with the AP (keep irqs disabled | |
927 | * while doing so): | |
928 | */ | |
929 | local_irq_save(flags); | |
930 | check_tsc_sync_source(cpu); | |
931 | local_irq_restore(flags); | |
932 | ||
7c04e64a | 933 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
934 | cpu_relax(); |
935 | touch_nmi_watchdog(); | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
7167d08e HK |
941 | /** |
942 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
943 | */ | |
944 | void arch_disable_smp_support(void) | |
945 | { | |
946 | disable_ioapic_support(); | |
947 | } | |
948 | ||
8aef135c GOC |
949 | /* |
950 | * Fall back to non SMP mode after errors. | |
951 | * | |
952 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
953 | */ | |
954 | static __init void disable_smp(void) | |
955 | { | |
4f062896 RR |
956 | init_cpu_present(cpumask_of(0)); |
957 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 958 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 959 | |
8aef135c | 960 | if (smp_found_config) |
b6df1b8b | 961 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 962 | else |
b6df1b8b | 963 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
964 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
965 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
966 | } |
967 | ||
968 | /* | |
969 | * Various sanity checks. | |
970 | */ | |
971 | static int __init smp_sanity_check(unsigned max_cpus) | |
972 | { | |
ac23d4ee | 973 | preempt_disable(); |
a58f03b0 | 974 | |
1ff2f20d | 975 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
976 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
977 | unsigned int cpu; | |
978 | unsigned nr; | |
979 | ||
c767a54b JP |
980 | pr_warn("More than 8 CPUs detected - skipping them\n" |
981 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
982 | |
983 | nr = 0; | |
984 | for_each_present_cpu(cpu) { | |
985 | if (nr >= 8) | |
c2d1cec1 | 986 | set_cpu_present(cpu, false); |
a58f03b0 YL |
987 | nr++; |
988 | } | |
989 | ||
990 | nr = 0; | |
991 | for_each_possible_cpu(cpu) { | |
992 | if (nr >= 8) | |
c2d1cec1 | 993 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
994 | nr++; |
995 | } | |
996 | ||
997 | nr_cpu_ids = 8; | |
998 | } | |
999 | #endif | |
1000 | ||
8aef135c | 1001 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1002 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1003 | hard_smp_processor_id()); |
1004 | ||
8aef135c GOC |
1005 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * If we couldn't find an SMP configuration at boot time, | |
1010 | * get out of here now! | |
1011 | */ | |
1012 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1013 | preempt_enable(); |
c767a54b | 1014 | pr_notice("SMP motherboard not detected\n"); |
8aef135c GOC |
1015 | disable_smp(); |
1016 | if (APIC_init_uniprocessor()) | |
c767a54b | 1017 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
8aef135c GOC |
1018 | return -1; |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * Should not be necessary because the MP table should list the boot | |
1023 | * CPU too, but we do it for the sake of robustness anyway. | |
1024 | */ | |
a27a6210 | 1025 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1026 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1027 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1028 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1029 | } | |
ac23d4ee | 1030 | preempt_enable(); |
8aef135c GOC |
1031 | |
1032 | /* | |
1033 | * If we couldn't find a local APIC, then get out of here now! | |
1034 | */ | |
1035 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1036 | !cpu_has_apic) { | |
103428e5 CG |
1037 | if (!disable_apic) { |
1038 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1039 | boot_cpu_physical_apicid); | |
c767a54b | 1040 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1041 | } |
8aef135c | 1042 | smpboot_clear_io_apic(); |
7167d08e | 1043 | disable_ioapic_support(); |
8aef135c GOC |
1044 | return -1; |
1045 | } | |
1046 | ||
1047 | verify_local_APIC(); | |
1048 | ||
1049 | /* | |
1050 | * If SMP should be disabled, then really disable it! | |
1051 | */ | |
1052 | if (!max_cpus) { | |
c767a54b | 1053 | pr_info("SMP mode deactivated\n"); |
8aef135c | 1054 | smpboot_clear_io_apic(); |
d54db1ac | 1055 | |
e90955c2 | 1056 | connect_bsp_APIC(); |
e90955c2 | 1057 | setup_local_APIC(); |
2fb270f3 | 1058 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1059 | return -1; |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static void __init smp_cpu_index_default(void) | |
1066 | { | |
1067 | int i; | |
1068 | struct cpuinfo_x86 *c; | |
1069 | ||
7c04e64a | 1070 | for_each_possible_cpu(i) { |
8aef135c GOC |
1071 | c = &cpu_data(i); |
1072 | /* mark all to hotplug */ | |
9628937d | 1073 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1074 | } |
1075 | } | |
1076 | ||
1077 | /* | |
1078 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1079 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1080 | */ | |
1081 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1082 | { | |
7ad728f9 RR |
1083 | unsigned int i; |
1084 | ||
deef3250 | 1085 | preempt_disable(); |
8aef135c | 1086 | smp_cpu_index_default(); |
792363d2 | 1087 | |
8aef135c GOC |
1088 | /* |
1089 | * Setup boot CPU information | |
1090 | */ | |
30106c17 | 1091 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1092 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1093 | mb(); | |
bd22a2f1 | 1094 | |
8aef135c | 1095 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1096 | for_each_possible_cpu(i) { |
79f55997 LZ |
1097 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1098 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1099 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1100 | } |
8aef135c GOC |
1101 | set_cpu_sibling_map(0); |
1102 | ||
6e1cb38a | 1103 | |
8aef135c | 1104 | if (smp_sanity_check(max_cpus) < 0) { |
c767a54b | 1105 | pr_info("SMP disabled\n"); |
8aef135c | 1106 | disable_smp(); |
deef3250 | 1107 | goto out; |
8aef135c GOC |
1108 | } |
1109 | ||
fa47f7e5 SS |
1110 | default_setup_apic_routing(); |
1111 | ||
ac23d4ee | 1112 | preempt_disable(); |
4c9961d5 | 1113 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1114 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1115 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1116 | /* Or can we switch back to PIC here? */ |
1117 | } | |
ac23d4ee | 1118 | preempt_enable(); |
8aef135c | 1119 | |
8aef135c | 1120 | connect_bsp_APIC(); |
b5841765 | 1121 | |
8aef135c GOC |
1122 | /* |
1123 | * Switch from PIC to APIC mode. | |
1124 | */ | |
1125 | setup_local_APIC(); | |
1126 | ||
e1c467e6 FY |
1127 | if (x2apic_mode) |
1128 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1129 | else | |
1130 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1131 | ||
8aef135c GOC |
1132 | /* |
1133 | * Enable IO APIC before setting up error vector | |
1134 | */ | |
1135 | if (!skip_ioapic_setup && nr_ioapics) | |
1136 | enable_IO_APIC(); | |
88d0f550 | 1137 | |
2fb270f3 | 1138 | bsp_end_local_APIC_setup(); |
8aef135c | 1139 | |
d83093b5 IM |
1140 | if (apic->setup_portio_remap) |
1141 | apic->setup_portio_remap(); | |
8aef135c GOC |
1142 | |
1143 | smpboot_setup_io_apic(); | |
1144 | /* | |
1145 | * Set up local APIC timer on boot CPU. | |
1146 | */ | |
1147 | ||
c767a54b | 1148 | pr_info("CPU%d: ", 0); |
8aef135c | 1149 | print_cpu_info(&cpu_data(0)); |
736decac | 1150 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1151 | |
1152 | if (is_uv_system()) | |
1153 | uv_system_init(); | |
d0af9eed SS |
1154 | |
1155 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1156 | out: |
1157 | preempt_enable(); | |
8aef135c | 1158 | } |
d0af9eed SS |
1159 | |
1160 | void arch_enable_nonboot_cpus_begin(void) | |
1161 | { | |
1162 | set_mtrr_aps_delayed_init(); | |
1163 | } | |
1164 | ||
1165 | void arch_enable_nonboot_cpus_end(void) | |
1166 | { | |
1167 | mtrr_aps_init(); | |
1168 | } | |
1169 | ||
a8db8453 GOC |
1170 | /* |
1171 | * Early setup to make printk work. | |
1172 | */ | |
1173 | void __init native_smp_prepare_boot_cpu(void) | |
1174 | { | |
1175 | int me = smp_processor_id(); | |
552be871 | 1176 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1177 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1178 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1179 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1180 | } | |
1181 | ||
83f7eb9c GOC |
1182 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1183 | { | |
c767a54b | 1184 | pr_debug("Boot done\n"); |
83f7eb9c | 1185 | |
99e8b9ca | 1186 | nmi_selftest(); |
83f7eb9c | 1187 | impress_friends(); |
83f7eb9c GOC |
1188 | #ifdef CONFIG_X86_IO_APIC |
1189 | setup_ioapic_dest(); | |
1190 | #endif | |
d0af9eed | 1191 | mtrr_aps_init(); |
83f7eb9c GOC |
1192 | } |
1193 | ||
3b11ce7f MT |
1194 | static int __initdata setup_possible_cpus = -1; |
1195 | static int __init _setup_possible_cpus(char *str) | |
1196 | { | |
1197 | get_option(&str, &setup_possible_cpus); | |
1198 | return 0; | |
1199 | } | |
1200 | early_param("possible_cpus", _setup_possible_cpus); | |
1201 | ||
1202 | ||
68a1c3f8 | 1203 | /* |
4f062896 | 1204 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1205 | * are onlined, or offlined. The reason is per-cpu data-structures |
1206 | * are allocated by some modules at init time, and dont expect to | |
1207 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1208 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1209 | * In case when cpu_hotplug is not compiled, then we resort to current |
1210 | * behaviour, which is cpu_possible == cpu_present. | |
1211 | * - Ashok Raj | |
1212 | * | |
1213 | * Three ways to find out the number of additional hotplug CPUs: | |
1214 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1215 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1216 | * - Otherwise don't reserve additional CPUs. |
1217 | * We do this because additional CPUs waste a lot of memory. | |
1218 | * -AK | |
1219 | */ | |
1220 | __init void prefill_possible_map(void) | |
1221 | { | |
cb48bb59 | 1222 | int i, possible; |
68a1c3f8 | 1223 | |
329513a3 YL |
1224 | /* no processor from mptable or madt */ |
1225 | if (!num_processors) | |
1226 | num_processors = 1; | |
1227 | ||
5f2eb550 JB |
1228 | i = setup_max_cpus ?: 1; |
1229 | if (setup_possible_cpus == -1) { | |
1230 | possible = num_processors; | |
1231 | #ifdef CONFIG_HOTPLUG_CPU | |
1232 | if (setup_max_cpus) | |
1233 | possible += disabled_cpus; | |
1234 | #else | |
1235 | if (possible > i) | |
1236 | possible = i; | |
1237 | #endif | |
1238 | } else | |
3b11ce7f MT |
1239 | possible = setup_possible_cpus; |
1240 | ||
730cf272 MT |
1241 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1242 | ||
2b633e3f YL |
1243 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1244 | if (possible > nr_cpu_ids) { | |
c767a54b | 1245 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1246 | possible, nr_cpu_ids); |
1247 | possible = nr_cpu_ids; | |
3b11ce7f | 1248 | } |
68a1c3f8 | 1249 | |
5f2eb550 JB |
1250 | #ifdef CONFIG_HOTPLUG_CPU |
1251 | if (!setup_max_cpus) | |
1252 | #endif | |
1253 | if (possible > i) { | |
c767a54b | 1254 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1255 | possible, setup_max_cpus); |
1256 | possible = i; | |
1257 | } | |
1258 | ||
c767a54b | 1259 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1260 | possible, max_t(int, possible - num_processors, 0)); |
1261 | ||
1262 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1263 | set_cpu_possible(i, true); |
5f2eb550 JB |
1264 | for (; i < NR_CPUS; i++) |
1265 | set_cpu_possible(i, false); | |
3461b0af MT |
1266 | |
1267 | nr_cpu_ids = possible; | |
68a1c3f8 | 1268 | } |
69c18c15 | 1269 | |
14adf855 CE |
1270 | #ifdef CONFIG_HOTPLUG_CPU |
1271 | ||
1272 | static void remove_siblinginfo(int cpu) | |
1273 | { | |
1274 | int sibling; | |
1275 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1276 | ||
c2d1cec1 MT |
1277 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1278 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1279 | /*/ |
1280 | * last thread sibling in this cpu core going down | |
1281 | */ | |
c2d1cec1 | 1282 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1283 | cpu_data(sibling).booted_cores--; |
1284 | } | |
1285 | ||
c2d1cec1 MT |
1286 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1287 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1288 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1289 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1290 | c->phys_proc_id = 0; |
1291 | c->cpu_core_id = 0; | |
c2d1cec1 | 1292 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1293 | } |
1294 | ||
69c18c15 GC |
1295 | static void __ref remove_cpu_from_maps(int cpu) |
1296 | { | |
c2d1cec1 MT |
1297 | set_cpu_online(cpu, false); |
1298 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1299 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1300 | /* was set by cpu_init() */ |
c2d1cec1 | 1301 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1302 | numa_remove_cpu(cpu); |
69c18c15 GC |
1303 | } |
1304 | ||
8227dce7 | 1305 | void cpu_disable_common(void) |
69c18c15 GC |
1306 | { |
1307 | int cpu = smp_processor_id(); | |
69c18c15 | 1308 | |
69c18c15 GC |
1309 | remove_siblinginfo(cpu); |
1310 | ||
1311 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1312 | lock_vector_lock(); |
69c18c15 | 1313 | remove_cpu_from_maps(cpu); |
d388e5fd | 1314 | unlock_vector_lock(); |
d7b381bb | 1315 | fixup_irqs(); |
8227dce7 AN |
1316 | } |
1317 | ||
1318 | int native_cpu_disable(void) | |
1319 | { | |
da6139e4 PB |
1320 | int ret; |
1321 | ||
1322 | ret = check_irq_vectors_for_cpu_disable(); | |
1323 | if (ret) | |
1324 | return ret; | |
1325 | ||
8227dce7 AN |
1326 | clear_local_APIC(); |
1327 | ||
1328 | cpu_disable_common(); | |
69c18c15 GC |
1329 | return 0; |
1330 | } | |
1331 | ||
93be71b6 | 1332 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1333 | { |
1334 | /* We don't do anything here: idle task is faking death itself. */ | |
1335 | unsigned int i; | |
1336 | ||
1337 | for (i = 0; i < 10; i++) { | |
1338 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1339 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1340 | if (system_state == SYSTEM_RUNNING) |
1341 | pr_info("CPU %u is now offline\n", cpu); | |
69c18c15 GC |
1342 | return; |
1343 | } | |
1344 | msleep(100); | |
1345 | } | |
2eaad1fd | 1346 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1347 | } |
a21f5d88 AN |
1348 | |
1349 | void play_dead_common(void) | |
1350 | { | |
1351 | idle_task_exit(); | |
1352 | reset_lazy_tlbstate(); | |
02c68a02 | 1353 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1354 | |
1355 | mb(); | |
1356 | /* Ack it */ | |
0a3aee0d | 1357 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1358 | |
1359 | /* | |
1360 | * With physical CPU hotplug, we should halt the cpu | |
1361 | */ | |
1362 | local_irq_disable(); | |
1363 | } | |
1364 | ||
e1c467e6 FY |
1365 | static bool wakeup_cpu0(void) |
1366 | { | |
1367 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1368 | return true; | |
1369 | ||
1370 | return false; | |
1371 | } | |
1372 | ||
ea530692 PA |
1373 | /* |
1374 | * We need to flush the caches before going to sleep, lest we have | |
1375 | * dirty data in our caches when we come back up. | |
1376 | */ | |
1377 | static inline void mwait_play_dead(void) | |
1378 | { | |
1379 | unsigned int eax, ebx, ecx, edx; | |
1380 | unsigned int highest_cstate = 0; | |
1381 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1382 | void *mwait_ptr; |
576cfb40 | 1383 | int i; |
ea530692 | 1384 | |
69fb3676 | 1385 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1386 | return; |
840d2830 | 1387 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1388 | return; |
7b543a53 | 1389 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1390 | return; |
1391 | ||
1392 | eax = CPUID_MWAIT_LEAF; | |
1393 | ecx = 0; | |
1394 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1395 | ||
1396 | /* | |
1397 | * eax will be 0 if EDX enumeration is not valid. | |
1398 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1399 | */ | |
1400 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1401 | eax = 0; | |
1402 | } else { | |
1403 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1404 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1405 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1406 | highest_cstate = i; | |
1407 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1408 | } | |
1409 | } | |
1410 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1411 | (highest_subcstate - 1); | |
1412 | } | |
1413 | ||
ce5f6824 PA |
1414 | /* |
1415 | * This should be a memory location in a cache line which is | |
1416 | * unlikely to be touched by other processors. The actual | |
1417 | * content is immaterial as it is not actually modified in any way. | |
1418 | */ | |
1419 | mwait_ptr = ¤t_thread_info()->flags; | |
1420 | ||
a68e5c94 PA |
1421 | wbinvd(); |
1422 | ||
ea530692 | 1423 | while (1) { |
ce5f6824 PA |
1424 | /* |
1425 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1426 | * the Xeon 7400 series. It's not clear it is actually | |
1427 | * needed, but it should be harmless in either case. | |
1428 | * The WBINVD is insufficient due to the spurious-wakeup | |
1429 | * case where we return around the loop. | |
1430 | */ | |
7d590cca | 1431 | mb(); |
ce5f6824 | 1432 | clflush(mwait_ptr); |
7d590cca | 1433 | mb(); |
ce5f6824 | 1434 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1435 | mb(); |
1436 | __mwait(eax, 0); | |
e1c467e6 FY |
1437 | /* |
1438 | * If NMI wants to wake up CPU0, start CPU0. | |
1439 | */ | |
1440 | if (wakeup_cpu0()) | |
1441 | start_cpu0(); | |
ea530692 PA |
1442 | } |
1443 | } | |
1444 | ||
1445 | static inline void hlt_play_dead(void) | |
1446 | { | |
7b543a53 | 1447 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1448 | wbinvd(); |
1449 | ||
ea530692 | 1450 | while (1) { |
ea530692 | 1451 | native_halt(); |
e1c467e6 FY |
1452 | /* |
1453 | * If NMI wants to wake up CPU0, start CPU0. | |
1454 | */ | |
1455 | if (wakeup_cpu0()) | |
1456 | start_cpu0(); | |
ea530692 PA |
1457 | } |
1458 | } | |
1459 | ||
a21f5d88 AN |
1460 | void native_play_dead(void) |
1461 | { | |
1462 | play_dead_common(); | |
86886e55 | 1463 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1464 | |
1465 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1466 | if (cpuidle_play_dead()) |
1467 | hlt_play_dead(); | |
a21f5d88 AN |
1468 | } |
1469 | ||
69c18c15 | 1470 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1471 | int native_cpu_disable(void) |
69c18c15 GC |
1472 | { |
1473 | return -ENOSYS; | |
1474 | } | |
1475 | ||
93be71b6 | 1476 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1477 | { |
1478 | /* We said "no" in __cpu_disable */ | |
1479 | BUG(); | |
1480 | } | |
a21f5d88 AN |
1481 | |
1482 | void native_play_dead(void) | |
1483 | { | |
1484 | BUG(); | |
1485 | } | |
1486 | ||
68a1c3f8 | 1487 | #endif |