Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
69c18c15 | 51 | |
8aef135c | 52 | #include <asm/acpi.h> |
cb3c8b90 | 53 | #include <asm/desc.h> |
69c18c15 GC |
54 | #include <asm/nmi.h> |
55 | #include <asm/irq.h> | |
07bbc16a | 56 | #include <asm/idle.h> |
e44b7b75 | 57 | #include <asm/trampoline.h> |
69c18c15 GC |
58 | #include <asm/cpu.h> |
59 | #include <asm/numa.h> | |
cb3c8b90 GOC |
60 | #include <asm/pgtable.h> |
61 | #include <asm/tlbflush.h> | |
62 | #include <asm/mtrr.h> | |
bbc2ff6a | 63 | #include <asm/vmi.h> |
7b6aa335 | 64 | #include <asm/apic.h> |
569712b2 | 65 | #include <asm/setup.h> |
bdbcdd48 | 66 | #include <asm/uv/uv.h> |
cb3c8b90 | 67 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 68 | |
1164dd00 | 69 | #include <asm/smpboot_hooks.h> |
cb3c8b90 | 70 | |
16ecf7a4 | 71 | #ifdef CONFIG_X86_32 |
4cedb334 | 72 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 73 | static int low_mappings; |
acbb6734 GOC |
74 | #endif |
75 | ||
a8db8453 GOC |
76 | /* State of each CPU */ |
77 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
78 | ||
cb3c8b90 GOC |
79 | /* Store all idle threads, this can be reused instead of creating |
80 | * a new thread. Also avoids complicated thread destroy functionality | |
81 | * for idle threads. | |
82 | */ | |
83 | #ifdef CONFIG_HOTPLUG_CPU | |
84 | /* | |
85 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
86 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
87 | */ | |
88 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
89 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
90 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
91 | #else | |
f86c9985 | 92 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
93 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
94 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
95 | #endif | |
f6bc4029 | 96 | |
a355352b GC |
97 | /* Number of siblings per CPU package */ |
98 | int smp_num_siblings = 1; | |
99 | EXPORT_SYMBOL(smp_num_siblings); | |
100 | ||
101 | /* Last level cache ID of each logical CPU */ | |
102 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
103 | ||
a355352b | 104 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 105 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
106 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
107 | ||
108 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 109 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
110 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
111 | ||
112 | /* Per CPU bogomips and other parameters */ | |
113 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
114 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 115 | |
2b6163bf | 116 | atomic_t init_deasserted; |
cb3c8b90 | 117 | |
7cc3959e | 118 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
119 | /* which node each logical CPU is on */ |
120 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
121 | EXPORT_SYMBOL(cpu_to_node_map); | |
122 | ||
123 | /* set up a mapping between cpu and node. */ | |
124 | static void map_cpu_to_node(int cpu, int node) | |
125 | { | |
126 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 127 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
128 | cpu_to_node_map[cpu] = node; |
129 | } | |
130 | ||
131 | /* undo a mapping between cpu and node. */ | |
132 | static void unmap_cpu_to_node(int cpu) | |
133 | { | |
134 | int node; | |
135 | ||
136 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
137 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 138 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
139 | cpu_to_node_map[cpu] = 0; |
140 | } | |
141 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
142 | #define map_cpu_to_node(cpu, node) ({}) | |
143 | #define unmap_cpu_to_node(cpu) ({}) | |
144 | #endif | |
145 | ||
146 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
147 | static int boot_cpu_logical_apicid; |
148 | ||
7cc3959e GOC |
149 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
150 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
151 | ||
a4928cff | 152 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
153 | { |
154 | int cpu = smp_processor_id(); | |
155 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 156 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
157 | |
158 | if (!node_online(node)) | |
159 | node = first_online_node; | |
160 | ||
161 | cpu_2_logical_apicid[cpu] = apicid; | |
162 | map_cpu_to_node(cpu, node); | |
163 | } | |
164 | ||
1481a3dd | 165 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
166 | { |
167 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
168 | unmap_cpu_to_node(cpu); | |
169 | } | |
170 | #else | |
7cc3959e GOC |
171 | #define map_cpu_to_logical_apicid() do {} while (0) |
172 | #endif | |
173 | ||
cb3c8b90 GOC |
174 | /* |
175 | * Report back to the Boot Processor. | |
176 | * Running on AP. | |
177 | */ | |
a4928cff | 178 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
179 | { |
180 | int cpuid, phys_id; | |
181 | unsigned long timeout; | |
182 | ||
183 | /* | |
184 | * If waken up by an INIT in an 82489DX configuration | |
185 | * we may get here before an INIT-deassert IPI reaches | |
186 | * our local APIC. We have to wait for the IPI or we'll | |
187 | * lock up on an APIC access. | |
188 | */ | |
a9659366 IM |
189 | if (apic->wait_for_init_deassert) |
190 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
191 | |
192 | /* | |
193 | * (This works even if the APIC is not enabled.) | |
194 | */ | |
4c9961d5 | 195 | phys_id = read_apic_id(); |
cb3c8b90 | 196 | cpuid = smp_processor_id(); |
c2d1cec1 | 197 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
198 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
199 | phys_id, cpuid); | |
200 | } | |
cfc1b9a6 | 201 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
202 | |
203 | /* | |
204 | * STARTUP IPIs are fragile beasts as they might sometimes | |
205 | * trigger some glue motherboard logic. Complete APIC bus | |
206 | * silence for 1 second, this overestimates the time the | |
207 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
208 | * by a factor of two. This should be enough. | |
209 | */ | |
210 | ||
211 | /* | |
212 | * Waiting 2s total for startup (udelay is not yet working) | |
213 | */ | |
214 | timeout = jiffies + 2*HZ; | |
215 | while (time_before(jiffies, timeout)) { | |
216 | /* | |
217 | * Has the boot CPU finished it's STARTUP sequence? | |
218 | */ | |
c2d1cec1 | 219 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
220 | break; |
221 | cpu_relax(); | |
222 | } | |
223 | ||
224 | if (!time_before(jiffies, timeout)) { | |
225 | panic("%s: CPU%d started up but did not get a callout!\n", | |
226 | __func__, cpuid); | |
227 | } | |
228 | ||
229 | /* | |
230 | * the boot CPU has finished the init stage and is spinning | |
231 | * on callin_map until we finish. We are free to set up this | |
232 | * CPU, first the APIC. (this is probably redundant on most | |
233 | * boards) | |
234 | */ | |
235 | ||
cfc1b9a6 | 236 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
237 | if (apic->smp_callin_clear_local_apic) |
238 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
239 | setup_local_APIC(); |
240 | end_local_APIC_setup(); | |
241 | map_cpu_to_logical_apicid(); | |
242 | ||
e545a614 | 243 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
244 | /* |
245 | * Get our bogomips. | |
246 | * | |
247 | * Need to enable IRQs because it can take longer and then | |
248 | * the NMI watchdog might kill us. | |
249 | */ | |
250 | local_irq_enable(); | |
251 | calibrate_delay(); | |
252 | local_irq_disable(); | |
cfc1b9a6 | 253 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
254 | |
255 | /* | |
256 | * Save our processor parameters | |
257 | */ | |
258 | smp_store_cpu_info(cpuid); | |
259 | ||
260 | /* | |
261 | * Allow the master to continue. | |
262 | */ | |
c2d1cec1 | 263 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
264 | } |
265 | ||
bbc2ff6a GOC |
266 | /* |
267 | * Activate a secondary processor. | |
268 | */ | |
0ca59dd9 | 269 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
270 | { |
271 | /* | |
272 | * Don't put *anything* before cpu_init(), SMP booting is too | |
273 | * fragile that we want to limit the things done here to the | |
274 | * most necessary things. | |
275 | */ | |
bbc2ff6a | 276 | vmi_bringup(); |
bbc2ff6a GOC |
277 | cpu_init(); |
278 | preempt_disable(); | |
279 | smp_callin(); | |
280 | ||
281 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
282 | barrier(); | |
283 | /* | |
284 | * Check TSC synchronization with the BP: | |
285 | */ | |
286 | check_tsc_sync_target(); | |
287 | ||
288 | if (nmi_watchdog == NMI_IO_APIC) { | |
289 | disable_8259A_irq(0); | |
290 | enable_NMI_through_LVT0(); | |
291 | enable_8259A_irq(0); | |
292 | } | |
293 | ||
61165d7a HD |
294 | #ifdef CONFIG_X86_32 |
295 | while (low_mappings) | |
296 | cpu_relax(); | |
297 | __flush_tlb_all(); | |
298 | #endif | |
299 | ||
4f062896 | 300 | /* This must be done before setting cpu_online_mask */ |
bbc2ff6a GOC |
301 | set_cpu_sibling_map(raw_smp_processor_id()); |
302 | wmb(); | |
303 | ||
304 | /* | |
305 | * We need to hold call_lock, so there is no inconsistency | |
306 | * between the time smp_call_function() determines number of | |
307 | * IPI recipients, and the time when the determination is made | |
308 | * for which cpus receive the IPI. Holding this | |
309 | * lock helps us to not include this cpu in a currently in progress | |
310 | * smp_call_function(). | |
d388e5fd EB |
311 | * |
312 | * We need to hold vector_lock so there the set of online cpus | |
313 | * does not change while we are assigning vectors to cpus. Holding | |
314 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 315 | */ |
0cefa5b9 | 316 | ipi_call_lock(); |
d388e5fd EB |
317 | lock_vector_lock(); |
318 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 319 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 320 | unlock_vector_lock(); |
0cefa5b9 | 321 | ipi_call_unlock(); |
bbc2ff6a GOC |
322 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
323 | ||
0cefa5b9 MS |
324 | /* enable local interrupts */ |
325 | local_irq_enable(); | |
326 | ||
736decac | 327 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
328 | |
329 | wmb(); | |
330 | cpu_idle(); | |
331 | } | |
332 | ||
155dd720 RR |
333 | #ifdef CONFIG_CPUMASK_OFFSTACK |
334 | /* In this case, llc_shared_map is a pointer to a cpumask. */ | |
335 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
336 | const struct cpuinfo_x86 *src) | |
337 | { | |
338 | struct cpumask *llc = dst->llc_shared_map; | |
339 | *dst = *src; | |
340 | dst->llc_shared_map = llc; | |
341 | } | |
342 | #else | |
343 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
344 | const struct cpuinfo_x86 *src) | |
345 | { | |
346 | *dst = *src; | |
347 | } | |
348 | #endif /* CONFIG_CPUMASK_OFFSTACK */ | |
349 | ||
1d89a7f0 GOC |
350 | /* |
351 | * The bootstrap kernel entry code has set these up. Save them for | |
352 | * a given CPU | |
353 | */ | |
354 | ||
355 | void __cpuinit smp_store_cpu_info(int id) | |
356 | { | |
357 | struct cpuinfo_x86 *c = &cpu_data(id); | |
358 | ||
155dd720 | 359 | copy_cpuinfo_x86(c, &boot_cpu_data); |
1d89a7f0 GOC |
360 | c->cpu_index = id; |
361 | if (id != 0) | |
362 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
363 | } |
364 | ||
365 | ||
768d9505 GC |
366 | void __cpuinit set_cpu_sibling_map(int cpu) |
367 | { | |
368 | int i; | |
369 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
370 | ||
c2d1cec1 | 371 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
372 | |
373 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
374 | for_each_cpu(i, cpu_sibling_setup_mask) { |
375 | struct cpuinfo_x86 *o = &cpu_data(i); | |
376 | ||
377 | if (c->phys_proc_id == o->phys_proc_id && | |
378 | c->cpu_core_id == o->cpu_core_id) { | |
379 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
380 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
381 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
382 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
155dd720 RR |
383 | cpumask_set_cpu(i, c->llc_shared_map); |
384 | cpumask_set_cpu(cpu, o->llc_shared_map); | |
768d9505 GC |
385 | } |
386 | } | |
387 | } else { | |
c2d1cec1 | 388 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
389 | } |
390 | ||
155dd720 | 391 | cpumask_set_cpu(cpu, c->llc_shared_map); |
768d9505 GC |
392 | |
393 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 394 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
395 | c->booted_cores = 1; |
396 | return; | |
397 | } | |
398 | ||
c2d1cec1 | 399 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
400 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
401 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
155dd720 RR |
402 | cpumask_set_cpu(i, c->llc_shared_map); |
403 | cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); | |
768d9505 GC |
404 | } |
405 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
406 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
407 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
408 | /* |
409 | * Does this new cpu bringup a new core? | |
410 | */ | |
c2d1cec1 | 411 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
412 | /* |
413 | * for each core in package, increment | |
414 | * the booted_cores for this new cpu | |
415 | */ | |
c2d1cec1 | 416 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
417 | c->booted_cores++; |
418 | /* | |
419 | * increment the core count for all | |
420 | * the other cpus in this package | |
421 | */ | |
422 | if (i != cpu) | |
423 | cpu_data(i).booted_cores++; | |
424 | } else if (i != cpu && !c->booted_cores) | |
425 | c->booted_cores = cpu_data(i).booted_cores; | |
426 | } | |
427 | } | |
428 | } | |
429 | ||
70708a18 | 430 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 431 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
432 | { |
433 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
434 | /* | |
435 | * For perf, we return last level cache shared map. | |
436 | * And for power savings, we return cpu_core_map | |
437 | */ | |
5a925b42 AH |
438 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
439 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 440 | return cpu_core_mask(cpu); |
70708a18 | 441 | else |
155dd720 | 442 | return c->llc_shared_map; |
030bb203 RR |
443 | } |
444 | ||
a4928cff | 445 | static void impress_friends(void) |
904541e2 GOC |
446 | { |
447 | int cpu; | |
448 | unsigned long bogosum = 0; | |
449 | /* | |
450 | * Allow the user to impress friends. | |
451 | */ | |
cfc1b9a6 | 452 | pr_debug("Before bogomips.\n"); |
904541e2 | 453 | for_each_possible_cpu(cpu) |
c2d1cec1 | 454 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
455 | bogosum += cpu_data(cpu).loops_per_jiffy; |
456 | printk(KERN_INFO | |
457 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 458 | num_online_cpus(), |
904541e2 GOC |
459 | bogosum/(500000/HZ), |
460 | (bogosum/(5000/HZ))%100); | |
461 | ||
cfc1b9a6 | 462 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
463 | } |
464 | ||
569712b2 | 465 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
466 | { |
467 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
468 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
469 | int timeout; | |
470 | u32 status; | |
471 | ||
823b259b | 472 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
473 | |
474 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 475 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
476 | |
477 | /* | |
478 | * Wait for idle. | |
479 | */ | |
480 | status = safe_apic_wait_icr_idle(); | |
481 | if (status) | |
482 | printk(KERN_CONT | |
483 | "a previous APIC delivery may have failed\n"); | |
484 | ||
1b374e4d | 485 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
486 | |
487 | timeout = 0; | |
488 | do { | |
489 | udelay(100); | |
490 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
491 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
492 | ||
493 | switch (status) { | |
494 | case APIC_ICR_RR_VALID: | |
495 | status = apic_read(APIC_RRR); | |
496 | printk(KERN_CONT "%08x\n", status); | |
497 | break; | |
498 | default: | |
499 | printk(KERN_CONT "failed\n"); | |
500 | } | |
501 | } | |
502 | } | |
503 | ||
cb3c8b90 GOC |
504 | /* |
505 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
506 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
507 | * won't ... remember to clear down the APIC, etc later. | |
508 | */ | |
cece3155 | 509 | int __cpuinit |
569712b2 | 510 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
511 | { |
512 | unsigned long send_status, accept_status = 0; | |
513 | int maxlvt; | |
514 | ||
515 | /* Target chip */ | |
cb3c8b90 GOC |
516 | /* Boot on the stack */ |
517 | /* Kick the second */ | |
bdb1a9b6 | 518 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 519 | |
cfc1b9a6 | 520 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
521 | send_status = safe_apic_wait_icr_idle(); |
522 | ||
523 | /* | |
524 | * Give the other CPU some time to accept the IPI. | |
525 | */ | |
526 | udelay(200); | |
569712b2 | 527 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
528 | maxlvt = lapic_get_maxlvt(); |
529 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
530 | apic_write(APIC_ESR, 0); | |
531 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
532 | } | |
cfc1b9a6 | 533 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
534 | |
535 | if (send_status) | |
536 | printk(KERN_ERR "APIC never delivered???\n"); | |
537 | if (accept_status) | |
538 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
539 | ||
540 | return (send_status | accept_status); | |
541 | } | |
cb3c8b90 | 542 | |
cece3155 | 543 | static int __cpuinit |
569712b2 | 544 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
545 | { |
546 | unsigned long send_status, accept_status = 0; | |
547 | int maxlvt, num_starts, j; | |
548 | ||
593f4a78 MR |
549 | maxlvt = lapic_get_maxlvt(); |
550 | ||
cb3c8b90 GOC |
551 | /* |
552 | * Be paranoid about clearing APIC errors. | |
553 | */ | |
554 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
555 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
556 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
557 | apic_read(APIC_ESR); |
558 | } | |
559 | ||
cfc1b9a6 | 560 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
561 | |
562 | /* | |
563 | * Turn INIT on target chip | |
564 | */ | |
cb3c8b90 GOC |
565 | /* |
566 | * Send IPI | |
567 | */ | |
1b374e4d SS |
568 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
569 | phys_apicid); | |
cb3c8b90 | 570 | |
cfc1b9a6 | 571 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
572 | send_status = safe_apic_wait_icr_idle(); |
573 | ||
574 | mdelay(10); | |
575 | ||
cfc1b9a6 | 576 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
577 | |
578 | /* Target chip */ | |
cb3c8b90 | 579 | /* Send IPI */ |
1b374e4d | 580 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 581 | |
cfc1b9a6 | 582 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
583 | send_status = safe_apic_wait_icr_idle(); |
584 | ||
585 | mb(); | |
586 | atomic_set(&init_deasserted, 1); | |
587 | ||
588 | /* | |
589 | * Should we send STARTUP IPIs ? | |
590 | * | |
591 | * Determine this based on the APIC version. | |
592 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
593 | */ | |
594 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
595 | num_starts = 2; | |
596 | else | |
597 | num_starts = 0; | |
598 | ||
599 | /* | |
600 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
601 | * target processor state. | |
602 | */ | |
603 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 604 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
605 | |
606 | /* | |
607 | * Run STARTUP IPI loop. | |
608 | */ | |
cfc1b9a6 | 609 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 610 | |
cb3c8b90 | 611 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 612 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
613 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
614 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 615 | apic_read(APIC_ESR); |
cfc1b9a6 | 616 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
617 | |
618 | /* | |
619 | * STARTUP IPI | |
620 | */ | |
621 | ||
622 | /* Target chip */ | |
cb3c8b90 GOC |
623 | /* Boot on the stack */ |
624 | /* Kick the second */ | |
1b374e4d SS |
625 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
626 | phys_apicid); | |
cb3c8b90 GOC |
627 | |
628 | /* | |
629 | * Give the other CPU some time to accept the IPI. | |
630 | */ | |
631 | udelay(300); | |
632 | ||
cfc1b9a6 | 633 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 634 | |
cfc1b9a6 | 635 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
636 | send_status = safe_apic_wait_icr_idle(); |
637 | ||
638 | /* | |
639 | * Give the other CPU some time to accept the IPI. | |
640 | */ | |
641 | udelay(200); | |
593f4a78 | 642 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 643 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
644 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
645 | if (send_status || accept_status) | |
646 | break; | |
647 | } | |
cfc1b9a6 | 648 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
649 | |
650 | if (send_status) | |
651 | printk(KERN_ERR "APIC never delivered???\n"); | |
652 | if (accept_status) | |
653 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
654 | ||
655 | return (send_status | accept_status); | |
656 | } | |
cb3c8b90 GOC |
657 | |
658 | struct create_idle { | |
659 | struct work_struct work; | |
660 | struct task_struct *idle; | |
661 | struct completion done; | |
662 | int cpu; | |
663 | }; | |
664 | ||
665 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
666 | { | |
667 | struct create_idle *c_idle = | |
668 | container_of(work, struct create_idle, work); | |
669 | ||
670 | c_idle->idle = fork_idle(c_idle->cpu); | |
671 | complete(&c_idle->done); | |
672 | } | |
673 | ||
cb3c8b90 GOC |
674 | /* |
675 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
676 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
677 | * Returns zero if CPU booted OK, else error code from |
678 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 679 | */ |
ab6fb7c0 | 680 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
681 | { |
682 | unsigned long boot_error = 0; | |
cb3c8b90 | 683 | unsigned long start_ip; |
ab6fb7c0 | 684 | int timeout; |
cb3c8b90 | 685 | struct create_idle c_idle = { |
ab6fb7c0 IM |
686 | .cpu = cpu, |
687 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 688 | }; |
ab6fb7c0 | 689 | |
cb3c8b90 | 690 | INIT_WORK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 691 | |
cb3c8b90 GOC |
692 | alternatives_smp_switch(1); |
693 | ||
694 | c_idle.idle = get_idle_for_cpu(cpu); | |
695 | ||
696 | /* | |
697 | * We can't use kernel_thread since we must avoid to | |
698 | * reschedule the child. | |
699 | */ | |
700 | if (c_idle.idle) { | |
701 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
702 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
703 | init_idle(c_idle.idle, cpu); | |
704 | goto do_rest; | |
705 | } | |
706 | ||
707 | if (!keventd_up() || current_is_keventd()) | |
708 | c_idle.work.func(&c_idle.work); | |
709 | else { | |
710 | schedule_work(&c_idle.work); | |
711 | wait_for_completion(&c_idle.done); | |
712 | } | |
713 | ||
714 | if (IS_ERR(c_idle.idle)) { | |
715 | printk("failed fork for CPU %d\n", cpu); | |
716 | return PTR_ERR(c_idle.idle); | |
717 | } | |
718 | ||
719 | set_idle_for_cpu(cpu, c_idle.idle); | |
720 | do_rest: | |
cb3c8b90 | 721 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 722 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 723 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
724 | irq_ctx_init(cpu); |
725 | #else | |
cb3c8b90 | 726 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 727 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
728 | per_cpu(kernel_stack, cpu) = |
729 | (unsigned long)task_stack_page(c_idle.idle) - | |
730 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 731 | #endif |
a939098a | 732 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 733 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 734 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
735 | |
736 | /* start_ip had better be page-aligned! */ | |
737 | start_ip = setup_trampoline(); | |
738 | ||
739 | /* So we see what's up */ | |
823b259b | 740 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
741 | cpu, apicid, start_ip); |
742 | ||
743 | /* | |
744 | * This grunge runs the startup process for | |
745 | * the targeted processor. | |
746 | */ | |
747 | ||
748 | atomic_set(&init_deasserted, 0); | |
749 | ||
34d05591 | 750 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 751 | |
cfc1b9a6 | 752 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 753 | |
34d05591 JS |
754 | smpboot_setup_warm_reset_vector(start_ip); |
755 | /* | |
756 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
757 | */ |
758 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
759 | apic_write(APIC_ESR, 0); | |
760 | apic_read(APIC_ESR); | |
761 | } | |
34d05591 | 762 | } |
cb3c8b90 | 763 | |
cb3c8b90 | 764 | /* |
1f5bcabf IM |
765 | * Kick the secondary CPU. Use the method in the APIC driver |
766 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 767 | */ |
1f5bcabf IM |
768 | if (apic->wakeup_secondary_cpu) |
769 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
770 | else | |
771 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
772 | |
773 | if (!boot_error) { | |
774 | /* | |
775 | * allow APs to start initializing. | |
776 | */ | |
cfc1b9a6 | 777 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 778 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 779 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
780 | |
781 | /* | |
782 | * Wait 5s total for a response | |
783 | */ | |
784 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 785 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
786 | break; /* It has booted */ |
787 | udelay(100); | |
788 | } | |
789 | ||
c2d1cec1 | 790 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cb3c8b90 | 791 | /* number CPUs logically, starting from 1 (BSP is 0) */ |
cfc1b9a6 | 792 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
793 | printk(KERN_INFO "CPU%d: ", cpu); |
794 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 795 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
796 | } else { |
797 | boot_error = 1; | |
798 | if (*((volatile unsigned char *)trampoline_base) | |
799 | == 0xA5) | |
800 | /* trampoline started but...? */ | |
801 | printk(KERN_ERR "Stuck ??\n"); | |
802 | else | |
803 | /* trampoline code not run */ | |
804 | printk(KERN_ERR "Not responding.\n"); | |
25dc0049 IM |
805 | if (apic->inquire_remote_apic) |
806 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
807 | } |
808 | } | |
1a51e3a0 | 809 | |
cb3c8b90 GOC |
810 | if (boot_error) { |
811 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 812 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
813 | |
814 | /* was set by do_boot_cpu() */ | |
815 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
816 | ||
817 | /* was set by cpu_init() */ | |
818 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
819 | ||
820 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
821 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
822 | } | |
823 | ||
824 | /* mark "stuck" area as not stuck */ | |
825 | *((volatile unsigned long *)trampoline_base) = 0; | |
826 | ||
02421f98 YL |
827 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
828 | /* | |
829 | * Cleanup possible dangling ends... | |
830 | */ | |
831 | smpboot_restore_warm_reset_vector(); | |
832 | } | |
63d38198 | 833 | |
cb3c8b90 GOC |
834 | return boot_error; |
835 | } | |
836 | ||
837 | int __cpuinit native_cpu_up(unsigned int cpu) | |
838 | { | |
a21769a4 | 839 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
840 | unsigned long flags; |
841 | int err; | |
842 | ||
843 | WARN_ON(irqs_disabled()); | |
844 | ||
cfc1b9a6 | 845 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
846 | |
847 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
848 | !physid_isset(apicid, phys_cpu_present_map)) { | |
849 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | /* | |
854 | * Already booted CPU? | |
855 | */ | |
c2d1cec1 | 856 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 857 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
858 | return -ENOSYS; |
859 | } | |
860 | ||
861 | /* | |
862 | * Save current MTRR state in case it was changed since early boot | |
863 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
864 | */ | |
865 | mtrr_save_state(); | |
866 | ||
867 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
868 | ||
869 | #ifdef CONFIG_X86_32 | |
870 | /* init low mem mapping */ | |
68db065c | 871 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 872 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 873 | flush_tlb_all(); |
61165d7a | 874 | low_mappings = 1; |
cb3c8b90 GOC |
875 | |
876 | err = do_boot_cpu(apicid, cpu); | |
61165d7a | 877 | |
55cd6367 | 878 | zap_low_mappings(false); |
61165d7a HD |
879 | low_mappings = 0; |
880 | #else | |
881 | err = do_boot_cpu(apicid, cpu); | |
882 | #endif | |
883 | if (err) { | |
cfc1b9a6 | 884 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 885 | return -EIO; |
cb3c8b90 GOC |
886 | } |
887 | ||
888 | /* | |
889 | * Check TSC synchronization with the AP (keep irqs disabled | |
890 | * while doing so): | |
891 | */ | |
892 | local_irq_save(flags); | |
893 | check_tsc_sync_source(cpu); | |
894 | local_irq_restore(flags); | |
895 | ||
7c04e64a | 896 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
897 | cpu_relax(); |
898 | touch_nmi_watchdog(); | |
899 | } | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
8aef135c GOC |
904 | /* |
905 | * Fall back to non SMP mode after errors. | |
906 | * | |
907 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
908 | */ | |
909 | static __init void disable_smp(void) | |
910 | { | |
4f062896 RR |
911 | init_cpu_present(cpumask_of(0)); |
912 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 913 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 914 | |
8aef135c | 915 | if (smp_found_config) |
b6df1b8b | 916 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 917 | else |
b6df1b8b | 918 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 919 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
920 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
921 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
922 | } |
923 | ||
924 | /* | |
925 | * Various sanity checks. | |
926 | */ | |
927 | static int __init smp_sanity_check(unsigned max_cpus) | |
928 | { | |
ac23d4ee | 929 | preempt_disable(); |
a58f03b0 | 930 | |
1ff2f20d | 931 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
932 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
933 | unsigned int cpu; | |
934 | unsigned nr; | |
935 | ||
936 | printk(KERN_WARNING | |
937 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 938 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
939 | |
940 | nr = 0; | |
941 | for_each_present_cpu(cpu) { | |
942 | if (nr >= 8) | |
c2d1cec1 | 943 | set_cpu_present(cpu, false); |
a58f03b0 YL |
944 | nr++; |
945 | } | |
946 | ||
947 | nr = 0; | |
948 | for_each_possible_cpu(cpu) { | |
949 | if (nr >= 8) | |
c2d1cec1 | 950 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
951 | nr++; |
952 | } | |
953 | ||
954 | nr_cpu_ids = 8; | |
955 | } | |
956 | #endif | |
957 | ||
8aef135c | 958 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
959 | printk(KERN_WARNING |
960 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
961 | hard_smp_processor_id()); | |
962 | ||
8aef135c GOC |
963 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
964 | } | |
965 | ||
966 | /* | |
967 | * If we couldn't find an SMP configuration at boot time, | |
968 | * get out of here now! | |
969 | */ | |
970 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 971 | preempt_enable(); |
8aef135c GOC |
972 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
973 | disable_smp(); | |
974 | if (APIC_init_uniprocessor()) | |
975 | printk(KERN_NOTICE "Local APIC not detected." | |
976 | " Using dummy APIC emulation.\n"); | |
977 | return -1; | |
978 | } | |
979 | ||
980 | /* | |
981 | * Should not be necessary because the MP table should list the boot | |
982 | * CPU too, but we do it for the sake of robustness anyway. | |
983 | */ | |
a27a6210 | 984 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
985 | printk(KERN_NOTICE |
986 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
987 | boot_cpu_physical_apicid); | |
988 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
989 | } | |
ac23d4ee | 990 | preempt_enable(); |
8aef135c GOC |
991 | |
992 | /* | |
993 | * If we couldn't find a local APIC, then get out of here now! | |
994 | */ | |
995 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
996 | !cpu_has_apic) { | |
103428e5 CG |
997 | if (!disable_apic) { |
998 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
999 | boot_cpu_physical_apicid); | |
1000 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1001 | "(tell your hw vendor)\n"); |
103428e5 | 1002 | } |
8aef135c | 1003 | smpboot_clear_io_apic(); |
65a4e574 | 1004 | arch_disable_smp_support(); |
8aef135c GOC |
1005 | return -1; |
1006 | } | |
1007 | ||
1008 | verify_local_APIC(); | |
1009 | ||
1010 | /* | |
1011 | * If SMP should be disabled, then really disable it! | |
1012 | */ | |
1013 | if (!max_cpus) { | |
73d08e63 | 1014 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1015 | smpboot_clear_io_apic(); |
d54db1ac MR |
1016 | |
1017 | localise_nmi_watchdog(); | |
1018 | ||
e90955c2 | 1019 | connect_bsp_APIC(); |
e90955c2 JB |
1020 | setup_local_APIC(); |
1021 | end_local_APIC_setup(); | |
8aef135c GOC |
1022 | return -1; |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | static void __init smp_cpu_index_default(void) | |
1029 | { | |
1030 | int i; | |
1031 | struct cpuinfo_x86 *c; | |
1032 | ||
7c04e64a | 1033 | for_each_possible_cpu(i) { |
8aef135c GOC |
1034 | c = &cpu_data(i); |
1035 | /* mark all to hotplug */ | |
9628937d | 1036 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1037 | } |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1042 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1043 | */ | |
1044 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1045 | { | |
7ad728f9 RR |
1046 | unsigned int i; |
1047 | ||
deef3250 | 1048 | preempt_disable(); |
8aef135c GOC |
1049 | smp_cpu_index_default(); |
1050 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1051 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1052 | mb(); |
1053 | /* | |
1054 | * Setup boot CPU information | |
1055 | */ | |
1056 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1057 | #ifdef CONFIG_X86_32 |
8aef135c | 1058 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1059 | #endif |
8aef135c | 1060 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 RR |
1061 | for_each_possible_cpu(i) { |
1062 | alloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); | |
1063 | alloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
155dd720 | 1064 | alloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); |
7ad728f9 RR |
1065 | cpumask_clear(per_cpu(cpu_core_map, i)); |
1066 | cpumask_clear(per_cpu(cpu_sibling_map, i)); | |
155dd720 | 1067 | cpumask_clear(cpu_data(i).llc_shared_map); |
7ad728f9 | 1068 | } |
8aef135c GOC |
1069 | set_cpu_sibling_map(0); |
1070 | ||
6e1cb38a | 1071 | enable_IR_x2apic(); |
06cd9a7d | 1072 | #ifdef CONFIG_X86_64 |
72ce0165 | 1073 | default_setup_apic_routing(); |
6e1cb38a SS |
1074 | #endif |
1075 | ||
8aef135c GOC |
1076 | if (smp_sanity_check(max_cpus) < 0) { |
1077 | printk(KERN_INFO "SMP disabled\n"); | |
1078 | disable_smp(); | |
deef3250 | 1079 | goto out; |
8aef135c GOC |
1080 | } |
1081 | ||
ac23d4ee | 1082 | preempt_disable(); |
4c9961d5 | 1083 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1084 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1085 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1086 | /* Or can we switch back to PIC here? */ |
1087 | } | |
ac23d4ee | 1088 | preempt_enable(); |
8aef135c | 1089 | |
8aef135c | 1090 | connect_bsp_APIC(); |
b5841765 | 1091 | |
8aef135c GOC |
1092 | /* |
1093 | * Switch from PIC to APIC mode. | |
1094 | */ | |
1095 | setup_local_APIC(); | |
1096 | ||
8aef135c GOC |
1097 | /* |
1098 | * Enable IO APIC before setting up error vector | |
1099 | */ | |
1100 | if (!skip_ioapic_setup && nr_ioapics) | |
1101 | enable_IO_APIC(); | |
88d0f550 | 1102 | |
8aef135c GOC |
1103 | end_local_APIC_setup(); |
1104 | ||
1105 | map_cpu_to_logical_apicid(); | |
1106 | ||
d83093b5 IM |
1107 | if (apic->setup_portio_remap) |
1108 | apic->setup_portio_remap(); | |
8aef135c GOC |
1109 | |
1110 | smpboot_setup_io_apic(); | |
1111 | /* | |
1112 | * Set up local APIC timer on boot CPU. | |
1113 | */ | |
1114 | ||
1115 | printk(KERN_INFO "CPU%d: ", 0); | |
1116 | print_cpu_info(&cpu_data(0)); | |
736decac | 1117 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1118 | |
1119 | if (is_uv_system()) | |
1120 | uv_system_init(); | |
d0af9eed SS |
1121 | |
1122 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1123 | out: |
1124 | preempt_enable(); | |
8aef135c | 1125 | } |
d0af9eed SS |
1126 | |
1127 | void arch_enable_nonboot_cpus_begin(void) | |
1128 | { | |
1129 | set_mtrr_aps_delayed_init(); | |
1130 | } | |
1131 | ||
1132 | void arch_enable_nonboot_cpus_end(void) | |
1133 | { | |
1134 | mtrr_aps_init(); | |
1135 | } | |
1136 | ||
a8db8453 GOC |
1137 | /* |
1138 | * Early setup to make printk work. | |
1139 | */ | |
1140 | void __init native_smp_prepare_boot_cpu(void) | |
1141 | { | |
1142 | int me = smp_processor_id(); | |
552be871 | 1143 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1144 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1145 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1146 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1147 | } | |
1148 | ||
83f7eb9c GOC |
1149 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1150 | { | |
cfc1b9a6 | 1151 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1152 | |
1153 | impress_friends(); | |
83f7eb9c GOC |
1154 | #ifdef CONFIG_X86_IO_APIC |
1155 | setup_ioapic_dest(); | |
1156 | #endif | |
1157 | check_nmi_watchdog(); | |
d0af9eed | 1158 | mtrr_aps_init(); |
83f7eb9c GOC |
1159 | } |
1160 | ||
3b11ce7f MT |
1161 | static int __initdata setup_possible_cpus = -1; |
1162 | static int __init _setup_possible_cpus(char *str) | |
1163 | { | |
1164 | get_option(&str, &setup_possible_cpus); | |
1165 | return 0; | |
1166 | } | |
1167 | early_param("possible_cpus", _setup_possible_cpus); | |
1168 | ||
1169 | ||
68a1c3f8 | 1170 | /* |
4f062896 | 1171 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1172 | * are onlined, or offlined. The reason is per-cpu data-structures |
1173 | * are allocated by some modules at init time, and dont expect to | |
1174 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1175 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1176 | * In case when cpu_hotplug is not compiled, then we resort to current |
1177 | * behaviour, which is cpu_possible == cpu_present. | |
1178 | * - Ashok Raj | |
1179 | * | |
1180 | * Three ways to find out the number of additional hotplug CPUs: | |
1181 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1182 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1183 | * - Otherwise don't reserve additional CPUs. |
1184 | * We do this because additional CPUs waste a lot of memory. | |
1185 | * -AK | |
1186 | */ | |
1187 | __init void prefill_possible_map(void) | |
1188 | { | |
cb48bb59 | 1189 | int i, possible; |
68a1c3f8 | 1190 | |
329513a3 YL |
1191 | /* no processor from mptable or madt */ |
1192 | if (!num_processors) | |
1193 | num_processors = 1; | |
1194 | ||
3b11ce7f MT |
1195 | if (setup_possible_cpus == -1) |
1196 | possible = num_processors + disabled_cpus; | |
1197 | else | |
1198 | possible = setup_possible_cpus; | |
1199 | ||
730cf272 MT |
1200 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1201 | ||
3b11ce7f MT |
1202 | if (possible > CONFIG_NR_CPUS) { |
1203 | printk(KERN_WARNING | |
1204 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1205 | possible, CONFIG_NR_CPUS); | |
1206 | possible = CONFIG_NR_CPUS; | |
1207 | } | |
68a1c3f8 GC |
1208 | |
1209 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1210 | possible, max_t(int, possible - num_processors, 0)); | |
1211 | ||
1212 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1213 | set_cpu_possible(i, true); |
3461b0af MT |
1214 | |
1215 | nr_cpu_ids = possible; | |
68a1c3f8 | 1216 | } |
69c18c15 | 1217 | |
14adf855 CE |
1218 | #ifdef CONFIG_HOTPLUG_CPU |
1219 | ||
1220 | static void remove_siblinginfo(int cpu) | |
1221 | { | |
1222 | int sibling; | |
1223 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1224 | ||
c2d1cec1 MT |
1225 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1226 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1227 | /*/ |
1228 | * last thread sibling in this cpu core going down | |
1229 | */ | |
c2d1cec1 | 1230 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1231 | cpu_data(sibling).booted_cores--; |
1232 | } | |
1233 | ||
c2d1cec1 MT |
1234 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1235 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1236 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1237 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1238 | c->phys_proc_id = 0; |
1239 | c->cpu_core_id = 0; | |
c2d1cec1 | 1240 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1241 | } |
1242 | ||
69c18c15 GC |
1243 | static void __ref remove_cpu_from_maps(int cpu) |
1244 | { | |
c2d1cec1 MT |
1245 | set_cpu_online(cpu, false); |
1246 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1247 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1248 | /* was set by cpu_init() */ |
c2d1cec1 | 1249 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1250 | numa_remove_cpu(cpu); |
69c18c15 GC |
1251 | } |
1252 | ||
8227dce7 | 1253 | void cpu_disable_common(void) |
69c18c15 GC |
1254 | { |
1255 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1256 | /* |
1257 | * HACK: | |
1258 | * Allow any queued timer interrupts to get serviced | |
1259 | * This is only a temporary solution until we cleanup | |
1260 | * fixup_irqs as we do for IA64. | |
1261 | */ | |
1262 | local_irq_enable(); | |
1263 | mdelay(1); | |
1264 | ||
1265 | local_irq_disable(); | |
1266 | remove_siblinginfo(cpu); | |
1267 | ||
1268 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1269 | lock_vector_lock(); |
69c18c15 | 1270 | remove_cpu_from_maps(cpu); |
d388e5fd | 1271 | unlock_vector_lock(); |
d7b381bb | 1272 | fixup_irqs(); |
8227dce7 AN |
1273 | } |
1274 | ||
1275 | int native_cpu_disable(void) | |
1276 | { | |
1277 | int cpu = smp_processor_id(); | |
1278 | ||
1279 | /* | |
1280 | * Perhaps use cpufreq to drop frequency, but that could go | |
1281 | * into generic code. | |
1282 | * | |
1283 | * We won't take down the boot processor on i386 due to some | |
1284 | * interrupts only being able to be serviced by the BSP. | |
1285 | * Especially so if we're not using an IOAPIC -zwane | |
1286 | */ | |
1287 | if (cpu == 0) | |
1288 | return -EBUSY; | |
1289 | ||
1290 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1291 | stop_apic_nmi_watchdog(NULL); | |
1292 | clear_local_APIC(); | |
1293 | ||
1294 | cpu_disable_common(); | |
69c18c15 GC |
1295 | return 0; |
1296 | } | |
1297 | ||
93be71b6 | 1298 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1299 | { |
1300 | /* We don't do anything here: idle task is faking death itself. */ | |
1301 | unsigned int i; | |
1302 | ||
1303 | for (i = 0; i < 10; i++) { | |
1304 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1305 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1306 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1307 | if (1 == num_online_cpus()) | |
1308 | alternatives_smp_switch(0); | |
1309 | return; | |
1310 | } | |
1311 | msleep(100); | |
1312 | } | |
1313 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1314 | } | |
a21f5d88 AN |
1315 | |
1316 | void play_dead_common(void) | |
1317 | { | |
1318 | idle_task_exit(); | |
1319 | reset_lazy_tlbstate(); | |
1320 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1321 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1322 | |
1323 | mb(); | |
1324 | /* Ack it */ | |
1325 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1326 | ||
1327 | /* | |
1328 | * With physical CPU hotplug, we should halt the cpu | |
1329 | */ | |
1330 | local_irq_disable(); | |
1331 | } | |
1332 | ||
1333 | void native_play_dead(void) | |
1334 | { | |
1335 | play_dead_common(); | |
86886e55 | 1336 | tboot_shutdown(TB_SHUTDOWN_WFS); |
a21f5d88 AN |
1337 | wbinvd_halt(); |
1338 | } | |
1339 | ||
69c18c15 | 1340 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1341 | int native_cpu_disable(void) |
69c18c15 GC |
1342 | { |
1343 | return -ENOSYS; | |
1344 | } | |
1345 | ||
93be71b6 | 1346 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1347 | { |
1348 | /* We said "no" in __cpu_disable */ | |
1349 | BUG(); | |
1350 | } | |
a21f5d88 AN |
1351 | |
1352 | void native_play_dead(void) | |
1353 | { | |
1354 | BUG(); | |
1355 | } | |
1356 | ||
68a1c3f8 | 1357 | #endif |