Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
1da177e4 | 43 | #include <linux/bootmem.h> |
f3705136 ZM |
44 | #include <linux/notifier.h> |
45 | #include <linux/cpu.h> | |
46 | #include <linux/percpu.h> | |
d04f41e3 | 47 | #include <linux/nmi.h> |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
1da177e4 LT |
55 | |
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
7ce0bcfd | 59 | #include <asm/vmi.h> |
2b1f6278 | 60 | #include <asm/mtrr.h> |
1da177e4 LT |
61 | |
62 | /* Set if we find a B stepping CPU */ | |
f2206ec9 | 63 | static int __cpuinitdata smp_b_stepping; |
1da177e4 LT |
64 | |
65 | /* Number of siblings per CPU package */ | |
66 | int smp_num_siblings = 1; | |
129f6946 | 67 | EXPORT_SYMBOL(smp_num_siblings); |
d720803a | 68 | |
1e9f28fa | 69 | /* Last level cache ID of each logical CPU */ |
b6278470 | 70 | DEFINE_PER_CPU(u8, cpu_llc_id) = BAD_APICID; |
1e9f28fa | 71 | |
94605eff | 72 | /* representing HT siblings of each logical CPU */ |
d5a7430d MT |
73 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); |
74 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
d720803a | 75 | |
94605eff | 76 | /* representing HT and core siblings of each logical CPU */ |
08357611 MT |
77 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); |
78 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
d720803a | 79 | |
1da177e4 | 80 | /* bitmap of online cpus */ |
6c036527 | 81 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 82 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
83 | |
84 | cpumask_t cpu_callin_map; | |
85 | cpumask_t cpu_callout_map; | |
4ad8d383 ZM |
86 | cpumask_t cpu_possible_map; |
87 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
88 | static cpumask_t smp_commenced_mask; |
89 | ||
90 | /* Per CPU bogomips and other parameters */ | |
92cb7612 MT |
91 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); |
92 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
1da177e4 | 93 | |
71fff5e6 MT |
94 | /* |
95 | * The following static array is used during kernel startup | |
96 | * and the x86_cpu_to_apicid_ptr contains the address of the | |
97 | * array during this time. Is it zeroed when the per_cpu | |
98 | * data area is removed. | |
99 | */ | |
100 | u8 x86_cpu_to_apicid_init[NR_CPUS] __initdata = | |
101 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
102 | void *x86_cpu_to_apicid_ptr; | |
103 | DEFINE_PER_CPU(u8, x86_cpu_to_apicid) = BAD_APICID; | |
104 | EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
1da177e4 | 105 | |
3b08606d | 106 | u8 apicid_2_node[MAX_APICID]; |
107 | ||
1da177e4 LT |
108 | /* |
109 | * Trampoline 80x86 program as an array. | |
110 | */ | |
111 | ||
121d7bf5 JB |
112 | extern const unsigned char trampoline_data []; |
113 | extern const unsigned char trampoline_end []; | |
1da177e4 LT |
114 | static unsigned char *trampoline_base; |
115 | static int trampoline_exec; | |
116 | ||
117 | static void map_cpu_to_logical_apicid(void); | |
118 | ||
f3705136 ZM |
119 | /* State of each CPU. */ |
120 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
121 | ||
1da177e4 LT |
122 | /* |
123 | * Currently trivial. Write the real->protected mode | |
124 | * bootstrap into the page concerned. The caller | |
125 | * has made sure it's suitably aligned. | |
126 | */ | |
127 | ||
8957ecab | 128 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
129 | { |
130 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
131 | return virt_to_phys(trampoline_base); | |
132 | } | |
133 | ||
134 | /* | |
135 | * We are called very early to get the low memory for the | |
136 | * SMP bootup trampoline page. | |
137 | */ | |
138 | void __init smp_alloc_memory(void) | |
139 | { | |
140 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
141 | /* | |
142 | * Has to be in very low memory so we can execute | |
143 | * real-mode AP code. | |
144 | */ | |
145 | if (__pa(trampoline_base) >= 0x9F000) | |
146 | BUG(); | |
147 | /* | |
148 | * Make the SMP trampoline executable: | |
149 | */ | |
150 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
151 | } | |
152 | ||
153 | /* | |
154 | * The bootstrap kernel entry code has set these up. Save them for | |
155 | * a given CPU | |
156 | */ | |
157 | ||
724faa89 | 158 | void __cpuinit smp_store_cpu_info(int id) |
1da177e4 | 159 | { |
92cb7612 | 160 | struct cpuinfo_x86 *c = &cpu_data(id); |
1da177e4 LT |
161 | |
162 | *c = boot_cpu_data; | |
92cb7612 | 163 | c->cpu_index = id; |
1da177e4 | 164 | if (id!=0) |
a6c4e076 | 165 | identify_secondary_cpu(c); |
1da177e4 LT |
166 | /* |
167 | * Mask B, Pentium, but not Pentium MMX | |
168 | */ | |
169 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
170 | c->x86 == 5 && | |
171 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
172 | c->x86_model <= 3) | |
173 | /* | |
174 | * Remember we have B step Pentia with bugs | |
175 | */ | |
176 | smp_b_stepping = 1; | |
177 | ||
178 | /* | |
179 | * Certain Athlons might work (for various values of 'work') in SMP | |
180 | * but they are not certified as MP capable. | |
181 | */ | |
182 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
183 | ||
3ca113ea DJ |
184 | if (num_possible_cpus() == 1) |
185 | goto valid_k7; | |
186 | ||
1da177e4 LT |
187 | /* Athlon 660/661 is valid. */ |
188 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
189 | goto valid_k7; | |
190 | ||
191 | /* Duron 670 is valid */ | |
192 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
193 | goto valid_k7; | |
194 | ||
195 | /* | |
196 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
197 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
198 | * have the MP bit set. | |
199 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
200 | */ | |
201 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
202 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
203 | (c->x86_model> 7)) | |
204 | if (cpu_has_mp) | |
205 | goto valid_k7; | |
206 | ||
207 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 208 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
209 | } |
210 | ||
211 | valid_k7: | |
212 | ; | |
213 | } | |
214 | ||
1da177e4 LT |
215 | extern void calibrate_delay(void); |
216 | ||
217 | static atomic_t init_deasserted; | |
218 | ||
4a5d107a | 219 | static void __cpuinit smp_callin(void) |
1da177e4 LT |
220 | { |
221 | int cpuid, phys_id; | |
222 | unsigned long timeout; | |
223 | ||
224 | /* | |
225 | * If waken up by an INIT in an 82489DX configuration | |
226 | * we may get here before an INIT-deassert IPI reaches | |
227 | * our local APIC. We have to wait for the IPI or we'll | |
228 | * lock up on an APIC access. | |
229 | */ | |
230 | wait_for_init_deassert(&init_deasserted); | |
231 | ||
232 | /* | |
233 | * (This works even if the APIC is not enabled.) | |
234 | */ | |
235 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
236 | cpuid = smp_processor_id(); | |
237 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
238 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
239 | phys_id, cpuid); | |
240 | BUG(); | |
241 | } | |
242 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
243 | ||
244 | /* | |
245 | * STARTUP IPIs are fragile beasts as they might sometimes | |
246 | * trigger some glue motherboard logic. Complete APIC bus | |
247 | * silence for 1 second, this overestimates the time the | |
248 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
249 | * by a factor of two. This should be enough. | |
250 | */ | |
251 | ||
252 | /* | |
253 | * Waiting 2s total for startup (udelay is not yet working) | |
254 | */ | |
255 | timeout = jiffies + 2*HZ; | |
256 | while (time_before(jiffies, timeout)) { | |
257 | /* | |
258 | * Has the boot CPU finished it's STARTUP sequence? | |
259 | */ | |
260 | if (cpu_isset(cpuid, cpu_callout_map)) | |
261 | break; | |
262 | rep_nop(); | |
263 | } | |
264 | ||
265 | if (!time_before(jiffies, timeout)) { | |
266 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
267 | cpuid); | |
268 | BUG(); | |
269 | } | |
270 | ||
271 | /* | |
272 | * the boot CPU has finished the init stage and is spinning | |
273 | * on callin_map until we finish. We are free to set up this | |
274 | * CPU, first the APIC. (this is probably redundant on most | |
275 | * boards) | |
276 | */ | |
277 | ||
278 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
279 | smp_callin_clear_local_apic(); | |
280 | setup_local_APIC(); | |
281 | map_cpu_to_logical_apicid(); | |
282 | ||
283 | /* | |
284 | * Get our bogomips. | |
285 | */ | |
286 | calibrate_delay(); | |
287 | Dprintk("Stack at about %p\n",&cpuid); | |
288 | ||
289 | /* | |
290 | * Save our processor parameters | |
291 | */ | |
e9e2cdb4 | 292 | smp_store_cpu_info(cpuid); |
1da177e4 LT |
293 | |
294 | /* | |
295 | * Allow the master to continue. | |
296 | */ | |
297 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
298 | } |
299 | ||
300 | static int cpucount; | |
301 | ||
1e9f28fa SS |
302 | /* maps the cpu to the sched domain representing multi-core */ |
303 | cpumask_t cpu_coregroup_map(int cpu) | |
304 | { | |
92cb7612 | 305 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
1e9f28fa SS |
306 | /* |
307 | * For perf, we return last level cache shared map. | |
5c45bf27 | 308 | * And for power savings, we return cpu_core_map |
1e9f28fa | 309 | */ |
5c45bf27 | 310 | if (sched_mc_power_savings || sched_smt_power_savings) |
08357611 | 311 | return per_cpu(cpu_core_map, cpu); |
5c45bf27 SS |
312 | else |
313 | return c->llc_shared_map; | |
1e9f28fa SS |
314 | } |
315 | ||
94605eff SS |
316 | /* representing cpus for which sibling maps can be computed */ |
317 | static cpumask_t cpu_sibling_setup_map; | |
318 | ||
fbab6e7a | 319 | void __cpuinit set_cpu_sibling_map(int cpu) |
d720803a LS |
320 | { |
321 | int i; | |
92cb7612 | 322 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
94605eff SS |
323 | |
324 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
325 | |
326 | if (smp_num_siblings > 1) { | |
94605eff | 327 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
92cb7612 MT |
328 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && |
329 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
d5a7430d MT |
330 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); |
331 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
08357611 MT |
332 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
333 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
92cb7612 MT |
334 | cpu_set(i, c->llc_shared_map); |
335 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
d720803a LS |
336 | } |
337 | } | |
338 | } else { | |
d5a7430d | 339 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); |
d720803a LS |
340 | } |
341 | ||
92cb7612 | 342 | cpu_set(cpu, c->llc_shared_map); |
1e9f28fa | 343 | |
94605eff | 344 | if (current_cpu_data.x86_max_cores == 1) { |
d5a7430d | 345 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); |
92cb7612 | 346 | c->booted_cores = 1; |
94605eff SS |
347 | return; |
348 | } | |
349 | ||
350 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
b6278470 MT |
351 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
352 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
92cb7612 MT |
353 | cpu_set(i, c->llc_shared_map); |
354 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
1e9f28fa | 355 | } |
92cb7612 | 356 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { |
08357611 MT |
357 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
358 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
94605eff SS |
359 | /* |
360 | * Does this new cpu bringup a new core? | |
361 | */ | |
d5a7430d | 362 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { |
94605eff SS |
363 | /* |
364 | * for each core in package, increment | |
365 | * the booted_cores for this new cpu | |
366 | */ | |
d5a7430d | 367 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) |
92cb7612 | 368 | c->booted_cores++; |
94605eff SS |
369 | /* |
370 | * increment the core count for all | |
371 | * the other cpus in this package | |
372 | */ | |
373 | if (i != cpu) | |
92cb7612 MT |
374 | cpu_data(i).booted_cores++; |
375 | } else if (i != cpu && !c->booted_cores) | |
376 | c->booted_cores = cpu_data(i).booted_cores; | |
94605eff | 377 | } |
d720803a LS |
378 | } |
379 | } | |
380 | ||
1da177e4 LT |
381 | /* |
382 | * Activate a secondary processor. | |
383 | */ | |
4a5d107a | 384 | static void __cpuinit start_secondary(void *unused) |
1da177e4 LT |
385 | { |
386 | /* | |
d2cbcc49 RR |
387 | * Don't put *anything* before cpu_init(), SMP booting is too |
388 | * fragile that we want to limit the things done here to the | |
389 | * most necessary things. | |
1da177e4 | 390 | */ |
7ce0bcfd ZA |
391 | #ifdef CONFIG_VMI |
392 | vmi_bringup(); | |
393 | #endif | |
d2cbcc49 | 394 | cpu_init(); |
5bfb5d69 | 395 | preempt_disable(); |
1da177e4 LT |
396 | smp_callin(); |
397 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
398 | rep_nop(); | |
95492e46 IM |
399 | /* |
400 | * Check TSC synchronization with the BP: | |
401 | */ | |
402 | check_tsc_sync_target(); | |
403 | ||
bbab4f3b | 404 | setup_secondary_clock(); |
1da177e4 LT |
405 | if (nmi_watchdog == NMI_IO_APIC) { |
406 | disable_8259A_irq(0); | |
407 | enable_NMI_through_LVT0(NULL); | |
408 | enable_8259A_irq(0); | |
409 | } | |
1da177e4 LT |
410 | /* |
411 | * low-memory mappings have been cleared, flush them from | |
412 | * the local TLBs too. | |
413 | */ | |
414 | local_flush_tlb(); | |
6fe940d6 | 415 | |
d720803a LS |
416 | /* This must be done before setting cpu_online_map */ |
417 | set_cpu_sibling_map(raw_smp_processor_id()); | |
418 | wmb(); | |
419 | ||
6fe940d6 LS |
420 | /* |
421 | * We need to hold call_lock, so there is no inconsistency | |
422 | * between the time smp_call_function() determines number of | |
27b46d76 | 423 | * IPI recipients, and the time when the determination is made |
6fe940d6 LS |
424 | * for which cpus receive the IPI. Holding this |
425 | * lock helps us to not include this cpu in a currently in progress | |
426 | * smp_call_function(). | |
427 | */ | |
428 | lock_ipi_call_lock(); | |
1da177e4 | 429 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 430 | unlock_ipi_call_lock(); |
e1367daf | 431 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
432 | |
433 | /* We can take interrupts now: we're officially "up". */ | |
434 | local_irq_enable(); | |
435 | ||
436 | wmb(); | |
437 | cpu_idle(); | |
438 | } | |
439 | ||
440 | /* | |
441 | * Everything has been set up for the secondary | |
442 | * CPUs - they just need to reload everything | |
443 | * from the task structure | |
444 | * This function must not return. | |
445 | */ | |
0bb3184d | 446 | void __devinit initialize_secondary(void) |
1da177e4 LT |
447 | { |
448 | /* | |
449 | * We don't actually need to load the full TSS, | |
450 | * basically just the stack pointer and the eip. | |
451 | */ | |
452 | ||
453 | asm volatile( | |
454 | "movl %0,%%esp\n\t" | |
455 | "jmp *%1" | |
456 | : | |
62111195 | 457 | :"m" (current->thread.esp),"m" (current->thread.eip)); |
1da177e4 LT |
458 | } |
459 | ||
62111195 | 460 | /* Static state in head.S used to set up a CPU */ |
1da177e4 LT |
461 | extern struct { |
462 | void * esp; | |
463 | unsigned short ss; | |
464 | } stack_start; | |
465 | ||
466 | #ifdef CONFIG_NUMA | |
467 | ||
468 | /* which logical CPUs are on which nodes */ | |
6c036527 | 469 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 | 470 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
a406c366 | 471 | EXPORT_SYMBOL(node_2_cpu_mask); |
1da177e4 | 472 | /* which node each logical CPU is on */ |
6c036527 | 473 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
474 | EXPORT_SYMBOL(cpu_2_node); |
475 | ||
476 | /* set up a mapping between cpu and node. */ | |
477 | static inline void map_cpu_to_node(int cpu, int node) | |
478 | { | |
479 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
480 | cpu_set(cpu, node_2_cpu_mask[node]); | |
481 | cpu_2_node[cpu] = node; | |
482 | } | |
483 | ||
484 | /* undo a mapping between cpu and node. */ | |
485 | static inline void unmap_cpu_to_node(int cpu) | |
486 | { | |
487 | int node; | |
488 | ||
489 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
490 | for (node = 0; node < MAX_NUMNODES; node ++) | |
491 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
492 | cpu_2_node[cpu] = 0; | |
493 | } | |
494 | #else /* !CONFIG_NUMA */ | |
495 | ||
496 | #define map_cpu_to_node(cpu, node) ({}) | |
497 | #define unmap_cpu_to_node(cpu) ({}) | |
498 | ||
499 | #endif /* CONFIG_NUMA */ | |
500 | ||
6c036527 | 501 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
502 | |
503 | static void map_cpu_to_logical_apicid(void) | |
504 | { | |
505 | int cpu = smp_processor_id(); | |
506 | int apicid = logical_smp_processor_id(); | |
78b656b8 | 507 | int node = apicid_to_node(apicid); |
bfa0e9a0 | 508 | |
509 | if (!node_online(node)) | |
510 | node = first_online_node; | |
1da177e4 LT |
511 | |
512 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 513 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
514 | } |
515 | ||
516 | static void unmap_cpu_to_logical_apicid(int cpu) | |
517 | { | |
518 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
519 | unmap_cpu_to_node(cpu); | |
520 | } | |
521 | ||
1da177e4 LT |
522 | static inline void __inquire_remote_apic(int apicid) |
523 | { | |
524 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
525 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
4312fa81 FLV |
526 | int timeout; |
527 | unsigned long status; | |
1da177e4 LT |
528 | |
529 | printk("Inquiring remote APIC #%d...\n", apicid); | |
530 | ||
38e548ee | 531 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
532 | printk("... APIC #%d %s: ", apicid, names[i]); |
533 | ||
534 | /* | |
535 | * Wait for idle. | |
536 | */ | |
4312fa81 FLV |
537 | status = safe_apic_wait_icr_idle(); |
538 | if (status) | |
539 | printk("a previous APIC delivery may have failed\n"); | |
1da177e4 LT |
540 | |
541 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
542 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
543 | ||
544 | timeout = 0; | |
545 | do { | |
546 | udelay(100); | |
547 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
548 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
549 | ||
550 | switch (status) { | |
551 | case APIC_ICR_RR_VALID: | |
552 | status = apic_read(APIC_RRR); | |
ec1180db | 553 | printk("%lx\n", status); |
1da177e4 LT |
554 | break; |
555 | default: | |
556 | printk("failed\n"); | |
557 | } | |
558 | } | |
559 | } | |
1da177e4 LT |
560 | |
561 | #ifdef WAKE_SECONDARY_VIA_NMI | |
562 | /* | |
563 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
564 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
565 | * won't ... remember to clear down the APIC, etc later. | |
566 | */ | |
0bb3184d | 567 | static int __devinit |
1da177e4 LT |
568 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
569 | { | |
ae08e43e FLV |
570 | unsigned long send_status, accept_status = 0; |
571 | int maxlvt; | |
1da177e4 LT |
572 | |
573 | /* Target chip */ | |
574 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
575 | ||
576 | /* Boot on the stack */ | |
577 | /* Kick the second */ | |
578 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
579 | ||
580 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 581 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
582 | |
583 | /* | |
584 | * Give the other CPU some time to accept the IPI. | |
585 | */ | |
586 | udelay(200); | |
587 | /* | |
588 | * Due to the Pentium erratum 3AP. | |
589 | */ | |
e05d723f | 590 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
591 | if (maxlvt > 3) { |
592 | apic_read_around(APIC_SPIV); | |
593 | apic_write(APIC_ESR, 0); | |
594 | } | |
595 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
596 | Dprintk("NMI sent.\n"); | |
597 | ||
598 | if (send_status) | |
599 | printk("APIC never delivered???\n"); | |
600 | if (accept_status) | |
601 | printk("APIC delivery error (%lx).\n", accept_status); | |
602 | ||
603 | return (send_status | accept_status); | |
604 | } | |
605 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
606 | ||
607 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 608 | static int __devinit |
1da177e4 LT |
609 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
610 | { | |
ae08e43e FLV |
611 | unsigned long send_status, accept_status = 0; |
612 | int maxlvt, num_starts, j; | |
1da177e4 LT |
613 | |
614 | /* | |
615 | * Be paranoid about clearing APIC errors. | |
616 | */ | |
617 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
618 | apic_read_around(APIC_SPIV); | |
619 | apic_write(APIC_ESR, 0); | |
620 | apic_read(APIC_ESR); | |
621 | } | |
622 | ||
623 | Dprintk("Asserting INIT.\n"); | |
624 | ||
625 | /* | |
626 | * Turn INIT on target chip | |
627 | */ | |
628 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
629 | ||
630 | /* | |
631 | * Send IPI | |
632 | */ | |
633 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
634 | | APIC_DM_INIT); | |
635 | ||
636 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 637 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
638 | |
639 | mdelay(10); | |
640 | ||
641 | Dprintk("Deasserting INIT.\n"); | |
642 | ||
643 | /* Target chip */ | |
644 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
645 | ||
646 | /* Send IPI */ | |
647 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
648 | ||
649 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 650 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
651 | |
652 | atomic_set(&init_deasserted, 1); | |
653 | ||
654 | /* | |
655 | * Should we send STARTUP IPIs ? | |
656 | * | |
657 | * Determine this based on the APIC version. | |
658 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
659 | */ | |
660 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
661 | num_starts = 2; | |
662 | else | |
663 | num_starts = 0; | |
664 | ||
ae5da273 ZA |
665 | /* |
666 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
667 | * target processor state. | |
668 | */ | |
669 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
670 | (unsigned long) stack_start.esp); | |
671 | ||
1da177e4 LT |
672 | /* |
673 | * Run STARTUP IPI loop. | |
674 | */ | |
675 | Dprintk("#startup loops: %d.\n", num_starts); | |
676 | ||
e05d723f | 677 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
678 | |
679 | for (j = 1; j <= num_starts; j++) { | |
680 | Dprintk("Sending STARTUP #%d.\n",j); | |
681 | apic_read_around(APIC_SPIV); | |
682 | apic_write(APIC_ESR, 0); | |
683 | apic_read(APIC_ESR); | |
684 | Dprintk("After apic_write.\n"); | |
685 | ||
686 | /* | |
687 | * STARTUP IPI | |
688 | */ | |
689 | ||
690 | /* Target chip */ | |
691 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
692 | ||
693 | /* Boot on the stack */ | |
694 | /* Kick the second */ | |
695 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
696 | | (start_eip >> 12)); | |
697 | ||
698 | /* | |
699 | * Give the other CPU some time to accept the IPI. | |
700 | */ | |
701 | udelay(300); | |
702 | ||
703 | Dprintk("Startup point 1.\n"); | |
704 | ||
705 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 706 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
707 | |
708 | /* | |
709 | * Give the other CPU some time to accept the IPI. | |
710 | */ | |
711 | udelay(200); | |
712 | /* | |
713 | * Due to the Pentium erratum 3AP. | |
714 | */ | |
715 | if (maxlvt > 3) { | |
716 | apic_read_around(APIC_SPIV); | |
717 | apic_write(APIC_ESR, 0); | |
718 | } | |
719 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
720 | if (send_status || accept_status) | |
721 | break; | |
722 | } | |
723 | Dprintk("After Startup.\n"); | |
724 | ||
725 | if (send_status) | |
726 | printk("APIC never delivered???\n"); | |
727 | if (accept_status) | |
728 | printk("APIC delivery error (%lx).\n", accept_status); | |
729 | ||
730 | return (send_status | accept_status); | |
731 | } | |
732 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
733 | ||
734 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
735 | static inline int alloc_cpu_id(void) |
736 | { | |
737 | cpumask_t tmp_map; | |
738 | int cpu; | |
739 | cpus_complement(tmp_map, cpu_present_map); | |
740 | cpu = first_cpu(tmp_map); | |
741 | if (cpu >= NR_CPUS) | |
742 | return -ENODEV; | |
743 | return cpu; | |
744 | } | |
745 | ||
746 | #ifdef CONFIG_HOTPLUG_CPU | |
f2206ec9 AB |
747 | static struct task_struct * __cpuinitdata cpu_idle_tasks[NR_CPUS]; |
748 | static inline struct task_struct * __cpuinit alloc_idle_task(int cpu) | |
e1367daf LS |
749 | { |
750 | struct task_struct *idle; | |
751 | ||
752 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
753 | /* initialize thread_struct. we really want to avoid destroy | |
754 | * idle tread | |
755 | */ | |
07b047fc | 756 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
757 | init_idle(idle, cpu); |
758 | return idle; | |
759 | } | |
760 | idle = fork_idle(cpu); | |
761 | ||
762 | if (!IS_ERR(idle)) | |
763 | cpu_idle_tasks[cpu] = idle; | |
764 | return idle; | |
765 | } | |
766 | #else | |
767 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
768 | #endif | |
1da177e4 | 769 | |
4a5d107a | 770 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
771 | /* |
772 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
773 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
774 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
775 | */ | |
776 | { | |
777 | struct task_struct *idle; | |
778 | unsigned long boot_error; | |
e1367daf | 779 | int timeout; |
1da177e4 LT |
780 | unsigned long start_eip; |
781 | unsigned short nmi_high = 0, nmi_low = 0; | |
782 | ||
2b1f6278 BK |
783 | /* |
784 | * Save current MTRR state in case it was changed since early boot | |
785 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
786 | */ | |
787 | mtrr_save_state(); | |
788 | ||
1da177e4 LT |
789 | /* |
790 | * We can't use kernel_thread since we must avoid to | |
791 | * reschedule the child. | |
792 | */ | |
e1367daf | 793 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
794 | if (IS_ERR(idle)) |
795 | panic("failed fork for CPU %d", cpu); | |
62111195 | 796 | |
7c3576d2 JF |
797 | init_gdt(cpu); |
798 | per_cpu(current_task, cpu) = idle; | |
bf504672 | 799 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
62111195 | 800 | |
1da177e4 LT |
801 | idle->thread.eip = (unsigned long) start_secondary; |
802 | /* start_eip had better be page-aligned! */ | |
803 | start_eip = setup_trampoline(); | |
804 | ||
62111195 JF |
805 | ++cpucount; |
806 | alternatives_smp_switch(1); | |
807 | ||
1da177e4 LT |
808 | /* So we see what's up */ |
809 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
810 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
811 | stack_start.esp = (void *) idle->thread.esp; | |
812 | ||
813 | irq_ctx_init(cpu); | |
814 | ||
71fff5e6 | 815 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1da177e4 LT |
816 | /* |
817 | * This grunge runs the startup process for | |
818 | * the targeted processor. | |
819 | */ | |
820 | ||
821 | atomic_set(&init_deasserted, 0); | |
822 | ||
823 | Dprintk("Setting warm reset code and vector.\n"); | |
824 | ||
825 | store_NMI_vector(&nmi_high, &nmi_low); | |
826 | ||
827 | smpboot_setup_warm_reset_vector(start_eip); | |
828 | ||
829 | /* | |
830 | * Starting actual IPI sequence... | |
831 | */ | |
832 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
833 | ||
834 | if (!boot_error) { | |
835 | /* | |
836 | * allow APs to start initializing. | |
837 | */ | |
838 | Dprintk("Before Callout %d.\n", cpu); | |
839 | cpu_set(cpu, cpu_callout_map); | |
840 | Dprintk("After Callout %d.\n", cpu); | |
841 | ||
842 | /* | |
843 | * Wait 5s total for a response | |
844 | */ | |
845 | for (timeout = 0; timeout < 50000; timeout++) { | |
846 | if (cpu_isset(cpu, cpu_callin_map)) | |
847 | break; /* It has booted */ | |
848 | udelay(100); | |
849 | } | |
850 | ||
851 | if (cpu_isset(cpu, cpu_callin_map)) { | |
852 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
853 | Dprintk("OK.\n"); | |
854 | printk("CPU%d: ", cpu); | |
92cb7612 | 855 | print_cpu_info(&cpu_data(cpu)); |
1da177e4 LT |
856 | Dprintk("CPU has booted.\n"); |
857 | } else { | |
858 | boot_error= 1; | |
859 | if (*((volatile unsigned char *)trampoline_base) | |
860 | == 0xA5) | |
861 | /* trampoline started but...? */ | |
862 | printk("Stuck ??\n"); | |
863 | else | |
864 | /* trampoline code not run */ | |
865 | printk("Not responding.\n"); | |
866 | inquire_remote_apic(apicid); | |
867 | } | |
868 | } | |
e1367daf | 869 | |
1da177e4 LT |
870 | if (boot_error) { |
871 | /* Try to put things back the way they were before ... */ | |
872 | unmap_cpu_to_logical_apicid(cpu); | |
873 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
874 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
875 | cpucount--; | |
e1367daf | 876 | } else { |
71fff5e6 | 877 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
e1367daf | 878 | cpu_set(cpu, cpu_present_map); |
1da177e4 LT |
879 | } |
880 | ||
881 | /* mark "stuck" area as not stuck */ | |
882 | *((volatile unsigned long *)trampoline_base) = 0; | |
883 | ||
884 | return boot_error; | |
885 | } | |
886 | ||
e1367daf LS |
887 | #ifdef CONFIG_HOTPLUG_CPU |
888 | void cpu_exit_clear(void) | |
889 | { | |
890 | int cpu = raw_smp_processor_id(); | |
891 | ||
892 | idle_task_exit(); | |
893 | ||
894 | cpucount --; | |
895 | cpu_uninit(); | |
896 | irq_ctx_exit(cpu); | |
897 | ||
898 | cpu_clear(cpu, cpu_callout_map); | |
899 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
900 | |
901 | cpu_clear(cpu, smp_commenced_mask); | |
902 | unmap_cpu_to_logical_apicid(cpu); | |
903 | } | |
904 | ||
905 | struct warm_boot_cpu_info { | |
906 | struct completion *complete; | |
c4028958 | 907 | struct work_struct task; |
e1367daf LS |
908 | int apicid; |
909 | int cpu; | |
910 | }; | |
911 | ||
c4028958 | 912 | static void __cpuinit do_warm_boot_cpu(struct work_struct *work) |
e1367daf | 913 | { |
c4028958 DH |
914 | struct warm_boot_cpu_info *info = |
915 | container_of(work, struct warm_boot_cpu_info, task); | |
e1367daf LS |
916 | do_boot_cpu(info->apicid, info->cpu); |
917 | complete(info->complete); | |
918 | } | |
919 | ||
34f361ad | 920 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf | 921 | { |
6e9a4738 | 922 | DECLARE_COMPLETION_ONSTACK(done); |
e1367daf | 923 | struct warm_boot_cpu_info info; |
e1367daf LS |
924 | int apicid, ret; |
925 | ||
71fff5e6 | 926 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
e1367daf LS |
927 | if (apicid == BAD_APICID) { |
928 | ret = -ENODEV; | |
929 | goto exit; | |
930 | } | |
931 | ||
932 | info.complete = &done; | |
933 | info.apicid = apicid; | |
934 | info.cpu = cpu; | |
c4028958 | 935 | INIT_WORK(&info.task, do_warm_boot_cpu); |
e1367daf | 936 | |
e1367daf | 937 | /* init low mem mapping */ |
d7271b14 | 938 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
3b1bdf4e | 939 | min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS)); |
e1367daf | 940 | flush_tlb_all(); |
c4028958 | 941 | schedule_work(&info.task); |
e1367daf LS |
942 | wait_for_completion(&done); |
943 | ||
e1367daf LS |
944 | zap_low_mappings(); |
945 | ret = 0; | |
946 | exit: | |
e1367daf LS |
947 | return ret; |
948 | } | |
949 | #endif | |
950 | ||
1da177e4 LT |
951 | /* |
952 | * Cycle through the processors sending APIC IPIs to boot each. | |
953 | */ | |
954 | ||
955 | static int boot_cpu_logical_apicid; | |
956 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
957 | void *xquad_portio; | |
129f6946 AD |
958 | #ifdef CONFIG_X86_NUMAQ |
959 | EXPORT_SYMBOL(xquad_portio); | |
960 | #endif | |
1da177e4 | 961 | |
1da177e4 LT |
962 | static void __init smp_boot_cpus(unsigned int max_cpus) |
963 | { | |
964 | int apicid, cpu, bit, kicked; | |
965 | unsigned long bogosum = 0; | |
966 | ||
967 | /* | |
968 | * Setup boot CPU information | |
969 | */ | |
970 | smp_store_cpu_info(0); /* Final full version of the data */ | |
971 | printk("CPU%d: ", 0); | |
92cb7612 | 972 | print_cpu_info(&cpu_data(0)); |
1da177e4 | 973 | |
1e4c85f9 | 974 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 | 975 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
71fff5e6 | 976 | per_cpu(x86_cpu_to_apicid, 0) = boot_cpu_physical_apicid; |
1da177e4 LT |
977 | |
978 | current_thread_info()->cpu = 0; | |
1da177e4 | 979 | |
94605eff | 980 | set_cpu_sibling_map(0); |
3dd9d514 | 981 | |
1da177e4 LT |
982 | /* |
983 | * If we couldn't find an SMP configuration at boot time, | |
984 | * get out of here now! | |
985 | */ | |
986 | if (!smp_found_config && !acpi_lapic) { | |
987 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
988 | smpboot_clear_io_apic_irqs(); |
989 | phys_cpu_present_map = physid_mask_of_physid(0); | |
990 | if (APIC_init_uniprocessor()) | |
991 | printk(KERN_NOTICE "Local APIC not detected." | |
992 | " Using dummy APIC emulation.\n"); | |
993 | map_cpu_to_logical_apicid(); | |
d5a7430d | 994 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 995 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
1e4c85f9 LT |
996 | return; |
997 | } | |
998 | ||
999 | /* | |
1000 | * Should not be necessary because the MP table should list the boot | |
1001 | * CPU too, but we do it for the sake of robustness anyway. | |
1002 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1003 | */ | |
1004 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1005 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1006 | boot_cpu_physical_apicid); | |
1007 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1008 | } | |
1009 | ||
1010 | /* | |
1011 | * If we couldn't find a local APIC, then get out of here now! | |
1012 | */ | |
1013 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1014 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1015 | boot_cpu_physical_apicid); | |
1016 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1017 | smpboot_clear_io_apic_irqs(); | |
1018 | phys_cpu_present_map = physid_mask_of_physid(0); | |
54ffaa45 | 1019 | map_cpu_to_logical_apicid(); |
d5a7430d | 1020 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 1021 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
1da177e4 LT |
1022 | return; |
1023 | } | |
1024 | ||
1e4c85f9 LT |
1025 | verify_local_APIC(); |
1026 | ||
1da177e4 LT |
1027 | /* |
1028 | * If SMP should be disabled, then really disable it! | |
1029 | */ | |
1e4c85f9 LT |
1030 | if (!max_cpus) { |
1031 | smp_found_config = 0; | |
1032 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
3fb450a3 IM |
1033 | |
1034 | if (nmi_watchdog == NMI_LOCAL_APIC) { | |
1035 | printk(KERN_INFO "activating minimal APIC for NMI watchdog use.\n"); | |
1036 | connect_bsp_APIC(); | |
1037 | setup_local_APIC(); | |
1038 | } | |
1e4c85f9 LT |
1039 | smpboot_clear_io_apic_irqs(); |
1040 | phys_cpu_present_map = physid_mask_of_physid(0); | |
54ffaa45 | 1041 | map_cpu_to_logical_apicid(); |
d5a7430d | 1042 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 1043 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
1da177e4 LT |
1044 | return; |
1045 | } | |
1046 | ||
1e4c85f9 LT |
1047 | connect_bsp_APIC(); |
1048 | setup_local_APIC(); | |
1049 | map_cpu_to_logical_apicid(); | |
1050 | ||
1051 | ||
1da177e4 LT |
1052 | setup_portio_remap(); |
1053 | ||
1054 | /* | |
1055 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1056 | * | |
1057 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1058 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1059 | * clustered apic ID. | |
1060 | */ | |
1061 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1062 | ||
1063 | kicked = 1; | |
1064 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1065 | apicid = cpu_present_to_apicid(bit); | |
1066 | /* | |
1067 | * Don't even attempt to start the boot CPU! | |
1068 | */ | |
1069 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1070 | continue; | |
1071 | ||
1072 | if (!check_apicid_present(bit)) | |
1073 | continue; | |
1074 | if (max_cpus <= cpucount+1) | |
1075 | continue; | |
1076 | ||
e1367daf | 1077 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1078 | printk("CPU #%d not responding - cannot use it.\n", |
1079 | apicid); | |
1080 | else | |
1081 | ++kicked; | |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | * Cleanup possible dangling ends... | |
1086 | */ | |
1087 | smpboot_restore_warm_reset_vector(); | |
1088 | ||
1089 | /* | |
1090 | * Allow the user to impress friends. | |
1091 | */ | |
1092 | Dprintk("Before bogomips.\n"); | |
1093 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1094 | if (cpu_isset(cpu, cpu_callout_map)) | |
92cb7612 | 1095 | bogosum += cpu_data(cpu).loops_per_jiffy; |
1da177e4 LT |
1096 | printk(KERN_INFO |
1097 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1098 | cpucount+1, | |
1099 | bogosum/(500000/HZ), | |
1100 | (bogosum/(5000/HZ))%100); | |
1101 | ||
1102 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1103 | ||
1104 | if (smp_b_stepping) | |
1105 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1106 | ||
1107 | /* | |
1108 | * Don't taint if we are running SMP kernel on a single non-MP | |
1109 | * approved Athlon | |
1110 | */ | |
1111 | if (tainted & TAINT_UNSAFE_SMP) { | |
1112 | if (cpucount) | |
1113 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1114 | else | |
1115 | tainted &= ~TAINT_UNSAFE_SMP; | |
1116 | } | |
1117 | ||
1118 | Dprintk("Boot done.\n"); | |
1119 | ||
1120 | /* | |
d5a7430d | 1121 | * construct cpu_sibling_map, so that we can tell sibling CPUs |
1da177e4 LT |
1122 | * efficiently. |
1123 | */ | |
3dd9d514 | 1124 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
d5a7430d | 1125 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); |
08357611 | 1126 | cpus_clear(per_cpu(cpu_core_map, cpu)); |
3dd9d514 | 1127 | } |
1da177e4 | 1128 | |
d5a7430d | 1129 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 1130 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
1da177e4 | 1131 | |
1e4c85f9 LT |
1132 | smpboot_setup_io_apic(); |
1133 | ||
bbab4f3b | 1134 | setup_boot_clock(); |
1da177e4 LT |
1135 | } |
1136 | ||
1137 | /* These are wrappers to interface to the new boot process. Someone | |
1138 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
01a2f435 | 1139 | void __init native_smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 1140 | { |
f3705136 ZM |
1141 | smp_commenced_mask = cpumask_of_cpu(0); |
1142 | cpu_callin_map = cpumask_of_cpu(0); | |
1143 | mb(); | |
1da177e4 LT |
1144 | smp_boot_cpus(max_cpus); |
1145 | } | |
1146 | ||
01a2f435 | 1147 | void __init native_smp_prepare_boot_cpu(void) |
bf504672 RR |
1148 | { |
1149 | unsigned int cpu = smp_processor_id(); | |
1150 | ||
7c3576d2 | 1151 | init_gdt(cpu); |
bf504672 RR |
1152 | switch_to_new_gdt(); |
1153 | ||
1154 | cpu_set(cpu, cpu_online_map); | |
1155 | cpu_set(cpu, cpu_callout_map); | |
1156 | cpu_set(cpu, cpu_present_map); | |
1157 | cpu_set(cpu, cpu_possible_map); | |
1158 | __get_cpu_var(cpu_state) = CPU_ONLINE; | |
1da177e4 LT |
1159 | } |
1160 | ||
f3705136 | 1161 | #ifdef CONFIG_HOTPLUG_CPU |
c70df743 | 1162 | void remove_siblinginfo(int cpu) |
1da177e4 | 1163 | { |
e1367daf | 1164 | int sibling; |
92cb7612 | 1165 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
e1367daf | 1166 | |
08357611 MT |
1167 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { |
1168 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1169 | /*/ | |
94605eff SS |
1170 | * last thread sibling in this cpu core going down |
1171 | */ | |
d5a7430d | 1172 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) |
92cb7612 | 1173 | cpu_data(sibling).booted_cores--; |
94605eff SS |
1174 | } |
1175 | ||
d5a7430d MT |
1176 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) |
1177 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1178 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
08357611 | 1179 | cpus_clear(per_cpu(cpu_core_map, cpu)); |
92cb7612 MT |
1180 | c->phys_proc_id = 0; |
1181 | c->cpu_core_id = 0; | |
94605eff | 1182 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1183 | } |
1184 | ||
1185 | int __cpu_disable(void) | |
1186 | { | |
1187 | cpumask_t map = cpu_online_map; | |
1188 | int cpu = smp_processor_id(); | |
1189 | ||
1190 | /* | |
1191 | * Perhaps use cpufreq to drop frequency, but that could go | |
1192 | * into generic code. | |
1193 | * | |
1194 | * We won't take down the boot processor on i386 due to some | |
1195 | * interrupts only being able to be serviced by the BSP. | |
1196 | * Especially so if we're not using an IOAPIC -zwane | |
1197 | */ | |
1198 | if (cpu == 0) | |
1199 | return -EBUSY; | |
4038f901 SL |
1200 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1201 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1202 | clear_local_APIC(); |
f3705136 ZM |
1203 | /* Allow any queued timer interrupts to get serviced */ |
1204 | local_irq_enable(); | |
1205 | mdelay(1); | |
1206 | local_irq_disable(); | |
1207 | ||
e1367daf LS |
1208 | remove_siblinginfo(cpu); |
1209 | ||
f3705136 ZM |
1210 | cpu_clear(cpu, map); |
1211 | fixup_irqs(map); | |
1212 | /* It's now safe to remove this processor from the online map */ | |
1213 | cpu_clear(cpu, cpu_online_map); | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | void __cpu_die(unsigned int cpu) | |
1218 | { | |
1219 | /* We don't do anything here: idle task is faking death itself. */ | |
1220 | unsigned int i; | |
1221 | ||
1222 | for (i = 0; i < 10; i++) { | |
1223 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1224 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1225 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1226 | if (1 == num_online_cpus()) |
1227 | alternatives_smp_switch(0); | |
f3705136 | 1228 | return; |
e1367daf | 1229 | } |
aeb8397b | 1230 | msleep(100); |
1da177e4 | 1231 | } |
f3705136 ZM |
1232 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1233 | } | |
1234 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1235 | int __cpu_disable(void) | |
1236 | { | |
1237 | return -ENOSYS; | |
1238 | } | |
1da177e4 | 1239 | |
f3705136 ZM |
1240 | void __cpu_die(unsigned int cpu) |
1241 | { | |
1242 | /* We said "no" in __cpu_disable */ | |
1243 | BUG(); | |
1244 | } | |
1245 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1246 | ||
01a2f435 | 1247 | int __cpuinit native_cpu_up(unsigned int cpu) |
f3705136 | 1248 | { |
d04f41e3 | 1249 | unsigned long flags; |
34f361ad | 1250 | #ifdef CONFIG_HOTPLUG_CPU |
d04f41e3 | 1251 | int ret = 0; |
34f361ad AR |
1252 | |
1253 | /* | |
1254 | * We do warm boot only on cpus that had booted earlier | |
1255 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1256 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1257 | * when a cpu is taken offline from cpu_exit_clear(). | |
1258 | */ | |
1259 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1260 | ret = __smp_prepare_cpu(cpu); | |
1261 | ||
1262 | if (ret) | |
1263 | return -EIO; | |
1264 | #endif | |
1265 | ||
1da177e4 LT |
1266 | /* In case one didn't come up */ |
1267 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1268 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1269 | return -EIO; |
1270 | } | |
1271 | ||
e1367daf | 1272 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1273 | /* Unleash the CPU! */ |
1274 | cpu_set(cpu, smp_commenced_mask); | |
95492e46 IM |
1275 | |
1276 | /* | |
d04f41e3 IM |
1277 | * Check TSC synchronization with the AP (keep irqs disabled |
1278 | * while doing so): | |
95492e46 | 1279 | */ |
d04f41e3 | 1280 | local_irq_save(flags); |
95492e46 | 1281 | check_tsc_sync_source(cpu); |
d04f41e3 | 1282 | local_irq_restore(flags); |
95492e46 | 1283 | |
d04f41e3 | 1284 | while (!cpu_isset(cpu, cpu_online_map)) { |
18698917 | 1285 | cpu_relax(); |
d04f41e3 IM |
1286 | touch_nmi_watchdog(); |
1287 | } | |
b0d0a4ba | 1288 | |
1da177e4 LT |
1289 | return 0; |
1290 | } | |
1291 | ||
01a2f435 | 1292 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1da177e4 LT |
1293 | { |
1294 | #ifdef CONFIG_X86_IO_APIC | |
1295 | setup_ioapic_dest(); | |
1296 | #endif | |
1297 | zap_low_mappings(); | |
e1367daf | 1298 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1299 | /* |
1300 | * Disable executability of the SMP trampoline: | |
1301 | */ | |
1302 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1303 | #endif |
1da177e4 LT |
1304 | } |
1305 | ||
1306 | void __init smp_intr_init(void) | |
1307 | { | |
1308 | /* | |
1309 | * IRQ0 must be given a fixed assignment and initialized, | |
1310 | * because it's used before the IO-APIC is set up. | |
1311 | */ | |
1312 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1313 | ||
1314 | /* | |
1315 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1316 | * IPI, driven by wakeup. | |
1317 | */ | |
1318 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1319 | ||
1320 | /* IPI for invalidation */ | |
1321 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1322 | ||
1323 | /* IPI for generic function call */ | |
1324 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1325 | } | |
1a3f239d RR |
1326 | |
1327 | /* | |
1328 | * If the BIOS enumerates physical processors before logical, | |
1329 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1330 | */ | |
1331 | static int __init parse_maxcpus(char *arg) | |
1332 | { | |
1333 | extern unsigned int maxcpus; | |
1334 | ||
1335 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1336 | return 0; | |
1337 | } | |
1338 | early_param("maxcpus", parse_maxcpus); |