[deliverable/linux.git] / arch / x86 / kernel / suspend_64.c

/*
 * Suspend support specific for i386.
 *
 * Distribute under GPLv2
 *
 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
 */

#include <linux/smp.h>
#include <linux/suspend.h>
#include <asm/proto.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mtrr.h>

/* References to section boundaries */
extern const void __nosave_begin, __nosave_end;

struct saved_context saved_context;

/**
 *	__save_processor_state - save CPU registers before creating a
 *		hibernation image and before restoring the memory state from it
 *	@ctxt - structure to store the registers contents in
 *
 *	NOTE: If there is a CPU register the modification of which by the
 *	boot kernel (ie. the kernel used for loading the hibernation image)
 *	might affect the operations of the restored target kernel (ie. the one
 *	saved in the hibernation image), then its contents must be saved by this
 *	function.  In other words, if kernel A is hibernated and different
 *	kernel B is used for loading the hibernation image into memory, the
 *	kernel A's __save_processor_state() function must save all registers
 *	needed by kernel A, so that it can operate correctly after the resume
 *	regardless of what kernel B does in the meantime.
 */
void __save_processor_state(struct saved_context *ctxt)
{
	kernel_fpu_begin();

	/*
	 * descriptor tables
	 */
	store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
	store_idt((struct desc_ptr *)&ctxt->idt_limit);
	store_tr(ctxt->tr);

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/*
	 * segment registers
	 */
	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));

	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	mtrr_save_fixed_ranges(NULL);

	/*
	 * control registers 
	 */
	rdmsrl(MSR_EFER, ctxt->efer);
	ctxt->cr0 = read_cr0();
	ctxt->cr2 = read_cr2();
	ctxt->cr3 = read_cr3();
	ctxt->cr4 = read_cr4();
	ctxt->cr8 = read_cr8();
}

void save_processor_state(void)
{
	__save_processor_state(&saved_context);
}

static void do_fpu_end(void)
{
	/*
	 * Restore FPU regs if necessary
	 */
	kernel_fpu_end();
}

/**
 *	__restore_processor_state - restore the contents of CPU registers saved
 *		by __save_processor_state()
 *	@ctxt - structure to load the registers contents from
 */
void __restore_processor_state(struct saved_context *ctxt)
{
	/*
	 * control registers
	 */
	wrmsrl(MSR_EFER, ctxt->efer);
	write_cr8(ctxt->cr8);
	write_cr4(ctxt->cr4);
	write_cr3(ctxt->cr3);
	write_cr2(ctxt->cr2);
	write_cr0(ctxt->cr0);

	/*
	 * now restore the descriptor tables to their proper values
	 * ltr is done i fix_processor_context().
	 */
	load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
	load_idt((const struct desc_ptr *)&ctxt->idt_limit);


	/*
	 * segment registers
	 */
	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	load_gs_index(ctxt->gs);
	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));

	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);

	fix_processor_context();

	do_fpu_end();
	mtrr_ap_init();
}

void restore_processor_state(void)
{
	__restore_processor_state(&saved_context);
}

void fix_processor_context(void)
{
	int cpu = smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);

	set_tss_desc(cpu,t);	/* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */

	get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;

	syscall_init();                         /* This sets MSR_*STAR and related */
	load_TR_desc();				/* This does ltr */
	load_LDT(&current->active_mm->context);	/* This does lldt */

	/*
	 * Now maybe reload the debug registers
	 */
	if (current->thread.debugreg7){
                loaddebug(&current->thread, 0);
                loaddebug(&current->thread, 1);
                loaddebug(&current->thread, 2);
                loaddebug(&current->thread, 3);
                /* no 4 and 5 */
                loaddebug(&current->thread, 6);
                loaddebug(&current->thread, 7);
	}

}

#ifdef CONFIG_HIBERNATION
/* Defined in arch/x86_64/kernel/suspend_asm.S */
extern int restore_image(void);

/*
 * Address to jump to in the last phase of restore in order to get to the image
 * kernel's text (this value is passed in the image header).
 */
unsigned long restore_jump_address;

/*
 * Value of the cr3 register from before the hibernation (this value is passed
 * in the image header).
 */
unsigned long restore_cr3;

pgd_t *temp_level4_pgt;

void *relocated_restore_code;

static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
{
	long i, j;

	i = pud_index(address);
	pud = pud + i;
	for (; i < PTRS_PER_PUD; pud++, i++) {
		unsigned long paddr;
		pmd_t *pmd;

		paddr = address + i*PUD_SIZE;
		if (paddr >= end)
			break;

		pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
		if (!pmd)
			return -ENOMEM;
		set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
		for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
			unsigned long pe;

			if (paddr >= end)
				break;
			pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
			pe &= __supported_pte_mask;
			set_pmd(pmd, __pmd(pe));
		}
	}
	return 0;
}

static int set_up_temporary_mappings(void)
{
	unsigned long start, end, next;
	int error;

	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	if (!temp_level4_pgt)
		return -ENOMEM;

	/* It is safe to reuse the original kernel mapping */
	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
		init_level4_pgt[pgd_index(__START_KERNEL_map)]);

	/* Set up the direct mapping from scratch */
	start = (unsigned long)pfn_to_kaddr(0);
	end = (unsigned long)pfn_to_kaddr(end_pfn);

	for (; start < end; start = next) {
		pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
		if (!pud)
			return -ENOMEM;
		next = start + PGDIR_SIZE;
		if (next > end)
			next = end;
		if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
			return error;
		set_pgd(temp_level4_pgt + pgd_index(start),
			mk_kernel_pgd(__pa(pud)));
	}
	return 0;
}

int swsusp_arch_resume(void)
{
	int error;

	/* We have got enough memory and from now on we cannot recover */
	if ((error = set_up_temporary_mappings()))
		return error;

	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	if (!relocated_restore_code)
		return -ENOMEM;
	memcpy(relocated_restore_code, &core_restore_code,
	       &restore_registers - &core_restore_code);

	restore_image();
	return 0;
}

/*
 *	pfn_is_nosave - check if given pfn is in the 'nosave' section
 */

int pfn_is_nosave(unsigned long pfn)
{
	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
}

struct restore_data_record {
	unsigned long jump_address;
	unsigned long cr3;
	unsigned long magic;
};

#define RESTORE_MAGIC	0x0123456789ABCDEFUL

/**
 *	arch_hibernation_header_save - populate the architecture specific part
 *		of a hibernation image header
 *	@addr: address to save the data at
 */
int arch_hibernation_header_save(void *addr, unsigned int max_size)
{
	struct restore_data_record *rdr = addr;

	if (max_size < sizeof(struct restore_data_record))
		return -EOVERFLOW;
	rdr->jump_address = restore_jump_address;
	rdr->cr3 = restore_cr3;
	rdr->magic = RESTORE_MAGIC;
	return 0;
}

/**
 *	arch_hibernation_header_restore - read the architecture specific data
 *		from the hibernation image header
 *	@addr: address to read the data from
 */
int arch_hibernation_header_restore(void *addr)
{
	struct restore_data_record *rdr = addr;

	restore_jump_address = rdr->jump_address;
	restore_cr3 = rdr->cr3;
	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
}
#endif /* CONFIG_HIBERNATION */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Suspend support specific for i386.
	3	*
	4	* Distribute under GPLv2
	5	*
	6	* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
	7	* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
	8	*/
	9
55679edb	10	#include <linux/smp.h>
1da177e4	11	#include <linux/suspend.h>
1da177e4	12	#include <asm/proto.h>
3dd08325 RW	13	#include <asm/page.h>
3dd08325 RW	14	#include <asm/pgtable.h>
3ebad590	15	#include <asm/mtrr.h>
1da177e4	16
49c3df6a VG	17	/* References to section boundaries */
	18	extern const void __nosave_begin, __nosave_end;
	19
1da177e4 LT	20	struct saved_context saved_context;
1da177e4 LT	21
5c9c9bec RW	22	/**
	23	* __save_processor_state - save CPU registers before creating a
	24	* hibernation image and before restoring the memory state from it
	25	* @ctxt - structure to store the registers contents in
	26	*
	27	* NOTE: If there is a CPU register the modification of which by the
	28	* boot kernel (ie. the kernel used for loading the hibernation image)
	29	* might affect the operations of the restored target kernel (ie. the one
	30	* saved in the hibernation image), then its contents must be saved by this
	31	* function. In other words, if kernel A is hibernated and different
	32	* kernel B is used for loading the hibernation image into memory, the
	33	* kernel A's __save_processor_state() function must save all registers
	34	* needed by kernel A, so that it can operate correctly after the resume
	35	* regardless of what kernel B does in the meantime.
	36	*/
1da177e4 LT	37	void __save_processor_state(struct saved_context *ctxt)
	38	{
	39	kernel_fpu_begin();
	40
	41	/*
	42	* descriptor tables
	43	*/
9d1c6e7c GOC	44	store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
	45	store_idt((struct desc_ptr *)&ctxt->idt_limit);
	46	store_tr(ctxt->tr);
1da177e4 LT	47
1da177e4 LT	48	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4 LT	49	/*
	50	* segment registers
	51	*/
	52	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	53	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	54	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	55	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	56	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
	57
	58	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	59	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	60	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590	61	mtrr_save_fixed_ranges(NULL);
1da177e4 LT	62
	63	/*
	64	* control registers
	65	*/
3c321bce	66	rdmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	67	ctxt->cr0 = read_cr0();
	68	ctxt->cr2 = read_cr2();
	69	ctxt->cr3 = read_cr3();
	70	ctxt->cr4 = read_cr4();
	71	ctxt->cr8 = read_cr8();
1da177e4 LT	72	}
	73
	74	void save_processor_state(void)
	75	{
	76	__save_processor_state(&saved_context);
	77	}
	78
08967f94	79	static void do_fpu_end(void)
1da177e4	80	{
08967f94 SL	81	/*
	82	* Restore FPU regs if necessary
	83	*/
	84	kernel_fpu_end();
1da177e4 LT	85	}
1da177e4 LT	86
5c9c9bec RW	87	/**
	88	* __restore_processor_state - restore the contents of CPU registers saved
	89	* by __save_processor_state()
	90	* @ctxt - structure to load the registers contents from
	91	*/
1da177e4 LT	92	void __restore_processor_state(struct saved_context *ctxt)
	93	{
	94	/*
	95	* control registers
	96	*/
3c321bce	97	wrmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	98	write_cr8(ctxt->cr8);
	99	write_cr4(ctxt->cr4);
	100	write_cr3(ctxt->cr3);
	101	write_cr2(ctxt->cr2);
	102	write_cr0(ctxt->cr0);
1da177e4	103
8d783b3e PM	104	/*
	105	* now restore the descriptor tables to their proper values
	106	* ltr is done i fix_processor_context().
	107	*/
9d1c6e7c GOC	108	load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
	109	load_idt((const struct desc_ptr *)&ctxt->idt_limit);
	110
8d783b3e	111
1da177e4 LT	112	/*
	113	* segment registers
	114	*/
	115	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	116	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	117	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	118	load_gs_index(ctxt->gs);
	119	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
	120
	121	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	122	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	123	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	124
1da177e4 LT	125	fix_processor_context();
	126
	127	do_fpu_end();
3b520b23	128	mtrr_ap_init();
1da177e4 LT	129	}
	130
	131	void restore_processor_state(void)
	132	{
	133	__restore_processor_state(&saved_context);
	134	}
	135
	136	void fix_processor_context(void)
	137	{
	138	int cpu = smp_processor_id();
	139	struct tss_struct *t = &per_cpu(init_tss, cpu);
	140
3a4fa0a2	141	set_tss_desc(cpu,t); /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
1da177e4	142
f6dc247c	143	get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
1da177e4 LT	144
	145	syscall_init(); /* This sets MSR_STAR and related /
	146	load_TR_desc(); /* This does ltr */
	147	load_LDT(&current->active_mm->context); /* This does lldt */
	148
	149	/*
	150	* Now maybe reload the debug registers
	151	*/
	152	if (current->thread.debugreg7){
	153	loaddebug(&current->thread, 0);
	154	loaddebug(&current->thread, 1);
	155	loaddebug(&current->thread, 2);
	156	loaddebug(&current->thread, 3);
	157	/* no 4 and 5 */
	158	loaddebug(&current->thread, 6);
	159	loaddebug(&current->thread, 7);
	160	}
	161
	162	}
	163
b0cb1a19	164	#ifdef CONFIG_HIBERNATION
3dd08325 RW	165	/* Defined in arch/x86_64/kernel/suspend_asm.S */
3dd08325 RW	166	extern int restore_image(void);
1da177e4	167
d158cbdf RW	168	/*
	169	* Address to jump to in the last phase of restore in order to get to the image
	170	* kernel's text (this value is passed in the image header).
	171	*/
	172	unsigned long restore_jump_address;
	173
c30bb68c RW	174	/*
	175	* Value of the cr3 register from before the hibernation (this value is passed
	176	* in the image header).
	177	*/
	178	unsigned long restore_cr3;
	179
3dd08325 RW	180	pgd_t *temp_level4_pgt;
3dd08325 RW	181
d158cbdf RW	182	void *relocated_restore_code;
d158cbdf RW	183
2c1b4a5c	184	static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
3dd08325 RW	185	{
	186	long i, j;
	187
	188	i = pud_index(address);
	189	pud = pud + i;
	190	for (; i < PTRS_PER_PUD; pud++, i++) {
	191	unsigned long paddr;
	192	pmd_t *pmd;
	193
	194	paddr = address + i*PUD_SIZE;
	195	if (paddr >= end)
	196	break;
	197
2c1b4a5c RW	198	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	199	if (!pmd)
	200	return -ENOMEM;
3dd08325 RW	201	set_pud(pud, __pud(__pa(pmd) \| _KERNPG_TABLE));
	202	for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
	203	unsigned long pe;
	204
	205	if (paddr >= end)
	206	break;
d158cbdf	207	pe = __PAGE_KERNEL_LARGE_EXEC \| paddr;
3dd08325 RW	208	pe &= __supported_pte_mask;
	209	set_pmd(pmd, __pmd(pe));
	210	}
	211	}
2c1b4a5c	212	return 0;
3dd08325 RW	213	}
3dd08325 RW	214
2c1b4a5c	215	static int set_up_temporary_mappings(void)
3dd08325 RW	216	{
3dd08325 RW	217	unsigned long start, end, next;
2c1b4a5c	218	int error;
3dd08325	219
2c1b4a5c RW	220	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	221	if (!temp_level4_pgt)
	222	return -ENOMEM;
3dd08325	223
5867a78f AM	224	/* It is safe to reuse the original kernel mapping */
	225	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
	226	init_level4_pgt[pgd_index(__START_KERNEL_map)]);
	227
3dd08325 RW	228	/* Set up the direct mapping from scratch */
	229	start = (unsigned long)pfn_to_kaddr(0);
	230	end = (unsigned long)pfn_to_kaddr(end_pfn);
	231
	232	for (; start < end; start = next) {
5867a78f	233	pud_t pud = (pud_t )get_safe_page(GFP_ATOMIC);
2c1b4a5c RW	234	if (!pud)
2c1b4a5c RW	235	return -ENOMEM;
3dd08325 RW	236	next = start + PGDIR_SIZE;
	237	if (next > end)
	238	next = end;
2c1b4a5c RW	239	if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
2c1b4a5c RW	240	return error;
3dd08325 RW	241	set_pgd(temp_level4_pgt + pgd_index(start),
	242	mk_kernel_pgd(__pa(pud)));
	243	}
5867a78f	244	return 0;
3dd08325 RW	245	}
	246
	247	int swsusp_arch_resume(void)
	248	{
2c1b4a5c	249	int error;
3dd08325	250
3dd08325	251	/* We have got enough memory and from now on we cannot recover */
2c1b4a5c RW	252	if ((error = set_up_temporary_mappings()))
2c1b4a5c RW	253	return error;
d158cbdf RW	254
	255	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	256	if (!relocated_restore_code)
	257	return -ENOMEM;
	258	memcpy(relocated_restore_code, &core_restore_code,
	259	&restore_registers - &core_restore_code);
	260
3dd08325 RW	261	restore_image();
	262	return 0;
	263	}
49c3df6a VG	264
	265	/*
	266	* pfn_is_nosave - check if given pfn is in the 'nosave' section
	267	*/
	268
	269	int pfn_is_nosave(unsigned long pfn)
	270	{
	271	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	272	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	273	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
	274	}
d158cbdf RW	275
	276	struct restore_data_record {
	277	unsigned long jump_address;
c30bb68c RW	278	unsigned long cr3;
c30bb68c RW	279	unsigned long magic;
d158cbdf RW	280	};
	281
	282	#define RESTORE_MAGIC 0x0123456789ABCDEFUL
	283
	284	/**
	285	* arch_hibernation_header_save - populate the architecture specific part
	286	* of a hibernation image header
	287	* @addr: address to save the data at
	288	*/
	289	int arch_hibernation_header_save(void *addr, unsigned int max_size)
	290	{
	291	struct restore_data_record *rdr = addr;
	292
	293	if (max_size < sizeof(struct restore_data_record))
	294	return -EOVERFLOW;
	295	rdr->jump_address = restore_jump_address;
c30bb68c RW	296	rdr->cr3 = restore_cr3;
c30bb68c RW	297	rdr->magic = RESTORE_MAGIC;
d158cbdf RW	298	return 0;
	299	}
	300
	301	/**
	302	* arch_hibernation_header_restore - read the architecture specific data
	303	* from the hibernation image header
	304	* @addr: address to read the data from
	305	*/
	306	int arch_hibernation_header_restore(void *addr)
	307	{
	308	struct restore_data_record *rdr = addr;
	309
	310	restore_jump_address = rdr->jump_address;
c30bb68c RW	311	restore_cr3 = rdr->cr3;
c30bb68c RW	312	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
d158cbdf	313	}
b0cb1a19	314	#endif /* CONFIG_HIBERNATION */