Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
b5964405 IM |
24 | #include <linux/module.h> |
25 | #include <linux/ptrace.h> | |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
1da177e4 | 32 | #include <linux/timer.h> |
1da177e4 | 33 | #include <linux/init.h> |
91768d6c | 34 | #include <linux/bug.h> |
b5964405 IM |
35 | #include <linux/nmi.h> |
36 | #include <linux/mm.h> | |
c1d518c8 AH |
37 | #include <linux/smp.h> |
38 | #include <linux/io.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_EISA | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/eisa.h> | |
43 | #endif | |
44 | ||
c0d12172 DJ |
45 | #if defined(CONFIG_EDAC) |
46 | #include <linux/edac.h> | |
47 | #endif | |
48 | ||
f8561296 | 49 | #include <asm/kmemcheck.h> |
b5964405 | 50 | #include <asm/stacktrace.h> |
1da177e4 | 51 | #include <asm/processor.h> |
1da177e4 | 52 | #include <asm/debugreg.h> |
60063497 | 53 | #include <linux/atomic.h> |
35de5b06 | 54 | #include <asm/text-patching.h> |
08d636b6 | 55 | #include <asm/ftrace.h> |
c1d518c8 | 56 | #include <asm/traps.h> |
1da177e4 | 57 | #include <asm/desc.h> |
78f7f1e5 | 58 | #include <asm/fpu/internal.h> |
9e55e44e | 59 | #include <asm/mce.h> |
4eefbe79 | 60 | #include <asm/fixmap.h> |
1164dd00 | 61 | #include <asm/mach_traps.h> |
17f41571 | 62 | #include <asm/alternative.h> |
a84eeaa9 | 63 | #include <asm/fpu/xstate.h> |
e7126cf5 | 64 | #include <asm/trace/mpx.h> |
fe3d197f | 65 | #include <asm/mpx.h> |
ba3e127e | 66 | #include <asm/vm86.h> |
c1d518c8 | 67 | |
081f75bb | 68 | #ifdef CONFIG_X86_64 |
428cf902 | 69 | #include <asm/x86_init.h> |
081f75bb AH |
70 | #include <asm/pgalloc.h> |
71 | #include <asm/proto.h> | |
4df05f36 KC |
72 | |
73 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
74 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 75 | #else |
c1d518c8 | 76 | #include <asm/processor-flags.h> |
8e6dafd6 | 77 | #include <asm/setup.h> |
b2502b41 | 78 | #include <asm/proto.h> |
081f75bb | 79 | #endif |
1da177e4 | 80 | |
4df05f36 KC |
81 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
82 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
83 | ||
b77b881f YL |
84 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
85 | EXPORT_SYMBOL_GPL(used_vectors); | |
86 | ||
d99e1bd1 | 87 | static inline void cond_local_irq_enable(struct pt_regs *regs) |
762db434 AH |
88 | { |
89 | if (regs->flags & X86_EFLAGS_IF) | |
90 | local_irq_enable(); | |
91 | } | |
92 | ||
d99e1bd1 | 93 | static inline void cond_local_irq_disable(struct pt_regs *regs) |
3d2a71a5 AH |
94 | { |
95 | if (regs->flags & X86_EFLAGS_IF) | |
96 | local_irq_disable(); | |
3d2a71a5 AH |
97 | } |
98 | ||
aaee8c3c AL |
99 | /* |
100 | * In IST context, we explicitly disable preemption. This serves two | |
101 | * purposes: it makes it much less likely that we would accidentally | |
102 | * schedule in IST context and it will force a warning if we somehow | |
103 | * manage to schedule by accident. | |
104 | */ | |
8c84014f | 105 | void ist_enter(struct pt_regs *regs) |
95927475 | 106 | { |
f39b6f0e | 107 | if (user_mode(regs)) { |
5778077d | 108 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
95927475 AL |
109 | } else { |
110 | /* | |
111 | * We might have interrupted pretty much anything. In | |
112 | * fact, if we're a machine check, we can even interrupt | |
113 | * NMI processing. We don't want in_nmi() to return true, | |
114 | * but we need to notify RCU. | |
115 | */ | |
116 | rcu_nmi_enter(); | |
95927475 | 117 | } |
b926e6f6 | 118 | |
aaee8c3c | 119 | preempt_disable(); |
b926e6f6 AL |
120 | |
121 | /* This code is a bit fragile. Test it. */ | |
f78f5b90 | 122 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work"); |
95927475 AL |
123 | } |
124 | ||
8c84014f | 125 | void ist_exit(struct pt_regs *regs) |
95927475 | 126 | { |
aaee8c3c | 127 | preempt_enable_no_resched(); |
95927475 | 128 | |
8c84014f | 129 | if (!user_mode(regs)) |
95927475 AL |
130 | rcu_nmi_exit(); |
131 | } | |
132 | ||
bced35b6 AL |
133 | /** |
134 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
135 | * @regs: regs passed to the IST exception handler | |
136 | * | |
137 | * IST exception handlers normally cannot schedule. As a special | |
138 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 139 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
140 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
141 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
142 | * Callers are responsible for enabling interrupts themselves inside | |
8c84014f | 143 | * the non-atomic section, and callers must call ist_end_non_atomic() |
bced35b6 AL |
144 | * before ist_exit(). |
145 | */ | |
146 | void ist_begin_non_atomic(struct pt_regs *regs) | |
147 | { | |
f39b6f0e | 148 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
149 | |
150 | /* | |
151 | * Sanity check: we need to be on the normal thread stack. This | |
152 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
153 | * from double_fault. | |
154 | */ | |
a7fcf28d AL |
155 | BUG_ON((unsigned long)(current_top_of_stack() - |
156 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 | 157 | |
aaee8c3c | 158 | preempt_enable_no_resched(); |
bced35b6 AL |
159 | } |
160 | ||
161 | /** | |
162 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
163 | * | |
164 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
165 | */ | |
166 | void ist_end_non_atomic(void) | |
167 | { | |
aaee8c3c | 168 | preempt_disable(); |
bced35b6 AL |
169 | } |
170 | ||
9326638c | 171 | static nokprobe_inline int |
c416ddf5 FW |
172 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
173 | struct pt_regs *regs, long error_code) | |
1da177e4 | 174 | { |
d74ef111 | 175 | if (v8086_mode(regs)) { |
3c1326f8 | 176 | /* |
c416ddf5 | 177 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
178 | * On nmi (interrupt 2), do_trap should not be called. |
179 | */ | |
c416ddf5 FW |
180 | if (trapnr < X86_TRAP_UD) { |
181 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
182 | error_code, trapnr)) | |
183 | return 0; | |
184 | } | |
185 | return -1; | |
1da177e4 | 186 | } |
d74ef111 | 187 | |
55474c48 | 188 | if (!user_mode(regs)) { |
548acf19 | 189 | if (!fixup_exception(regs, trapnr)) { |
c416ddf5 FW |
190 | tsk->thread.error_code = error_code; |
191 | tsk->thread.trap_nr = trapnr; | |
192 | die(str, regs, error_code); | |
193 | } | |
194 | return 0; | |
195 | } | |
1da177e4 | 196 | |
c416ddf5 FW |
197 | return -1; |
198 | } | |
1da177e4 | 199 | |
1c326c4d ON |
200 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
201 | siginfo_t *info) | |
958d3d72 ON |
202 | { |
203 | unsigned long siaddr; | |
204 | int sicode; | |
205 | ||
206 | switch (trapnr) { | |
1c326c4d ON |
207 | default: |
208 | return SEND_SIG_PRIV; | |
209 | ||
958d3d72 ON |
210 | case X86_TRAP_DE: |
211 | sicode = FPE_INTDIV; | |
b02ef20a | 212 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
213 | break; |
214 | case X86_TRAP_UD: | |
215 | sicode = ILL_ILLOPN; | |
b02ef20a | 216 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
217 | break; |
218 | case X86_TRAP_AC: | |
219 | sicode = BUS_ADRALN; | |
220 | siaddr = 0; | |
221 | break; | |
222 | } | |
223 | ||
224 | info->si_signo = signr; | |
225 | info->si_errno = 0; | |
226 | info->si_code = sicode; | |
227 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 228 | return info; |
958d3d72 ON |
229 | } |
230 | ||
9326638c | 231 | static void |
c416ddf5 FW |
232 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
233 | long error_code, siginfo_t *info) | |
234 | { | |
235 | struct task_struct *tsk = current; | |
236 | ||
237 | ||
238 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
239 | return; | |
b5964405 | 240 | /* |
51e7dc70 | 241 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
242 | * kernelspace faults which result in die(), but not |
243 | * kernelspace faults which are fixed up. die() gives the | |
244 | * process no chance to handle the signal and notice the | |
245 | * kernel fault information, so that won't result in polluting | |
246 | * the information about previously queued, but not yet | |
247 | * delivered, faults. See also do_general_protection below. | |
248 | */ | |
249 | tsk->thread.error_code = error_code; | |
51e7dc70 | 250 | tsk->thread.trap_nr = trapnr; |
d1895183 | 251 | |
081f75bb AH |
252 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && |
253 | printk_ratelimit()) { | |
c767a54b JP |
254 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
255 | tsk->comm, tsk->pid, str, | |
256 | regs->ip, regs->sp, error_code); | |
081f75bb | 257 | print_vma_addr(" in ", regs->ip); |
c767a54b | 258 | pr_cont("\n"); |
081f75bb | 259 | } |
081f75bb | 260 | |
38cad57b | 261 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 262 | } |
9326638c | 263 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 264 | |
dff0796e | 265 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 266 | unsigned long trapnr, int signr) |
dff0796e | 267 | { |
1c326c4d | 268 | siginfo_t info; |
dff0796e | 269 | |
5778077d | 270 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
02fdcd5e | 271 | |
dff0796e ON |
272 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != |
273 | NOTIFY_STOP) { | |
d99e1bd1 | 274 | cond_local_irq_enable(regs); |
1c326c4d ON |
275 | do_trap(trapnr, signr, str, regs, error_code, |
276 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e | 277 | } |
dff0796e ON |
278 | } |
279 | ||
b5964405 | 280 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 281 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 282 | { \ |
1c326c4d | 283 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
284 | } |
285 | ||
0eb14833 ON |
286 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
287 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
288 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
289 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
290 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
291 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 292 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 293 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 294 | |
081f75bb AH |
295 | #ifdef CONFIG_X86_64 |
296 | /* Runs on IST stack */ | |
081f75bb AH |
297 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
298 | { | |
299 | static const char str[] = "double fault"; | |
300 | struct task_struct *tsk = current; | |
301 | ||
af726f21 AL |
302 | #ifdef CONFIG_X86_ESPFIX64 |
303 | extern unsigned char native_irq_return_iret[]; | |
304 | ||
305 | /* | |
306 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
307 | * end up promoting it to a doublefault. In that case, modify | |
308 | * the stack to make it look like we just entered the #GP | |
309 | * handler from user space, similar to bad_iret. | |
95927475 AL |
310 | * |
311 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
312 | */ |
313 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
314 | regs->cs == __KERNEL_CS && | |
315 | regs->ip == (unsigned long)native_irq_return_iret) | |
316 | { | |
317 | struct pt_regs *normal_regs = task_pt_regs(current); | |
318 | ||
319 | /* Fake a #GP(0) from userspace. */ | |
320 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
321 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
322 | regs->ip = (unsigned long)general_protection; | |
323 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 324 | |
af726f21 AL |
325 | return; |
326 | } | |
327 | #endif | |
328 | ||
8c84014f | 329 | ist_enter(regs); |
c9408265 | 330 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
331 | |
332 | tsk->thread.error_code = error_code; | |
51e7dc70 | 333 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 334 | |
4d067d8e BP |
335 | #ifdef CONFIG_DOUBLEFAULT |
336 | df_debug(regs, error_code); | |
337 | #endif | |
bd8b96df IM |
338 | /* |
339 | * This is always a kernel trap and never fixable (and thus must | |
340 | * never return). | |
341 | */ | |
081f75bb AH |
342 | for (;;) |
343 | die(str, regs, error_code); | |
344 | } | |
345 | #endif | |
346 | ||
fe3d197f DH |
347 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
348 | { | |
1126cb45 | 349 | const struct mpx_bndcsr *bndcsr; |
fe3d197f DH |
350 | siginfo_t *info; |
351 | ||
5778077d | 352 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
fe3d197f DH |
353 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, |
354 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
8c84014f | 355 | return; |
d99e1bd1 | 356 | cond_local_irq_enable(regs); |
fe3d197f | 357 | |
f39b6f0e | 358 | if (!user_mode(regs)) |
fe3d197f DH |
359 | die("bounds", regs, error_code); |
360 | ||
361 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
362 | /* The exception is not from Intel MPX */ | |
363 | goto exit_trap; | |
364 | } | |
365 | ||
366 | /* | |
367 | * We need to look at BNDSTATUS to resolve this exception. | |
a84eeaa9 DH |
368 | * A NULL here might mean that it is in its 'init state', |
369 | * which is all zeros which indicates MPX was not | |
370 | * responsible for the exception. | |
fe3d197f | 371 | */ |
d91cab78 | 372 | bndcsr = get_xsave_field_ptr(XFEATURE_MASK_BNDCSR); |
fe3d197f DH |
373 | if (!bndcsr) |
374 | goto exit_trap; | |
375 | ||
e7126cf5 | 376 | trace_bounds_exception_mpx(bndcsr); |
fe3d197f DH |
377 | /* |
378 | * The error code field of the BNDSTATUS register communicates status | |
379 | * information of a bound range exception #BR or operation involving | |
380 | * bound directory. | |
381 | */ | |
382 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
383 | case 2: /* Bound directory has invalid entry. */ | |
46a6e0cf | 384 | if (mpx_handle_bd_fault()) |
fe3d197f DH |
385 | goto exit_trap; |
386 | break; /* Success, it was handled */ | |
387 | case 1: /* Bound violation. */ | |
46a6e0cf | 388 | info = mpx_generate_siginfo(regs); |
e10abb2f | 389 | if (IS_ERR(info)) { |
fe3d197f DH |
390 | /* |
391 | * We failed to decode the MPX instruction. Act as if | |
392 | * the exception was not caused by MPX. | |
393 | */ | |
394 | goto exit_trap; | |
395 | } | |
396 | /* | |
397 | * Success, we decoded the instruction and retrieved | |
398 | * an 'info' containing the address being accessed | |
399 | * which caused the exception. This information | |
400 | * allows and application to possibly handle the | |
401 | * #BR exception itself. | |
402 | */ | |
403 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
404 | kfree(info); | |
405 | break; | |
406 | case 0: /* No exception caused by Intel MPX operations. */ | |
407 | goto exit_trap; | |
408 | default: | |
409 | die("bounds", regs, error_code); | |
410 | } | |
411 | ||
fe3d197f | 412 | return; |
8c84014f | 413 | |
fe3d197f DH |
414 | exit_trap: |
415 | /* | |
416 | * This path out is for all the cases where we could not | |
417 | * handle the exception in some way (like allocating a | |
418 | * table or telling userspace about it. We will also end | |
419 | * up here if the kernel has MPX turned off at compile | |
420 | * time.. | |
421 | */ | |
422 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
fe3d197f DH |
423 | } |
424 | ||
9326638c | 425 | dotraplinkage void |
13485ab5 | 426 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 427 | { |
13485ab5 | 428 | struct task_struct *tsk; |
b5964405 | 429 | |
5778077d | 430 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
d99e1bd1 | 431 | cond_local_irq_enable(regs); |
c6df0d71 | 432 | |
d74ef111 | 433 | if (v8086_mode(regs)) { |
ef3f6288 FW |
434 | local_irq_enable(); |
435 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
8c84014f | 436 | return; |
ef3f6288 | 437 | } |
1da177e4 | 438 | |
13485ab5 | 439 | tsk = current; |
55474c48 | 440 | if (!user_mode(regs)) { |
548acf19 | 441 | if (fixup_exception(regs, X86_TRAP_GP)) |
8c84014f | 442 | return; |
ef3f6288 FW |
443 | |
444 | tsk->thread.error_code = error_code; | |
445 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
446 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
447 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 448 | die("general protection fault", regs, error_code); |
8c84014f | 449 | return; |
ef3f6288 | 450 | } |
1da177e4 | 451 | |
13485ab5 | 452 | tsk->thread.error_code = error_code; |
51e7dc70 | 453 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 454 | |
13485ab5 AH |
455 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
456 | printk_ratelimit()) { | |
c767a54b | 457 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
458 | tsk->comm, task_pid_nr(tsk), |
459 | regs->ip, regs->sp, error_code); | |
03252919 | 460 | print_vma_addr(" in ", regs->ip); |
c767a54b | 461 | pr_cont("\n"); |
03252919 | 462 | } |
abd4f750 | 463 | |
38cad57b | 464 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
1da177e4 | 465 | } |
9326638c | 466 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 467 | |
c1d518c8 | 468 | /* May run on IST stack. */ |
9326638c | 469 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 470 | { |
08d636b6 | 471 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
472 | /* |
473 | * ftrace must be first, everything else may cause a recursive crash. | |
474 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
475 | */ | |
476 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
477 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
478 | return; |
479 | #endif | |
17f41571 JK |
480 | if (poke_int3_handler(regs)) |
481 | return; | |
482 | ||
8c84014f | 483 | ist_enter(regs); |
5778077d | 484 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f503b5ae | 485 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
486 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
487 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 488 | goto exit; |
f503b5ae | 489 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 490 | |
6f6343f5 MH |
491 | #ifdef CONFIG_KPROBES |
492 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 493 | goto exit; |
6f6343f5 MH |
494 | #endif |
495 | ||
c9408265 KC |
496 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
497 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 498 | goto exit; |
b5964405 | 499 | |
42181186 SR |
500 | /* |
501 | * Let others (NMI) know that the debug stack is in use | |
502 | * as we may switch to the interrupt stack. | |
503 | */ | |
504 | debug_stack_usage_inc(); | |
d99e1bd1 AK |
505 | preempt_disable(); |
506 | cond_local_irq_enable(regs); | |
c9408265 | 507 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
d99e1bd1 AK |
508 | cond_local_irq_disable(regs); |
509 | preempt_enable_no_resched(); | |
42181186 | 510 | debug_stack_usage_dec(); |
6ba3c97a | 511 | exit: |
8c84014f | 512 | ist_exit(regs); |
1da177e4 | 513 | } |
9326638c | 514 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 515 | |
081f75bb | 516 | #ifdef CONFIG_X86_64 |
bd8b96df | 517 | /* |
48e08d0f AL |
518 | * Help handler running on IST stack to switch off the IST stack if the |
519 | * interrupted code was in user mode. The actual stack switch is done in | |
520 | * entry_64.S | |
bd8b96df | 521 | */ |
7ddc6a21 | 522 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 523 | { |
48e08d0f AL |
524 | struct pt_regs *regs = task_pt_regs(current); |
525 | *regs = *eregs; | |
081f75bb AH |
526 | return regs; |
527 | } | |
9326638c | 528 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
529 | |
530 | struct bad_iret_stack { | |
531 | void *error_entry_ret; | |
532 | struct pt_regs regs; | |
533 | }; | |
534 | ||
7ddc6a21 | 535 | asmlinkage __visible notrace |
b645af2d AL |
536 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
537 | { | |
538 | /* | |
539 | * This is called from entry_64.S early in handling a fault | |
540 | * caused by a bad iret to user mode. To handle the fault | |
541 | * correctly, we want move our stack frame to task_pt_regs | |
542 | * and we want to pretend that the exception came from the | |
543 | * iret target. | |
544 | */ | |
545 | struct bad_iret_stack *new_stack = | |
546 | container_of(task_pt_regs(current), | |
547 | struct bad_iret_stack, regs); | |
548 | ||
549 | /* Copy the IRET target to the new stack. */ | |
550 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
551 | ||
552 | /* Copy the remainder of the stack from the current stack. */ | |
553 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
554 | ||
f39b6f0e | 555 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
556 | return new_stack; |
557 | } | |
7ddc6a21 | 558 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
559 | #endif |
560 | ||
f2b37575 AL |
561 | static bool is_sysenter_singlestep(struct pt_regs *regs) |
562 | { | |
563 | /* | |
564 | * We don't try for precision here. If we're anywhere in the region of | |
565 | * code that can be single-stepped in the SYSENTER entry path, then | |
566 | * assume that this is a useless single-step trap due to SYSENTER | |
567 | * being invoked with TF set. (We don't know in advance exactly | |
568 | * which instructions will be hit because BTF could plausibly | |
569 | * be set.) | |
570 | */ | |
571 | #ifdef CONFIG_X86_32 | |
572 | return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < | |
573 | (unsigned long)__end_SYSENTER_singlestep_region - | |
574 | (unsigned long)__begin_SYSENTER_singlestep_region; | |
575 | #elif defined(CONFIG_IA32_EMULATION) | |
576 | return (regs->ip - (unsigned long)entry_SYSENTER_compat) < | |
577 | (unsigned long)__end_entry_SYSENTER_compat - | |
578 | (unsigned long)entry_SYSENTER_compat; | |
579 | #else | |
580 | return false; | |
581 | #endif | |
582 | } | |
583 | ||
1da177e4 LT |
584 | /* |
585 | * Our handling of the processor debug registers is non-trivial. | |
586 | * We do not clear them on entry and exit from the kernel. Therefore | |
587 | * it is possible to get a watchpoint trap here from inside the kernel. | |
588 | * However, the code in ./ptrace.c has ensured that the user can | |
589 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
590 | * watchpoint trap can only occur in code which is reading/writing | |
591 | * from user space. Such code must not hold kernel locks (since it | |
592 | * can equally take a page fault), therefore it is safe to call | |
593 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 594 | * |
1da177e4 LT |
595 | * Code in ./signal.c ensures that the debug control register |
596 | * is restored before we deliver any signal, and therefore that | |
597 | * user code runs with the correct debug control register even though | |
598 | * we clear it here. | |
599 | * | |
600 | * Being careful here means that we don't have to be as careful in a | |
601 | * lot of more complicated places (task switching can be a bit lazy | |
602 | * about restoring all the debug state, and ptrace doesn't have to | |
603 | * find every occurrence of the TF bit that could be saved away even | |
604 | * by user code) | |
c1d518c8 AH |
605 | * |
606 | * May run on IST stack. | |
1da177e4 | 607 | */ |
9326638c | 608 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 609 | { |
1da177e4 | 610 | struct task_struct *tsk = current; |
a1e80faf | 611 | int user_icebp = 0; |
08d68323 | 612 | unsigned long dr6; |
da654b74 | 613 | int si_code; |
1da177e4 | 614 | |
8c84014f | 615 | ist_enter(regs); |
4cdf77a8 | 616 | |
08d68323 | 617 | get_debugreg(dr6, 6); |
8bb56436 AL |
618 | /* |
619 | * The Intel SDM says: | |
620 | * | |
621 | * Certain debug exceptions may clear bits 0-3. The remaining | |
622 | * contents of the DR6 register are never cleared by the | |
623 | * processor. To avoid confusion in identifying debug | |
624 | * exceptions, debug handlers should clear the register before | |
625 | * returning to the interrupted task. | |
626 | * | |
627 | * Keep it simple: clear DR6 immediately. | |
628 | */ | |
629 | set_debugreg(0, 6); | |
1da177e4 | 630 | |
40f9249a P |
631 | /* Filter out all the reserved bits which are preset to 1 */ |
632 | dr6 &= ~DR6_RESERVED; | |
633 | ||
81edd9f6 AL |
634 | /* |
635 | * The SDM says "The processor clears the BTF flag when it | |
636 | * generates a debug exception." Clear TIF_BLOCKSTEP to keep | |
637 | * TIF_BLOCKSTEP in sync with the hardware BTF flag. | |
638 | */ | |
639 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
640 | ||
f2b37575 AL |
641 | if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) && |
642 | is_sysenter_singlestep(regs))) { | |
643 | dr6 &= ~DR_STEP; | |
644 | if (!dr6) | |
645 | goto exit; | |
646 | /* | |
647 | * else we might have gotten a single-step trap and hit a | |
648 | * watchpoint at the same time, in which case we should fall | |
649 | * through and handle the watchpoint. | |
650 | */ | |
651 | } | |
652 | ||
a1e80faf FW |
653 | /* |
654 | * If dr6 has no reason to give us about the origin of this trap, | |
655 | * then it's very likely the result of an icebp/int01 trap. | |
656 | * User wants a sigtrap for that. | |
657 | */ | |
f39b6f0e | 658 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
659 | user_icebp = 1; |
660 | ||
f2b37575 | 661 | /* Catch kmemcheck conditions! */ |
eadb8a09 | 662 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 663 | goto exit; |
f8561296 | 664 | |
08d68323 P |
665 | /* Store the virtualized DR6 value */ |
666 | tsk->thread.debugreg6 = dr6; | |
667 | ||
6f6343f5 MH |
668 | #ifdef CONFIG_KPROBES |
669 | if (kprobe_debug_handler(regs)) | |
670 | goto exit; | |
671 | #endif | |
672 | ||
5a802e15 | 673 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 674 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 675 | goto exit; |
3d2a71a5 | 676 | |
42181186 SR |
677 | /* |
678 | * Let others (NMI) know that the debug stack is in use | |
679 | * as we may switch to the interrupt stack. | |
680 | */ | |
681 | debug_stack_usage_inc(); | |
682 | ||
1da177e4 | 683 | /* It's safe to allow irq's after DR6 has been saved */ |
d99e1bd1 AK |
684 | preempt_disable(); |
685 | cond_local_irq_enable(regs); | |
1da177e4 | 686 | |
d74ef111 | 687 | if (v8086_mode(regs)) { |
c9408265 KC |
688 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
689 | X86_TRAP_DB); | |
d99e1bd1 AK |
690 | cond_local_irq_disable(regs); |
691 | preempt_enable_no_resched(); | |
42181186 | 692 | debug_stack_usage_dec(); |
6ba3c97a | 693 | goto exit; |
1da177e4 LT |
694 | } |
695 | ||
f2b37575 AL |
696 | if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) { |
697 | /* | |
698 | * Historical junk that used to handle SYSENTER single-stepping. | |
699 | * This should be unreachable now. If we survive for a while | |
700 | * without anyone hitting this warning, we'll turn this into | |
701 | * an oops. | |
702 | */ | |
08d68323 P |
703 | tsk->thread.debugreg6 &= ~DR_STEP; |
704 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
705 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 706 | } |
08d68323 | 707 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 708 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 709 | send_sigtrap(tsk, regs, error_code, si_code); |
d99e1bd1 AK |
710 | cond_local_irq_disable(regs); |
711 | preempt_enable_no_resched(); | |
42181186 | 712 | debug_stack_usage_dec(); |
1da177e4 | 713 | |
6ba3c97a | 714 | exit: |
2a41aa4f AL |
715 | #if defined(CONFIG_X86_32) |
716 | /* | |
717 | * This is the most likely code path that involves non-trivial use | |
718 | * of the SYSENTER stack. Check that we haven't overrun it. | |
719 | */ | |
720 | WARN(this_cpu_read(cpu_tss.SYSENTER_stack_canary) != STACK_END_MAGIC, | |
721 | "Overran or corrupted SYSENTER stack\n"); | |
722 | #endif | |
8c84014f | 723 | ist_exit(regs); |
1da177e4 | 724 | } |
9326638c | 725 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
726 | |
727 | /* | |
728 | * Note that we play around with the 'TS' bit in an attempt to get | |
729 | * the correct behaviour even in the presence of the asynchronous | |
730 | * IRQ13 behaviour | |
731 | */ | |
5e1b05be | 732 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 733 | { |
e2e75c91 | 734 | struct task_struct *task = current; |
e1cebad4 | 735 | struct fpu *fpu = &task->thread.fpu; |
1da177e4 | 736 | siginfo_t info; |
c9408265 KC |
737 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
738 | "simd exception"; | |
e2e75c91 BG |
739 | |
740 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
741 | return; | |
d99e1bd1 | 742 | cond_local_irq_enable(regs); |
e2e75c91 | 743 | |
e1cebad4 | 744 | if (!user_mode(regs)) { |
548acf19 | 745 | if (!fixup_exception(regs, trapnr)) { |
e2e75c91 | 746 | task->thread.error_code = error_code; |
51e7dc70 | 747 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
748 | die(str, regs, error_code); |
749 | } | |
750 | return; | |
751 | } | |
1da177e4 LT |
752 | |
753 | /* | |
754 | * Save the info for the exception handler and clear the error. | |
755 | */ | |
e1cebad4 IM |
756 | fpu__save(fpu); |
757 | ||
758 | task->thread.trap_nr = trapnr; | |
9b6dba9e | 759 | task->thread.error_code = error_code; |
e1cebad4 IM |
760 | info.si_signo = SIGFPE; |
761 | info.si_errno = 0; | |
762 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); | |
adf77bac | 763 | |
e1cebad4 | 764 | info.si_code = fpu__exception_code(fpu, trapnr); |
adf77bac | 765 | |
e1cebad4 IM |
766 | /* Retry when we get spurious exceptions: */ |
767 | if (!info.si_code) | |
c9408265 | 768 | return; |
e1cebad4 | 769 | |
1da177e4 LT |
770 | force_sig_info(SIGFPE, &info, task); |
771 | } | |
772 | ||
e407d620 | 773 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 774 | { |
5778077d | 775 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 776 | math_error(regs, error_code, X86_TRAP_MF); |
1da177e4 LT |
777 | } |
778 | ||
e407d620 AH |
779 | dotraplinkage void |
780 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 781 | { |
5778077d | 782 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 783 | math_error(regs, error_code, X86_TRAP_XF); |
1da177e4 LT |
784 | } |
785 | ||
e407d620 AH |
786 | dotraplinkage void |
787 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 788 | { |
d99e1bd1 | 789 | cond_local_irq_enable(regs); |
081f75bb AH |
790 | } |
791 | ||
9326638c | 792 | dotraplinkage void |
aa78bcfa | 793 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 794 | { |
5778077d | 795 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
304bceda | 796 | |
a334fe43 | 797 | #ifdef CONFIG_MATH_EMULATION |
c6ab109f | 798 | if (!boot_cpu_has(X86_FEATURE_FPU) && (read_cr0() & X86_CR0_EM)) { |
d315760f TH |
799 | struct math_emu_info info = { }; |
800 | ||
d99e1bd1 | 801 | cond_local_irq_enable(regs); |
d315760f | 802 | |
aa78bcfa | 803 | info.regs = regs; |
d315760f | 804 | math_emulate(&info); |
a334fe43 | 805 | return; |
7643e9b9 | 806 | } |
a334fe43 | 807 | #endif |
e1884d69 | 808 | fpu__restore(¤t->thread.fpu); /* interrupts still off */ |
a334fe43 | 809 | #ifdef CONFIG_X86_32 |
d99e1bd1 | 810 | cond_local_irq_enable(regs); |
081f75bb | 811 | #endif |
7643e9b9 | 812 | } |
9326638c | 813 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 814 | |
081f75bb | 815 | #ifdef CONFIG_X86_32 |
e407d620 | 816 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
817 | { |
818 | siginfo_t info; | |
6ba3c97a | 819 | |
5778077d | 820 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f8e0870f AH |
821 | local_irq_enable(); |
822 | ||
823 | info.si_signo = SIGILL; | |
824 | info.si_errno = 0; | |
825 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 826 | info.si_addr = NULL; |
c9408265 | 827 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
828 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
829 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
830 | &info); | |
831 | } | |
f8e0870f | 832 | } |
081f75bb | 833 | #endif |
f8e0870f | 834 | |
29c84391 JK |
835 | /* Set of traps needed for early debugging. */ |
836 | void __init early_trap_init(void) | |
837 | { | |
b4d83270 | 838 | /* |
5eca7453 WN |
839 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
840 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
841 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
842 | * stack. Using the original stack works well enough at this | |
843 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 844 | * trap_init(). |
5eca7453 WN |
845 | * |
846 | * We don't need to set trace_idt_table like set_intr_gate(), | |
847 | * since we don't have trace_debug and it will be reset to | |
848 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 849 | */ |
5eca7453 | 850 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 851 | /* int3 can be called from all */ |
5eca7453 | 852 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 853 | #ifdef CONFIG_X86_32 |
25c74b10 | 854 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 855 | #endif |
29c84391 JK |
856 | load_idt(&idt_descr); |
857 | } | |
858 | ||
8170e6be PA |
859 | void __init early_trap_pf_init(void) |
860 | { | |
861 | #ifdef CONFIG_X86_64 | |
25c74b10 | 862 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
863 | #endif |
864 | } | |
865 | ||
1da177e4 LT |
866 | void __init trap_init(void) |
867 | { | |
dbeb2be2 RR |
868 | int i; |
869 | ||
1da177e4 | 870 | #ifdef CONFIG_EISA |
927222b1 | 871 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
872 | |
873 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 874 | EISA_bus = 1; |
927222b1 | 875 | early_iounmap(p, 4); |
1da177e4 LT |
876 | #endif |
877 | ||
25c74b10 | 878 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 879 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 880 | /* int4 can be called from all */ |
c9408265 | 881 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
882 | set_intr_gate(X86_TRAP_BR, bounds); |
883 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
884 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 885 | #ifdef CONFIG_X86_32 |
c9408265 | 886 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 887 | #else |
c9408265 | 888 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 889 | #endif |
25c74b10 SA |
890 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
891 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
892 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 893 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
894 | set_intr_gate(X86_TRAP_GP, general_protection); |
895 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
896 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
897 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 898 | #ifdef CONFIG_X86_MCE |
c9408265 | 899 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 900 | #endif |
25c74b10 | 901 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 902 | |
bb3f0b59 YL |
903 | /* Reserve all the builtin and the syscall vector: */ |
904 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
905 | set_bit(i, used_vectors); | |
906 | ||
081f75bb | 907 | #ifdef CONFIG_IA32_EMULATION |
2cd23553 | 908 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_compat); |
bb3f0b59 | 909 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
910 | #endif |
911 | ||
912 | #ifdef CONFIG_X86_32 | |
a798f091 | 913 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_32); |
51bb9284 | 914 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb | 915 | #endif |
bb3f0b59 | 916 | |
4eefbe79 KC |
917 | /* |
918 | * Set the IDT descriptor to a fixed read-only location, so that the | |
919 | * "sidt" instruction will not leak the location of the kernel, and | |
920 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
921 | * It will be reloaded in cpu_init() */ | |
922 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
923 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
924 | ||
1da177e4 | 925 | /* |
b5964405 | 926 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
927 | */ |
928 | cpu_init(); | |
929 | ||
b4d83270 WN |
930 | /* |
931 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 932 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
933 | * cpu_init() loads TSS. See comments in early_trap_init(). |
934 | */ | |
935 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
936 | /* int3 can be called from all */ | |
937 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
938 | ||
428cf902 | 939 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
940 | |
941 | #ifdef CONFIG_X86_64 | |
629f4f9d | 942 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
943 | set_nmi_gate(X86_TRAP_DB, &debug); |
944 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 945 | #endif |
1da177e4 | 946 | } |