Commit | Line | Data |
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65253636 | 1 | /* |
26dd9fcf IM |
2 | * SGI Visual Workstation support and quirks, unmaintained. |
3 | * | |
65253636 | 4 | * Split out from setup.c by davej@suse.de |
26dd9fcf IM |
5 | * |
6 | * Copyright (C) 1999 Bent Hagemark, Ingo Molnar | |
7 | * | |
8 | * SGI Visual Workstation interrupt controller | |
9 | * | |
10 | * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC | |
11 | * which serves as the main interrupt controller in the system. Non-legacy | |
12 | * hardware in the system uses this controller directly. Legacy devices | |
13 | * are connected to the PIIX4 which in turn has its 8259(s) connected to | |
14 | * a of the Cobalt APIC entry. | |
15 | * | |
16 | * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com | |
17 | * | |
18 | * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru> | |
65253636 | 19 | */ |
65253636 IM |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/smp.h> | |
24 | ||
25 | #include <asm/visws/cobalt.h> | |
26 | #include <asm/visws/piix4.h> | |
27 | #include <asm/arch_hooks.h> | |
3964cd3a | 28 | #include <asm/io_apic.h> |
65253636 IM |
29 | #include <asm/fixmap.h> |
30 | #include <asm/reboot.h> | |
31 | #include <asm/setup.h> | |
32 | #include <asm/e820.h> | |
65253636 IM |
33 | #include <asm/io.h> |
34 | ||
35 | #include <mach_ipi.h> | |
36 | ||
37 | #include "mach_apic.h" | |
38 | ||
26dd9fcf | 39 | #include <linux/kernel_stat.h> |
26dd9fcf | 40 | |
26dd9fcf IM |
41 | #include <asm/i8259.h> |
42 | #include <asm/irq_vectors.h> | |
26dd9fcf | 43 | #include <asm/visws/lithium.h> |
26dd9fcf IM |
44 | |
45 | #include <linux/sched.h> | |
46 | #include <linux/kernel.h> | |
26dd9fcf IM |
47 | #include <linux/pci.h> |
48 | #include <linux/pci_ids.h> | |
49 | ||
f78cb9b1 IM |
50 | extern int no_broadcast; |
51 | ||
26dd9fcf | 52 | #include <asm/apic.h> |
26dd9fcf | 53 | |
65253636 IM |
54 | char visws_board_type = -1; |
55 | char visws_board_rev = -1; | |
56 | ||
57 | int is_visws_box(void) | |
58 | { | |
59 | return visws_board_type >= 0; | |
60 | } | |
61 | ||
3c9cb6de | 62 | static int __init visws_time_init(void) |
65253636 IM |
63 | { |
64 | printk(KERN_INFO "Starting Cobalt Timer system clock\n"); | |
65 | ||
66 | /* Set the countdown value */ | |
67 | co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); | |
68 | ||
69 | /* Start the timer */ | |
70 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); | |
71 | ||
72 | /* Enable (unmask) the timer interrupt */ | |
73 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); | |
74 | ||
75 | /* | |
76 | * Zero return means the generic timer setup code will set up | |
77 | * the standard vector: | |
78 | */ | |
79 | return 0; | |
80 | } | |
81 | ||
3c9cb6de | 82 | static int __init visws_pre_intr_init(void) |
65253636 IM |
83 | { |
84 | init_VISWS_APIC_irqs(); | |
85 | ||
86 | /* | |
87 | * We dont want ISA irqs to be set up by the generic code: | |
88 | */ | |
89 | return 1; | |
90 | } | |
91 | ||
92 | /* Quirk for machine specific memory setup. */ | |
93 | ||
94 | #define MB (1024 * 1024) | |
95 | ||
96 | unsigned long sgivwfb_mem_phys; | |
97 | unsigned long sgivwfb_mem_size; | |
98 | EXPORT_SYMBOL(sgivwfb_mem_phys); | |
99 | EXPORT_SYMBOL(sgivwfb_mem_size); | |
100 | ||
101 | long long mem_size __initdata = 0; | |
102 | ||
3c9cb6de | 103 | static char * __init visws_memory_setup(void) |
65253636 IM |
104 | { |
105 | long long gfx_mem_size = 8 * MB; | |
106 | ||
107 | mem_size = boot_params.alt_mem_k; | |
108 | ||
109 | if (!mem_size) { | |
110 | printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n"); | |
111 | mem_size = 128 * MB; | |
112 | } | |
113 | ||
114 | /* | |
115 | * this hardcodes the graphics memory to 8 MB | |
116 | * it really should be sized dynamically (or at least | |
117 | * set as a boot param) | |
118 | */ | |
119 | if (!sgivwfb_mem_size) { | |
120 | printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n"); | |
121 | sgivwfb_mem_size = 8 * MB; | |
122 | } | |
123 | ||
124 | /* | |
125 | * Trim to nearest MB | |
126 | */ | |
127 | sgivwfb_mem_size &= ~((1 << 20) - 1); | |
128 | sgivwfb_mem_phys = mem_size - gfx_mem_size; | |
129 | ||
130 | e820_add_region(0, LOWMEMSIZE(), E820_RAM); | |
131 | e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM); | |
132 | e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED); | |
133 | ||
134 | return "PROM"; | |
135 | } | |
136 | ||
137 | static void visws_machine_emergency_restart(void) | |
138 | { | |
139 | /* | |
140 | * Visual Workstations restart after this | |
141 | * register is poked on the PIIX4 | |
142 | */ | |
143 | outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT); | |
144 | } | |
145 | ||
146 | static void visws_machine_power_off(void) | |
147 | { | |
148 | unsigned short pm_status; | |
149 | /* extern unsigned int pci_bus0; */ | |
150 | ||
151 | while ((pm_status = inw(PMSTS_PORT)) & 0x100) | |
152 | outw(pm_status, PMSTS_PORT); | |
153 | ||
154 | outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT); | |
155 | ||
156 | mdelay(10); | |
157 | ||
158 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ | |
159 | (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) | |
160 | ||
161 | /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */ | |
162 | outl(PIIX_SPECIAL_STOP, 0xCFC); | |
163 | } | |
164 | ||
3c9cb6de | 165 | static int __init visws_get_smp_config(unsigned int early) |
65253636 IM |
166 | { |
167 | /* | |
168 | * Prevent MP-table parsing by the generic code: | |
169 | */ | |
170 | return 1; | |
171 | } | |
172 | ||
65253636 IM |
173 | /* |
174 | * The Visual Workstation is Intel MP compliant in the hardware | |
175 | * sense, but it doesn't have a BIOS(-configuration table). | |
176 | * No problem for Linux. | |
177 | */ | |
178 | ||
f4f21b71 | 179 | static void __init MP_processor_info(struct mpc_cpu *m) |
65253636 IM |
180 | { |
181 | int ver, logical_apicid; | |
182 | physid_mask_t apic_cpus; | |
183 | ||
184 | if (!(m->mpc_cpuflag & CPU_ENABLED)) | |
185 | return; | |
186 | ||
187 | logical_apicid = m->mpc_apicid; | |
188 | printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n", | |
189 | m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "", | |
190 | m->mpc_apicid, | |
191 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, | |
192 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, | |
193 | m->mpc_apicver); | |
194 | ||
195 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) | |
196 | boot_cpu_physical_apicid = m->mpc_apicid; | |
197 | ||
198 | ver = m->mpc_apicver; | |
199 | if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) { | |
200 | printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n", | |
201 | m->mpc_apicid, MAX_APICS); | |
202 | return; | |
203 | } | |
204 | ||
205 | apic_cpus = apicid_to_cpu_present(m->mpc_apicid); | |
206 | physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus); | |
207 | /* | |
208 | * Validate version | |
209 | */ | |
210 | if (ver == 0x0) { | |
211 | printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! " | |
212 | "fixing up to 0x10. (tell your hw vendor)\n", | |
213 | m->mpc_apicid); | |
214 | ver = 0x10; | |
215 | } | |
216 | apic_version[m->mpc_apicid] = ver; | |
217 | } | |
218 | ||
3c9cb6de | 219 | static int __init visws_find_smp_config(unsigned int reserve) |
65253636 | 220 | { |
f4f21b71 | 221 | struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS); |
65253636 IM |
222 | unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS)); |
223 | ||
224 | if (ncpus > CO_CPU_MAX) { | |
225 | printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n", | |
226 | ncpus, mp); | |
227 | ||
228 | ncpus = CO_CPU_MAX; | |
229 | } | |
230 | ||
23b49c19 MK |
231 | if (ncpus > setup_max_cpus) |
232 | ncpus = setup_max_cpus; | |
65253636 IM |
233 | |
234 | #ifdef CONFIG_X86_LOCAL_APIC | |
235 | smp_found_config = 1; | |
236 | #endif | |
237 | while (ncpus--) | |
238 | MP_processor_info(mp++); | |
239 | ||
240 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
241 | ||
242 | return 1; | |
243 | } | |
244 | ||
3c9cb6de YL |
245 | static int visws_trap_init(void); |
246 | ||
247 | static struct x86_quirks visws_x86_quirks __initdata = { | |
248 | .arch_time_init = visws_time_init, | |
249 | .arch_pre_intr_init = visws_pre_intr_init, | |
250 | .arch_memory_setup = visws_memory_setup, | |
251 | .arch_intr_init = NULL, | |
252 | .arch_trap_init = visws_trap_init, | |
253 | .mach_get_smp_config = visws_get_smp_config, | |
254 | .mach_find_smp_config = visws_find_smp_config, | |
255 | }; | |
65253636 IM |
256 | |
257 | void __init visws_early_detect(void) | |
258 | { | |
259 | int raw; | |
260 | ||
261 | visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) | |
262 | >> PIIX_GPI_BD_SHIFT; | |
263 | ||
264 | if (visws_board_type < 0) | |
265 | return; | |
266 | ||
267 | /* | |
268 | * Install special quirks for timer, interrupt and memory setup: | |
65253636 | 269 | * Fall back to generic behavior for traps: |
3c9cb6de | 270 | * Override generic MP-table parsing: |
65253636 | 271 | */ |
3c9cb6de | 272 | x86_quirks = &visws_x86_quirks; |
65253636 IM |
273 | |
274 | /* | |
275 | * Install reboot quirks: | |
276 | */ | |
277 | pm_power_off = visws_machine_power_off; | |
278 | machine_ops.emergency_restart = visws_machine_emergency_restart; | |
279 | ||
280 | /* | |
281 | * Do not use broadcast IPIs: | |
282 | */ | |
283 | no_broadcast = 0; | |
284 | ||
54ce7f99 IM |
285 | #ifdef CONFIG_X86_IO_APIC |
286 | /* | |
287 | * Turn off IO-APIC detection and initialization: | |
288 | */ | |
289 | skip_ioapic_setup = 1; | |
290 | #endif | |
291 | ||
65253636 IM |
292 | /* |
293 | * Get Board rev. | |
294 | * First, we have to initialize the 307 part to allow us access | |
295 | * to the GPIO registers. Let's map them at 0x0fc0 which is right | |
296 | * after the PIIX4 PM section. | |
297 | */ | |
298 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
299 | outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
300 | ||
301 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
302 | outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ | |
303 | ||
304 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
305 | outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ | |
306 | ||
307 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
308 | outb_p(1, SIO_DATA); /* Enable GPIO registers. */ | |
309 | ||
310 | /* | |
311 | * Now, we have to map the power management section to write | |
312 | * a bit which enables access to the GPIO registers. | |
313 | * What lunatic came up with this shit? | |
314 | */ | |
315 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
316 | outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
317 | ||
318 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
319 | outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ | |
320 | ||
321 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
322 | outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ | |
323 | ||
324 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
325 | outb_p(1, SIO_DATA); /* Enable PM registers. */ | |
326 | ||
327 | /* | |
328 | * Now, write the PM register which enables the GPIO registers. | |
329 | */ | |
330 | outb_p(SIO_PM_FER2, SIO_PM_INDEX); | |
331 | outb_p(SIO_PM_GP_EN, SIO_PM_DATA); | |
332 | ||
333 | /* | |
334 | * Now, initialize the GPIO registers. | |
335 | * We want them all to be inputs which is the | |
336 | * power on default, so let's leave them alone. | |
337 | * So, let's just read the board rev! | |
338 | */ | |
339 | raw = inb_p(SIO_GP_DATA1); | |
340 | raw &= 0x7f; /* 7 bits of valid board revision ID. */ | |
341 | ||
342 | if (visws_board_type == VISWS_320) { | |
343 | if (raw < 0x6) { | |
344 | visws_board_rev = 4; | |
345 | } else if (raw < 0xc) { | |
346 | visws_board_rev = 5; | |
347 | } else { | |
348 | visws_board_rev = 6; | |
349 | } | |
350 | } else if (visws_board_type == VISWS_540) { | |
351 | visws_board_rev = 2; | |
352 | } else { | |
353 | visws_board_rev = raw; | |
354 | } | |
355 | ||
356 | printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n", | |
357 | (visws_board_type == VISWS_320 ? "320" : | |
358 | (visws_board_type == VISWS_540 ? "540" : | |
359 | "unknown")), visws_board_rev); | |
360 | } | |
26dd9fcf IM |
361 | |
362 | #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4) | |
363 | #define BCD (LI_INTB | LI_INTC | LI_INTD) | |
364 | #define ALLDEVS (A01234 | BCD) | |
365 | ||
366 | static __init void lithium_init(void) | |
367 | { | |
368 | set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS); | |
369 | set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS); | |
370 | ||
371 | if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
372 | (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
373 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A'); | |
374 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
375 | } | |
376 | ||
377 | if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
378 | (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
379 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B'); | |
380 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
381 | } | |
382 | ||
383 | li_pcia_write16(LI_PCI_INTEN, ALLDEVS); | |
384 | li_pcib_write16(LI_PCI_INTEN, ALLDEVS); | |
385 | } | |
386 | ||
387 | static __init void cobalt_init(void) | |
388 | { | |
389 | /* | |
390 | * On normal SMP PC this is used only with SMP, but we have to | |
391 | * use it and set it up here to start the Cobalt clock | |
392 | */ | |
393 | set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); | |
394 | setup_local_APIC(); | |
395 | printk(KERN_INFO "Local APIC Version %#x, ID %#x\n", | |
396 | (unsigned int)apic_read(APIC_LVR), | |
397 | (unsigned int)apic_read(APIC_ID)); | |
398 | ||
399 | set_fixmap(FIX_CO_CPU, CO_CPU_PHYS); | |
400 | set_fixmap(FIX_CO_APIC, CO_APIC_PHYS); | |
401 | printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n", | |
402 | co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID)); | |
403 | ||
404 | /* Enable Cobalt APIC being careful to NOT change the ID! */ | |
405 | co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE); | |
406 | ||
407 | printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n", | |
408 | co_apic_read(CO_APIC_ID)); | |
409 | } | |
410 | ||
3c9cb6de | 411 | static int __init visws_trap_init(void) |
26dd9fcf IM |
412 | { |
413 | lithium_init(); | |
414 | cobalt_init(); | |
415 | ||
416 | return 1; | |
417 | } | |
418 | ||
419 | /* | |
420 | * IRQ controller / APIC support: | |
421 | */ | |
422 | ||
423 | static DEFINE_SPINLOCK(cobalt_lock); | |
424 | ||
425 | /* | |
426 | * Set the given Cobalt APIC Redirection Table entry to point | |
427 | * to the given IDT vector/index. | |
428 | */ | |
429 | static inline void co_apic_set(int entry, int irq) | |
430 | { | |
431 | co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR)); | |
432 | co_apic_write(CO_APIC_HI(entry), 0); | |
433 | } | |
434 | ||
435 | /* | |
436 | * Cobalt (IO)-APIC functions to handle PCI devices. | |
437 | */ | |
438 | static inline int co_apic_ide0_hack(void) | |
439 | { | |
440 | extern char visws_board_type; | |
441 | extern char visws_board_rev; | |
442 | ||
443 | if (visws_board_type == VISWS_320 && visws_board_rev == 5) | |
444 | return 5; | |
445 | return CO_APIC_IDE0; | |
446 | } | |
447 | ||
448 | static int is_co_apic(unsigned int irq) | |
449 | { | |
450 | if (IS_CO_APIC(irq)) | |
451 | return CO_APIC(irq); | |
452 | ||
453 | switch (irq) { | |
454 | case 0: return CO_APIC_CPU; | |
455 | case CO_IRQ_IDE0: return co_apic_ide0_hack(); | |
456 | case CO_IRQ_IDE1: return CO_APIC_IDE1; | |
457 | default: return -1; | |
458 | } | |
459 | } | |
460 | ||
461 | ||
462 | /* | |
463 | * This is the SGI Cobalt (IO-)APIC: | |
464 | */ | |
465 | ||
466 | static void enable_cobalt_irq(unsigned int irq) | |
467 | { | |
468 | co_apic_set(is_co_apic(irq), irq); | |
469 | } | |
470 | ||
471 | static void disable_cobalt_irq(unsigned int irq) | |
472 | { | |
473 | int entry = is_co_apic(irq); | |
474 | ||
475 | co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK); | |
476 | co_apic_read(CO_APIC_LO(entry)); | |
477 | } | |
478 | ||
479 | /* | |
480 | * "irq" really just serves to identify the device. Here is where we | |
481 | * map this to the Cobalt APIC entry where it's physically wired. | |
482 | * This is called via request_irq -> setup_irq -> irq_desc->startup() | |
483 | */ | |
484 | static unsigned int startup_cobalt_irq(unsigned int irq) | |
485 | { | |
486 | unsigned long flags; | |
08678b08 | 487 | struct irq_desc *desc = irq_to_desc(irq); |
26dd9fcf IM |
488 | |
489 | spin_lock_irqsave(&cobalt_lock, flags); | |
08678b08 YL |
490 | if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING))) |
491 | desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING); | |
26dd9fcf IM |
492 | enable_cobalt_irq(irq); |
493 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static void ack_cobalt_irq(unsigned int irq) | |
498 | { | |
499 | unsigned long flags; | |
500 | ||
501 | spin_lock_irqsave(&cobalt_lock, flags); | |
502 | disable_cobalt_irq(irq); | |
503 | apic_write(APIC_EOI, APIC_EIO_ACK); | |
504 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
505 | } | |
506 | ||
507 | static void end_cobalt_irq(unsigned int irq) | |
508 | { | |
509 | unsigned long flags; | |
08678b08 | 510 | struct irq_desc *desc = irq_to_desc(irq); |
26dd9fcf IM |
511 | |
512 | spin_lock_irqsave(&cobalt_lock, flags); | |
08678b08 | 513 | if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
26dd9fcf IM |
514 | enable_cobalt_irq(irq); |
515 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
516 | } | |
517 | ||
518 | static struct irq_chip cobalt_irq_type = { | |
519 | .typename = "Cobalt-APIC", | |
520 | .startup = startup_cobalt_irq, | |
521 | .shutdown = disable_cobalt_irq, | |
522 | .enable = enable_cobalt_irq, | |
523 | .disable = disable_cobalt_irq, | |
524 | .ack = ack_cobalt_irq, | |
525 | .end = end_cobalt_irq, | |
526 | }; | |
527 | ||
528 | ||
529 | /* | |
530 | * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt | |
531 | * -- not the manner expected by the code in i8259.c. | |
532 | * | |
533 | * there is a 'master' physical interrupt source that gets sent to | |
534 | * the CPU. But in the chipset there are various 'virtual' interrupts | |
535 | * waiting to be handled. We represent this to Linux through a 'master' | |
536 | * interrupt controller type, and through a special virtual interrupt- | |
537 | * controller. Device drivers only see the virtual interrupt sources. | |
538 | */ | |
539 | static unsigned int startup_piix4_master_irq(unsigned int irq) | |
540 | { | |
541 | init_8259A(0); | |
542 | ||
543 | return startup_cobalt_irq(irq); | |
544 | } | |
545 | ||
546 | static void end_piix4_master_irq(unsigned int irq) | |
547 | { | |
548 | unsigned long flags; | |
549 | ||
550 | spin_lock_irqsave(&cobalt_lock, flags); | |
551 | enable_cobalt_irq(irq); | |
552 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
553 | } | |
554 | ||
555 | static struct irq_chip piix4_master_irq_type = { | |
556 | .typename = "PIIX4-master", | |
557 | .startup = startup_piix4_master_irq, | |
558 | .ack = ack_cobalt_irq, | |
559 | .end = end_piix4_master_irq, | |
560 | }; | |
561 | ||
562 | ||
563 | static struct irq_chip piix4_virtual_irq_type = { | |
564 | .typename = "PIIX4-virtual", | |
565 | .shutdown = disable_8259A_irq, | |
566 | .enable = enable_8259A_irq, | |
567 | .disable = disable_8259A_irq, | |
568 | }; | |
569 | ||
570 | ||
571 | /* | |
572 | * PIIX4-8259 master/virtual functions to handle interrupt requests | |
573 | * from legacy devices: floppy, parallel, serial, rtc. | |
574 | * | |
575 | * None of these get Cobalt APIC entries, neither do they have IDT | |
576 | * entries. These interrupts are purely virtual and distributed from | |
577 | * the 'master' interrupt source: CO_IRQ_8259. | |
578 | * | |
579 | * When the 8259 interrupts its handler figures out which of these | |
580 | * devices is interrupting and dispatches to its handler. | |
581 | * | |
582 | * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/ | |
583 | * enable_irq gets the right irq. This 'master' irq is never directly | |
584 | * manipulated by any driver. | |
585 | */ | |
586 | static irqreturn_t piix4_master_intr(int irq, void *dev_id) | |
587 | { | |
588 | int realirq; | |
589 | irq_desc_t *desc; | |
590 | unsigned long flags; | |
591 | ||
592 | spin_lock_irqsave(&i8259A_lock, flags); | |
593 | ||
594 | /* Find out what's interrupting in the PIIX4 master 8259 */ | |
595 | outb(0x0c, 0x20); /* OCW3 Poll command */ | |
596 | realirq = inb(0x20); | |
597 | ||
598 | /* | |
599 | * Bit 7 == 0 means invalid/spurious | |
600 | */ | |
601 | if (unlikely(!(realirq & 0x80))) | |
602 | goto out_unlock; | |
603 | ||
604 | realirq &= 7; | |
605 | ||
606 | if (unlikely(realirq == 2)) { | |
607 | outb(0x0c, 0xa0); | |
608 | realirq = inb(0xa0); | |
609 | ||
610 | if (unlikely(!(realirq & 0x80))) | |
611 | goto out_unlock; | |
612 | ||
613 | realirq = (realirq & 7) + 8; | |
614 | } | |
615 | ||
616 | /* mask and ack interrupt */ | |
617 | cached_irq_mask |= 1 << realirq; | |
618 | if (unlikely(realirq > 7)) { | |
619 | inb(0xa1); | |
620 | outb(cached_slave_mask, 0xa1); | |
621 | outb(0x60 + (realirq & 7), 0xa0); | |
622 | outb(0x60 + 2, 0x20); | |
623 | } else { | |
624 | inb(0x21); | |
625 | outb(cached_master_mask, 0x21); | |
626 | outb(0x60 + realirq, 0x20); | |
627 | } | |
628 | ||
629 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
630 | ||
08678b08 | 631 | desc = irq_to_desc(realirq); |
26dd9fcf IM |
632 | |
633 | /* | |
634 | * handle this 'virtual interrupt' as a Cobalt one now. | |
635 | */ | |
d6c88a50 | 636 | kstat_incr_irqs_this_cpu(realirq, desc); |
26dd9fcf IM |
637 | |
638 | if (likely(desc->action != NULL)) | |
639 | handle_IRQ_event(realirq, desc->action); | |
640 | ||
641 | if (!(desc->status & IRQ_DISABLED)) | |
642 | enable_8259A_irq(realirq); | |
643 | ||
644 | return IRQ_HANDLED; | |
645 | ||
646 | out_unlock: | |
647 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
648 | return IRQ_NONE; | |
649 | } | |
650 | ||
651 | static struct irqaction master_action = { | |
652 | .handler = piix4_master_intr, | |
653 | .name = "PIIX4-8259", | |
654 | }; | |
655 | ||
656 | static struct irqaction cascade_action = { | |
657 | .handler = no_action, | |
658 | .name = "cascade", | |
659 | }; | |
660 | ||
661 | ||
662 | void init_VISWS_APIC_irqs(void) | |
663 | { | |
664 | int i; | |
665 | ||
666 | for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) { | |
08678b08 YL |
667 | struct irq_desc *desc = irq_to_desc(i); |
668 | ||
669 | desc->status = IRQ_DISABLED; | |
670 | desc->action = 0; | |
671 | desc->depth = 1; | |
26dd9fcf IM |
672 | |
673 | if (i == 0) { | |
08678b08 | 674 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
675 | } |
676 | else if (i == CO_IRQ_IDE0) { | |
08678b08 | 677 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
678 | } |
679 | else if (i == CO_IRQ_IDE1) { | |
08678b08 | 680 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
681 | } |
682 | else if (i == CO_IRQ_8259) { | |
08678b08 | 683 | desc->chip = &piix4_master_irq_type; |
26dd9fcf IM |
684 | } |
685 | else if (i < CO_IRQ_APIC0) { | |
08678b08 | 686 | desc->chip = &piix4_virtual_irq_type; |
26dd9fcf IM |
687 | } |
688 | else if (IS_CO_APIC(i)) { | |
08678b08 | 689 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
690 | } |
691 | } | |
692 | ||
693 | setup_irq(CO_IRQ_8259, &master_action); | |
694 | setup_irq(2, &cascade_action); | |
695 | } |