Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
c767a54b JP |
6 | |
7 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
8 | ||
dc1e35c6 SS |
9 | #include <linux/bootmem.h> |
10 | #include <linux/compat.h> | |
7e7ce87f | 11 | #include <linux/cpu.h> |
dc1e35c6 | 12 | #include <asm/i387.h> |
1361b83a | 13 | #include <asm/fpu-internal.h> |
72a671ce | 14 | #include <asm/sigframe.h> |
6152e4b1 | 15 | #include <asm/xcr.h> |
dc1e35c6 SS |
16 | |
17 | /* | |
18 | * Supported feature mask by the CPU and the kernel. | |
19 | */ | |
6152e4b1 | 20 | u64 pcntxt_mask; |
dc1e35c6 | 21 | |
45c2d7f4 RR |
22 | /* |
23 | * Represents init state for the supported extended state. | |
24 | */ | |
304bceda | 25 | struct xsave_struct *init_xstate_buf; |
45c2d7f4 | 26 | |
72a671ce | 27 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
7e7ce87f | 28 | static unsigned int *xstate_offsets, *xstate_sizes; |
8ff925e1 | 29 | static unsigned int xstate_comp_offsets[sizeof(pcntxt_mask)*8]; |
7e7ce87f | 30 | static unsigned int xstate_features; |
a1488f8b | 31 | |
29104e10 SS |
32 | /* |
33 | * If a processor implementation discern that a processor state component is | |
34 | * in its initialized state it may modify the corresponding bit in the | |
35 | * xsave_hdr.xstate_bv as '0', with out modifying the corresponding memory | |
36 | * layout in the case of xsaveopt. While presenting the xstate information to | |
37 | * the user, we always ensure that the memory layout of a feature will be in | |
38 | * the init state if the corresponding header bit is zero. This is to ensure | |
39 | * that the user doesn't see some stale state in the memory layout during | |
40 | * signal handling, debugging etc. | |
41 | */ | |
42 | void __sanitize_i387_state(struct task_struct *tsk) | |
43 | { | |
29104e10 | 44 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave; |
72a671ce SS |
45 | int feature_bit = 0x2; |
46 | u64 xstate_bv; | |
29104e10 SS |
47 | |
48 | if (!fx) | |
49 | return; | |
50 | ||
29104e10 SS |
51 | xstate_bv = tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv; |
52 | ||
53 | /* | |
54 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 55 | * to do for us, as the memory layout is up to date. |
29104e10 SS |
56 | */ |
57 | if ((xstate_bv & pcntxt_mask) == pcntxt_mask) | |
58 | return; | |
59 | ||
60 | /* | |
61 | * FP is in init state | |
62 | */ | |
63 | if (!(xstate_bv & XSTATE_FP)) { | |
64 | fx->cwd = 0x37f; | |
65 | fx->swd = 0; | |
66 | fx->twd = 0; | |
67 | fx->fop = 0; | |
68 | fx->rip = 0; | |
69 | fx->rdp = 0; | |
70 | memset(&fx->st_space[0], 0, 128); | |
71 | } | |
72 | ||
73 | /* | |
74 | * SSE is in init state | |
75 | */ | |
76 | if (!(xstate_bv & XSTATE_SSE)) | |
77 | memset(&fx->xmm_space[0], 0, 256); | |
78 | ||
79 | xstate_bv = (pcntxt_mask & ~xstate_bv) >> 2; | |
80 | ||
81 | /* | |
82 | * Update all the other memory layouts for which the corresponding | |
83 | * header bit is in the init state. | |
84 | */ | |
85 | while (xstate_bv) { | |
86 | if (xstate_bv & 0x1) { | |
87 | int offset = xstate_offsets[feature_bit]; | |
88 | int size = xstate_sizes[feature_bit]; | |
89 | ||
90 | memcpy(((void *) fx) + offset, | |
91 | ((void *) init_xstate_buf) + offset, | |
92 | size); | |
93 | } | |
94 | ||
95 | xstate_bv >>= 1; | |
96 | feature_bit++; | |
97 | } | |
98 | } | |
99 | ||
c37b5efe SS |
100 | /* |
101 | * Check for the presence of extended state information in the | |
102 | * user fpstate pointer in the sigcontext. | |
103 | */ | |
72a671ce SS |
104 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
105 | void __user *fpstate, | |
106 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
107 | { |
108 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
109 | sizeof(struct xsave_hdr_struct); | |
110 | unsigned int magic2; | |
c37b5efe | 111 | |
72a671ce SS |
112 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
113 | return -1; | |
c37b5efe | 114 | |
72a671ce SS |
115 | /* Check for the first magic field and other error scenarios. */ |
116 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
117 | fx_sw->xstate_size < min_xstate_size || | |
118 | fx_sw->xstate_size > xstate_size || | |
119 | fx_sw->xstate_size > fx_sw->extended_size) | |
120 | return -1; | |
c37b5efe | 121 | |
c37b5efe SS |
122 | /* |
123 | * Check for the presence of second magic word at the end of memory | |
124 | * layout. This detects the case where the user just copied the legacy | |
125 | * fpstate layout with out copying the extended state information | |
126 | * in the memory layout. | |
127 | */ | |
72a671ce SS |
128 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
129 | || magic2 != FP_XSTATE_MAGIC2) | |
130 | return -1; | |
c37b5efe SS |
131 | |
132 | return 0; | |
133 | } | |
134 | ||
ab513701 SS |
135 | /* |
136 | * Signal frame handlers. | |
137 | */ | |
72a671ce SS |
138 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
139 | { | |
140 | if (use_fxsr()) { | |
141 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
142 | struct user_i387_ia32_struct env; | |
143 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 144 | |
72a671ce SS |
145 | convert_from_fxsr(&env, tsk); |
146 | ||
147 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
148 | __put_user(xsave->i387.swd, &fp->status) || | |
149 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
150 | return -1; | |
151 | } else { | |
152 | struct i387_fsave_struct __user *fp = buf; | |
153 | u32 swd; | |
154 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
155 | return -1; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 162 | { |
72a671ce SS |
163 | struct xsave_struct __user *x = buf; |
164 | struct _fpx_sw_bytes *sw_bytes; | |
165 | u32 xstate_bv; | |
166 | int err; | |
ab513701 | 167 | |
72a671ce SS |
168 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
169 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
170 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 171 | |
72a671ce SS |
172 | if (!use_xsave()) |
173 | return err; | |
ab513701 | 174 | |
72a671ce | 175 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 176 | |
72a671ce SS |
177 | /* |
178 | * Read the xstate_bv which we copied (directly from the cpu or | |
179 | * from the state in task struct) to the user buffers. | |
180 | */ | |
181 | err |= __get_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv); | |
06c38d5e | 182 | |
72a671ce SS |
183 | /* |
184 | * For legacy compatible, we always set FP/SSE bits in the bit | |
185 | * vector while saving the state to the user context. This will | |
186 | * enable us capturing any changes(during sigreturn) to | |
187 | * the FP/SSE bits by the legacy applications which don't touch | |
188 | * xstate_bv in the xsave header. | |
189 | * | |
190 | * xsave aware apps can change the xstate_bv in the xsave | |
191 | * header as well as change any contents in the memory layout. | |
192 | * xrestore as part of sigreturn will capture all the changes. | |
193 | */ | |
194 | xstate_bv |= XSTATE_FPSSE; | |
c37b5efe | 195 | |
72a671ce SS |
196 | err |= __put_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv); |
197 | ||
198 | return err; | |
199 | } | |
200 | ||
201 | static inline int save_user_xstate(struct xsave_struct __user *buf) | |
202 | { | |
203 | int err; | |
204 | ||
205 | if (use_xsave()) | |
206 | err = xsave_user(buf); | |
207 | else if (use_fxsr()) | |
208 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
209 | else | |
210 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
211 | ||
212 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
213 | err = -EFAULT; | |
214 | return err; | |
215 | } | |
216 | ||
217 | /* | |
218 | * Save the fpu, extended register state to the user signal frame. | |
219 | * | |
220 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
221 | * state is copied. | |
222 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
223 | * | |
224 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
225 | * buf != buf_fx for 32-bit frames with fxstate. | |
226 | * | |
227 | * If the fpu, extended register state is live, save the state directly | |
228 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
229 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
230 | * | |
231 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
232 | * the aligned state at 'buf_fx'. | |
233 | * | |
234 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
235 | * indicating the absence/presence of the extended state to the user. | |
236 | */ | |
237 | int save_xstate_sig(void __user *buf, void __user *buf_fx, int size) | |
238 | { | |
239 | struct xsave_struct *xsave = ¤t->thread.fpu.state->xsave; | |
240 | struct task_struct *tsk = current; | |
241 | int ia32_fxstate = (buf != buf_fx); | |
242 | ||
243 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
244 | config_enabled(CONFIG_IA32_EMULATION)); | |
245 | ||
246 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
247 | return -EACCES; | |
248 | ||
60e019eb | 249 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
250 | return fpregs_soft_get(current, NULL, 0, |
251 | sizeof(struct user_i387_ia32_struct), NULL, | |
252 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
253 | ||
254 | if (user_has_fpu()) { | |
255 | /* Save the live register state to the user directly. */ | |
256 | if (save_user_xstate(buf_fx)) | |
257 | return -1; | |
258 | /* Update the thread's fxstate to save the fsave header. */ | |
259 | if (ia32_fxstate) | |
260 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 261 | } else { |
29104e10 | 262 | sanitize_i387_state(tsk); |
72a671ce | 263 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
264 | return -1; |
265 | } | |
c37b5efe | 266 | |
72a671ce SS |
267 | /* Save the fsave header for the 32-bit frames. */ |
268 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
269 | return -1; | |
06c38d5e | 270 | |
72a671ce SS |
271 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
272 | return -1; | |
273 | ||
72a671ce SS |
274 | return 0; |
275 | } | |
c37b5efe | 276 | |
72a671ce SS |
277 | static inline void |
278 | sanitize_restored_xstate(struct task_struct *tsk, | |
279 | struct user_i387_ia32_struct *ia32_env, | |
280 | u64 xstate_bv, int fx_only) | |
281 | { | |
282 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
283 | struct xsave_hdr_struct *xsave_hdr = &xsave->xsave_hdr; | |
c37b5efe | 284 | |
72a671ce SS |
285 | if (use_xsave()) { |
286 | /* These bits must be zero. */ | |
7e7ce87f | 287 | memset(xsave_hdr->reserved, 0, 48); |
04944b79 SS |
288 | |
289 | /* | |
72a671ce SS |
290 | * Init the state that is not present in the memory |
291 | * layout and not enabled by the OS. | |
04944b79 | 292 | */ |
72a671ce SS |
293 | if (fx_only) |
294 | xsave_hdr->xstate_bv = XSTATE_FPSSE; | |
295 | else | |
296 | xsave_hdr->xstate_bv &= (pcntxt_mask & xstate_bv); | |
297 | } | |
04944b79 | 298 | |
72a671ce | 299 | if (use_fxsr()) { |
04944b79 | 300 | /* |
72a671ce SS |
301 | * mscsr reserved bits must be masked to zero for security |
302 | * reasons. | |
04944b79 | 303 | */ |
72a671ce | 304 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 305 | |
72a671ce | 306 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 307 | } |
ab513701 SS |
308 | } |
309 | ||
c37b5efe | 310 | /* |
72a671ce | 311 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 312 | */ |
72a671ce | 313 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 314 | { |
72a671ce SS |
315 | if (use_xsave()) { |
316 | if ((unsigned long)buf % 64 || fx_only) { | |
317 | u64 init_bv = pcntxt_mask & ~XSTATE_FPSSE; | |
318 | xrstor_state(init_xstate_buf, init_bv); | |
e139e955 | 319 | return fxrstor_user(buf); |
72a671ce SS |
320 | } else { |
321 | u64 init_bv = pcntxt_mask & ~xbv; | |
322 | if (unlikely(init_bv)) | |
323 | xrstor_state(init_xstate_buf, init_bv); | |
324 | return xrestore_user(buf, xbv); | |
325 | } | |
326 | } else if (use_fxsr()) { | |
e139e955 | 327 | return fxrstor_user(buf); |
72a671ce | 328 | } else |
e139e955 | 329 | return frstor_user(buf); |
c37b5efe SS |
330 | } |
331 | ||
72a671ce | 332 | int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 333 | { |
72a671ce | 334 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 335 | struct task_struct *tsk = current; |
72a671ce SS |
336 | int state_size = xstate_size; |
337 | u64 xstate_bv = 0; | |
338 | int fx_only = 0; | |
339 | ||
340 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
341 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
342 | |
343 | if (!buf) { | |
304bceda | 344 | drop_init_fpu(tsk); |
ab513701 | 345 | return 0; |
72a671ce SS |
346 | } |
347 | ||
348 | if (!access_ok(VERIFY_READ, buf, size)) | |
349 | return -EACCES; | |
350 | ||
351 | if (!used_math() && init_fpu(tsk)) | |
352 | return -1; | |
ab513701 | 353 | |
60e019eb | 354 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
355 | return fpregs_soft_set(current, NULL, |
356 | 0, sizeof(struct user_i387_ia32_struct), | |
357 | NULL, buf) != 0; | |
ab513701 | 358 | |
72a671ce SS |
359 | if (use_xsave()) { |
360 | struct _fpx_sw_bytes fx_sw_user; | |
361 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
362 | /* | |
363 | * Couldn't find the extended state information in the | |
364 | * memory layout. Restore just the FP/SSE and init all | |
365 | * the other extended state. | |
366 | */ | |
367 | state_size = sizeof(struct i387_fxsave_struct); | |
368 | fx_only = 1; | |
369 | } else { | |
370 | state_size = fx_sw_user.xstate_size; | |
371 | xstate_bv = fx_sw_user.xstate_bv; | |
372 | } | |
373 | } | |
374 | ||
375 | if (ia32_fxstate) { | |
376 | /* | |
377 | * For 32-bit frames with fxstate, copy the user state to the | |
378 | * thread's fpu state, reconstruct fxstate from the fsave | |
379 | * header. Sanitize the copied state etc. | |
380 | */ | |
381 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
382 | struct user_i387_ia32_struct env; | |
304bceda | 383 | int err = 0; |
72a671ce | 384 | |
304bceda SS |
385 | /* |
386 | * Drop the current fpu which clears used_math(). This ensures | |
387 | * that any context-switch during the copy of the new state, | |
388 | * avoids the intermediate state from getting restored/saved. | |
389 | * Thus avoiding the new restored state from getting corrupted. | |
390 | * We will be ready to restore/save the state only after | |
391 | * set_used_math() is again set. | |
392 | */ | |
e9625917 | 393 | drop_fpu(tsk); |
72a671ce SS |
394 | |
395 | if (__copy_from_user(xsave, buf_fx, state_size) || | |
304bceda SS |
396 | __copy_from_user(&env, buf, sizeof(env))) { |
397 | err = -1; | |
398 | } else { | |
399 | sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only); | |
400 | set_used_math(); | |
401 | } | |
72a671ce | 402 | |
df24fb85 ON |
403 | if (use_eager_fpu()) { |
404 | preempt_disable(); | |
304bceda | 405 | math_state_restore(); |
df24fb85 ON |
406 | preempt_enable(); |
407 | } | |
304bceda SS |
408 | |
409 | return err; | |
72a671ce | 410 | } else { |
ab513701 | 411 | /* |
72a671ce SS |
412 | * For 64-bit frames and 32-bit fsave frames, restore the user |
413 | * state to the registers directly (with exceptions handled). | |
ab513701 | 414 | */ |
72a671ce SS |
415 | user_fpu_begin(); |
416 | if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) { | |
304bceda | 417 | drop_init_fpu(tsk); |
72a671ce SS |
418 | return -1; |
419 | } | |
ab513701 | 420 | } |
72a671ce SS |
421 | |
422 | return 0; | |
ab513701 | 423 | } |
ab513701 | 424 | |
c37b5efe SS |
425 | /* |
426 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
427 | * the presence of the extended state information in the memory layout | |
428 | * pointed by the fpstate pointer in the sigcontext. | |
429 | * This will be saved when ever the FP and extended state context is | |
430 | * saved on the user stack during the signal handler delivery to the user. | |
431 | */ | |
8bcad30f | 432 | static void prepare_fx_sw_frame(void) |
c37b5efe | 433 | { |
72a671ce SS |
434 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
435 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 436 | |
72a671ce SS |
437 | if (config_enabled(CONFIG_X86_32)) |
438 | size += fsave_header_size; | |
c37b5efe SS |
439 | |
440 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 441 | fx_sw_reserved.extended_size = size; |
6152e4b1 | 442 | fx_sw_reserved.xstate_bv = pcntxt_mask; |
c37b5efe | 443 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 444 | |
72a671ce SS |
445 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
446 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
447 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
448 | } | |
449 | } | |
3c1c7f10 | 450 | |
dc1e35c6 SS |
451 | /* |
452 | * Enable the extended processor state save/restore feature | |
453 | */ | |
1cff92d8 | 454 | static inline void xstate_enable(void) |
dc1e35c6 | 455 | { |
dc1e35c6 | 456 | set_in_cr4(X86_CR4_OSXSAVE); |
6152e4b1 | 457 | xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); |
dc1e35c6 SS |
458 | } |
459 | ||
a1488f8b SS |
460 | /* |
461 | * Record the offsets and sizes of different state managed by the xsave | |
462 | * memory layout. | |
463 | */ | |
4995b9db | 464 | static void __init setup_xstate_features(void) |
a1488f8b SS |
465 | { |
466 | int eax, ebx, ecx, edx, leaf = 0x2; | |
467 | ||
468 | xstate_features = fls64(pcntxt_mask); | |
469 | xstate_offsets = alloc_bootmem(xstate_features * sizeof(int)); | |
470 | xstate_sizes = alloc_bootmem(xstate_features * sizeof(int)); | |
471 | ||
472 | do { | |
ee813d53 | 473 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
474 | |
475 | if (eax == 0) | |
476 | break; | |
477 | ||
478 | xstate_offsets[leaf] = ebx; | |
479 | xstate_sizes[leaf] = eax; | |
480 | ||
481 | leaf++; | |
482 | } while (1); | |
483 | } | |
484 | ||
7496d645 FY |
485 | /* |
486 | * This function sets up offsets and sizes of all extended states in | |
487 | * xsave area. This supports both standard format and compacted format | |
488 | * of the xsave aread. | |
489 | * | |
490 | * Input: void | |
491 | * Output: void | |
492 | */ | |
493 | void setup_xstate_comp(void) | |
494 | { | |
8ff925e1 | 495 | unsigned int xstate_comp_sizes[sizeof(pcntxt_mask)*8]; |
7496d645 FY |
496 | int i; |
497 | ||
8ff925e1 FY |
498 | /* |
499 | * The FP xstates and SSE xstates are legacy states. They are always | |
500 | * in the fixed offsets in the xsave area in either compacted form | |
501 | * or standard form. | |
502 | */ | |
503 | xstate_comp_offsets[0] = 0; | |
504 | xstate_comp_offsets[1] = offsetof(struct i387_fxsave_struct, xmm_space); | |
7496d645 FY |
505 | |
506 | if (!cpu_has_xsaves) { | |
507 | for (i = 2; i < xstate_features; i++) { | |
508 | if (test_bit(i, (unsigned long *)&pcntxt_mask)) { | |
509 | xstate_comp_offsets[i] = xstate_offsets[i]; | |
510 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
511 | } | |
512 | } | |
513 | return; | |
514 | } | |
515 | ||
516 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
517 | ||
518 | for (i = 2; i < xstate_features; i++) { | |
519 | if (test_bit(i, (unsigned long *)&pcntxt_mask)) | |
520 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
521 | else | |
522 | xstate_comp_sizes[i] = 0; | |
523 | ||
524 | if (i > 2) | |
525 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
526 | + xstate_comp_sizes[i-1]; | |
527 | ||
528 | } | |
529 | } | |
530 | ||
dc1e35c6 SS |
531 | /* |
532 | * setup the xstate image representing the init state | |
533 | */ | |
5d2bd700 | 534 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 535 | { |
29104e10 SS |
536 | /* |
537 | * Setup init_xstate_buf to represent the init state of | |
538 | * all the features managed by the xsave | |
539 | */ | |
10340ae1 SS |
540 | init_xstate_buf = alloc_bootmem_align(xstate_size, |
541 | __alignof__(struct xsave_struct)); | |
5d2bd700 SS |
542 | fx_finit(&init_xstate_buf->i387); |
543 | ||
544 | if (!cpu_has_xsave) | |
545 | return; | |
546 | ||
547 | setup_xstate_features(); | |
a1488f8b | 548 | |
47c2f292 FY |
549 | if (cpu_has_xsaves) { |
550 | init_xstate_buf->xsave_hdr.xcomp_bv = | |
551 | (u64)1 << 63 | pcntxt_mask; | |
552 | init_xstate_buf->xsave_hdr.xstate_bv = pcntxt_mask; | |
553 | } | |
554 | ||
29104e10 SS |
555 | /* |
556 | * Init all the features state with header_bv being 0x0 | |
557 | */ | |
47c2f292 | 558 | xrstor_state_booting(init_xstate_buf, -1); |
29104e10 SS |
559 | /* |
560 | * Dump the init state again. This is to identify the init state | |
561 | * of any feature which is not represented by all zero's. | |
562 | */ | |
47c2f292 | 563 | xsave_state_booting(init_xstate_buf, -1); |
dc1e35c6 SS |
564 | } |
565 | ||
e0022981 | 566 | static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO; |
5d2bd700 SS |
567 | static int __init eager_fpu_setup(char *s) |
568 | { | |
569 | if (!strcmp(s, "on")) | |
e0022981 | 570 | eagerfpu = ENABLE; |
5d2bd700 | 571 | else if (!strcmp(s, "off")) |
e0022981 SS |
572 | eagerfpu = DISABLE; |
573 | else if (!strcmp(s, "auto")) | |
574 | eagerfpu = AUTO; | |
5d2bd700 SS |
575 | return 1; |
576 | } | |
577 | __setup("eagerfpu=", eager_fpu_setup); | |
578 | ||
7e7ce87f FY |
579 | |
580 | /* | |
581 | * Calculate total size of enabled xstates in XCR0/pcntxt_mask. | |
582 | */ | |
583 | static void __init init_xstate_size(void) | |
584 | { | |
585 | unsigned int eax, ebx, ecx, edx; | |
586 | int i; | |
587 | ||
588 | if (!cpu_has_xsaves) { | |
589 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
590 | xstate_size = ebx; | |
591 | return; | |
592 | } | |
593 | ||
594 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
595 | for (i = 2; i < 64; i++) { | |
596 | if (test_bit(i, (unsigned long *)&pcntxt_mask)) { | |
597 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); | |
598 | xstate_size += eax; | |
599 | } | |
600 | } | |
601 | } | |
602 | ||
dc1e35c6 SS |
603 | /* |
604 | * Enable and initialize the xsave feature. | |
605 | */ | |
1cff92d8 | 606 | static void __init xstate_enable_boot_cpu(void) |
dc1e35c6 SS |
607 | { |
608 | unsigned int eax, ebx, ecx, edx; | |
609 | ||
ee813d53 RR |
610 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
611 | WARN(1, KERN_ERR "XSTATE_CPUID missing\n"); | |
612 | return; | |
613 | } | |
614 | ||
615 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
6152e4b1 | 616 | pcntxt_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 617 | |
6152e4b1 | 618 | if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
c767a54b | 619 | pr_err("FP/SSE not shown under xsave features 0x%llx\n", |
6152e4b1 | 620 | pcntxt_mask); |
dc1e35c6 SS |
621 | BUG(); |
622 | } | |
623 | ||
624 | /* | |
a30469e7 | 625 | * Support only the state known to OS. |
dc1e35c6 | 626 | */ |
6152e4b1 | 627 | pcntxt_mask = pcntxt_mask & XCNTXT_MASK; |
97e80a70 | 628 | |
1cff92d8 | 629 | xstate_enable(); |
dc1e35c6 SS |
630 | |
631 | /* | |
632 | * Recompute the context size for enabled features | |
633 | */ | |
7e7ce87f | 634 | init_xstate_size(); |
dc1e35c6 | 635 | |
5b3efd50 | 636 | update_regset_xstate_info(xstate_size, pcntxt_mask); |
c37b5efe | 637 | prepare_fx_sw_frame(); |
5d2bd700 | 638 | setup_init_fpu_buf(); |
dc1e35c6 | 639 | |
e0022981 SS |
640 | /* Auto enable eagerfpu for xsaveopt */ |
641 | if (cpu_has_xsaveopt && eagerfpu != DISABLE) | |
642 | eagerfpu = ENABLE; | |
212b0212 | 643 | |
e7d820a5 QR |
644 | if (pcntxt_mask & XSTATE_EAGER) { |
645 | if (eagerfpu == DISABLE) { | |
646 | pr_err("eagerfpu not present, disabling some xstate features: 0x%llx\n", | |
647 | pcntxt_mask & XSTATE_EAGER); | |
648 | pcntxt_mask &= ~XSTATE_EAGER; | |
649 | } else { | |
650 | eagerfpu = ENABLE; | |
651 | } | |
652 | } | |
653 | ||
7e7ce87f FY |
654 | pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x using %s\n", |
655 | pcntxt_mask, xstate_size, | |
656 | cpu_has_xsaves ? "compacted form" : "standard form"); | |
dc1e35c6 | 657 | } |
82d4150c | 658 | |
1cff92d8 PA |
659 | /* |
660 | * For the very first instance, this calls xstate_enable_boot_cpu(); | |
661 | * for all subsequent instances, this calls xstate_enable(). | |
662 | * | |
663 | * This is somewhat obfuscated due to the lack of powerful enough | |
664 | * overrides for the section checks. | |
665 | */ | |
148f9bb8 | 666 | void xsave_init(void) |
82d4150c | 667 | { |
1cff92d8 PA |
668 | static __refdata void (*next_func)(void) = xstate_enable_boot_cpu; |
669 | void (*this_func)(void); | |
670 | ||
0e49bf66 RR |
671 | if (!cpu_has_xsave) |
672 | return; | |
673 | ||
1cff92d8 | 674 | this_func = next_func; |
5d2bd700 | 675 | next_func = xstate_enable; |
1cff92d8 | 676 | this_func(); |
82d4150c | 677 | } |
5d2bd700 SS |
678 | |
679 | static inline void __init eager_fpu_init_bp(void) | |
680 | { | |
681 | current->thread.fpu.state = | |
682 | alloc_bootmem_align(xstate_size, __alignof__(struct xsave_struct)); | |
683 | if (!init_xstate_buf) | |
684 | setup_init_fpu_buf(); | |
685 | } | |
686 | ||
148f9bb8 | 687 | void eager_fpu_init(void) |
5d2bd700 SS |
688 | { |
689 | static __refdata void (*boot_func)(void) = eager_fpu_init_bp; | |
690 | ||
691 | clear_used_math(); | |
692 | current_thread_info()->status = 0; | |
e0022981 SS |
693 | |
694 | if (eagerfpu == ENABLE) | |
695 | setup_force_cpu_cap(X86_FEATURE_EAGER_FPU); | |
696 | ||
5d2bd700 SS |
697 | if (!cpu_has_eager_fpu) { |
698 | stts(); | |
699 | return; | |
700 | } | |
701 | ||
702 | if (boot_func) { | |
703 | boot_func(); | |
704 | boot_func = NULL; | |
705 | } | |
706 | ||
707 | /* | |
708 | * This is same as math_state_restore(). But use_xsave() is | |
709 | * not yet patched to use math_state_restore(). | |
710 | */ | |
711 | init_fpu(current); | |
712 | __thread_fpu_begin(current); | |
713 | if (cpu_has_xsave) | |
714 | xrstor_state(init_xstate_buf, -1); | |
715 | else | |
716 | fxrstor_checking(&init_xstate_buf->i387); | |
717 | } | |
7496d645 FY |
718 | |
719 | /* | |
720 | * Given the xsave area and a state inside, this function returns the | |
721 | * address of the state. | |
722 | * | |
723 | * This is the API that is called to get xstate address in either | |
724 | * standard format or compacted format of xsave area. | |
725 | * | |
726 | * Inputs: | |
727 | * xsave: base address of the xsave area; | |
728 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
729 | * etc.) | |
730 | * Output: | |
731 | * address of the state in the xsave area. | |
732 | */ | |
733 | void *get_xsave_addr(struct xsave_struct *xsave, int xstate) | |
734 | { | |
735 | int feature = fls64(xstate) - 1; | |
736 | if (!test_bit(feature, (unsigned long *)&pcntxt_mask)) | |
737 | return NULL; | |
738 | ||
739 | return (void *)xsave + xstate_comp_offsets[feature]; | |
740 | } |